sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

make it so that you can do a standard switch without the caches option. this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache.

Browse source 
--HG--
extra : convert_revision : d733de7ebb362bbd7376a0235ee7f117df2d6d37
This commit is contained in:
Lisa Hsu 2006-11-01 11:49:39 -05:00
parent 9ef8bf74c7
commit 7665be4f70
1 changed files with 7 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
configs/common/Simulation.py
View file

@ -64,9 +64,16 @@ def run(options, root, testsys):
switch_cpus_1[i].workload = testsys.cpu[i].workload
switch_cpus[i].clock = testsys.cpu[0].clock
switch_cpus_1[i].clock = testsys.cpu[0].clock
## add caches to the warmup timing CPU (which will be
## xferred to O3 when you switch again)
if options.caches:
switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
else: # O3 CPU must have a cache to work.
switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
switch_cpus_1[i].connectMemPorts(testsys.membus)
switch_cpus[i].connectMemPorts(testsys.membus)