More restructuring of regression tests.

Moving work back to zizzer...

configs/common/FSConfig.py:
configs/test/fs.py:
    Move CPU connections out of makeLinuxAlphaSystem()
src/python/m5/objects/BaseCPU.py:
    Create default TLBs in full system.
    Move utility cache functions here.
src/python/m5/objects/O3CPU.py:
    Add _mem_ports
tests/run.py:
    Add binpath()
    Change maxtick default to 'forever'
tests/simple-atomic.py:
    Use connectmemPorts()
tests/simple-timing.py:
    Fix up.

--HG--
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.ini => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.out => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.out
rename : tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr
rename : tests/quick/eio1/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
rename : tests/quick/eio1/test.py => tests/quick/20.eio-short/test.py
rename : configs/test/hello => tests/test-progs/hello/bin/alpha/linux/hello
rename : configs/test/hello_mips => tests/test-progs/hello/bin/mips/linux/hello_mips
rename : configs/test/sparc_tests/hello_sparc => tests/test-progs/hello/bin/sparc/bin
extra : convert_revision : 1f891392ecc11ffcc3b3182fa673c401c0efc8a5

configs/common/FSConfig.py

@@ -31,7 +31,6 @@ from m5 import makeList
 from m5.objects import *
 from Benchmarks import *
 from FullO3Config import *
-from Util import *
 
 class CowIdeDisk(IdeDisk):
     image = CowDiskImage(child=RawDiskImage(read_only=True),
@@ -47,7 +46,7 @@ class BaseTsunami(Tsunami):
     ide = IdeController(disks=[Parent.disk0, Parent.disk2],
                         pci_func=0, pci_dev=0, pci_bus=0)
 
-def makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache=None):
+def makeLinuxAlphaSystem(mem_mode, mdesc):
     self = LinuxAlphaSystem()
     self.readfile = mdesc.script()
     self.iobus = Bus(bus_id=0)
@@ -72,13 +71,7 @@ def makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache
     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
                                                read_only = True))
     self.intrctrl = IntrControl()
-    self.cpu = cpu
     self.mem_mode = mem_mode
-    connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
-    for each_cpu in makeList(self.cpu):
-        each_cpu.itb = AlphaITB()
-        each_cpu.dtb = AlphaDTB()
-    self.cpu.clock = '2GHz'
     self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
     self.kernel = binary('vmlinux')
     self.pal = binary('ts_osfpal')

configs/test/fs.py

@@ -5,7 +5,6 @@ from m5.objects import *
 m5.AddToPath('../common')
 from FSConfig import *
 from SysPaths import *
-from Util import *
 from Benchmarks import *
 
 parser = optparse.OptionParser()
@@ -50,12 +49,15 @@ if options.benchmark:
     bm = Benchmarks[options.benchmark]
 
     if len(bm) == 2:
-        root = makeDualRoot(makeLinuxAlphaSystem(cpu, mem_mode, bm[0]),
-                            makeLinuxAlphaSystem(cpu2, mem_mode, bm[1]))
-
+        s1 = makeLinuxAlphaSystem(mem_mode, bm[0])
+        s2 = makeLinuxAlphaSystem(mem_mode, bm[1])
+        cpu.connectMemPorts(s1.membus)
+        cpu2.connectMemPorts(s2.membus)
+        root = makeDualRoot(s1, s2)
     elif len(bm) == 1:
         root = Root(clock = '1THz',
-                    system = makeLinuxAlphaSystem(cpu, mem_mode, bm[0]))
+                    system = makeLinuxAlphaSystem(mem_mode, bm[0]))
+        cpu.connectMemPorts(root.system.membus)
     else:
         print "Error I don't know how to create more than 2 systems."
         sys.exit(1)

src/python/m5/objects/BaseCPU.py

@@ -1,5 +1,7 @@
 from m5 import build_env
 from m5.config import *
+from AlphaTLB import AlphaDTB, AlphaITB
+from Bus import Bus
 
 class BaseCPU(SimObject):
     type = 'BaseCPU'
@@ -8,8 +10,8 @@ class BaseCPU(SimObject):
 
     system = Param.System(Parent.any, "system object")
     if build_env['FULL_SYSTEM']:
-        dtb = Param.AlphaDTB("Data TLB")
-        itb = Param.AlphaITB("Instruction TLB")
+        dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
+        itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
         cpu_id = Param.Int(-1, "CPU identifier")
     else:
         workload = VectorParam.Process("processes to run")
@@ -27,3 +29,25 @@ class BaseCPU(SimObject):
         "defer registration with system (for sampling)")
 
     clock = Param.Clock(Parent.clock, "clock speed")
+
+    _mem_ports = []
+
+    def connectMemPorts(self, bus):
+        for p in self._mem_ports:
+            exec('self.%s = bus.port' % p)
+
+    def addPrivateSplitL1Caches(self, ic, dc):
+        assert(len(self._mem_ports) == 2)
+        self.icache = ic
+        self.dcache = dc
+        self.icache_port = ic.cpu_side
+        self.dcache_port = dc.cpu_side
+        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+
+    def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
+        self.addPrivateSplitL1Caches(ic, dc)
+        self.toL2Bus = Bus()
+        self.connectMemPorts(self.toL2Bus)
+        self.l2cache = l2c
+        self.l2cache.cpu_side = toL2Bus.port
+        self._mem_ports = ['l2cache.mem_side']

src/python/m5/objects/O3CPU.py

@@ -22,6 +22,7 @@ class DerivO3CPU(BaseCPU):
     cachePorts = Param.Unsigned("Cache Ports")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
+    _mem_ports = ['icache_port', 'dcache_port']
 
     decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
     renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")

tests/quick/00.hello/test.py

@@ -0,0 +1,29 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+root.system.cpu.workload = LiveProcess(file = binpath('hello'))

tests/quick/20.eio-short/test.py

@@ -0,0 +1,30 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+root.system.cpu.workload = EioProcess(file = binpath('anagram-vshort.eio.gz'))
+root.system.cpu.max_insts_any_thread = 500000

tests/quick/eio1/test.py

@@ -1,2 +0,0 @@
-root.system.cpu.workload = EioProcess(file = tests_root + '/test-progs/anagram/bin/anagram-vshort.eio.gz')
-root.system.cpu.max_insts_any_thread = 500000

tests/run.py

@@ -33,12 +33,21 @@ import os, sys
 
 # find path to directory containing this file
 tests_root = os.path.dirname(__file__)
+test_progs = os.path.join(tests_root, 'test-progs')
+
+# generate path to binary file
+def binpath(app, file=None):
+    # executable has same name as app unless specified otherwise
+    if not file:
+        file = app
+    return os.path.join(test_progs, app, 'bin', isa, opsys, file)
 
 # build configuration
 execfile(os.path.join(tests_root, config + '.py'))
 
 # set default maxtick... script can override
-maxtick = 1000000
+# -1 means run forever
+maxtick = -1
 
 # tweak configuration for specific test
 

tests/simple-atomic.py

@@ -7,8 +7,6 @@ system = System(cpu = AtomicSimpleCPU(),
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-system.cpu.icache_port = system.membus.port
-system.cpu.dcache_port = system.membus.port
+system.cpu.connectMemPorts(system.membus)
 
 root = Root(system = system)
-

tests/simple-timing.py

@@ -11,11 +11,13 @@ class MyCache(BaseCache):
     tgts_per_mshr = 5
 
 cpu = TimingSimpleCPU()
-cpu.icache = MyCache(size = '128kB')
-cpu.dcache = MyCache(size = '256kB')
-cpu.l2cache = MyCache(size = '2MB')
+cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+                              MyCache(size = '2MB'))
 
-cpu.icache_port = cpu.icache.cpu_side
-cpu.dcache_port = cpu.dcache.cpu_side
+system = System(cpu = cpu,
+                physmem = PhysicalMemory(),
+                membus = Bus())
+system.physmem.port = system.membus.port
+cpu.connectMemPorts(system.membus)
 
-root = makeSESystem(cpu)
+root = Root(system = system)