gem5/configs/common
Kevin Lim 0ba2cc6571 Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches.
configs/common/Simulation.py:
    Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.

    However the O3CPU must always use caches, so a check for that must still exist.

    Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
    Atomic CPU now handles caches.

--HG--
extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
2006-11-09 15:05:13 -05:00
..
Benchmarks.py Add mutex test to Benchmarks.py. 2006-10-22 12:52:58 -04:00
Caches.py factor out common run code from se.py and fs.py. 2006-10-27 16:32:26 -04:00
FSConfig.py FSConfig.py: 2006-10-30 16:55:52 -05:00
Options.py decouple the switch option from the warmup period option - parsing was confused otherwise, oops. 2006-10-30 14:12:15 -05:00
Simulation.py Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches. 2006-11-09 15:05:13 -05:00
SysPaths.py Two minor fixes. 2006-10-10 01:49:46 -04:00