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Merge ktlim@zizzer:/bk/newmem

Browse source 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : 56cb7fe3be5b63bd89b48ac6cb88b47d13b4c137
This commit is contained in:
Kevin Lim 2006-11-10 12:14:38 -05:00
commit 73581bf801
40 changed files with 1409 additions and 551 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
SConstruct
View file

@ -370,7 +370,7 @@ nonsticky_opts.AddOptions(
# These options get exported to #defines in config/*.hh (see src/SConscript).
env.ExportOptions = ['FULL_SYSTEM', 'ALPHA_TLASER', 'USE_FENV', \
'USE_MYSQL', 'NO_FAST_ALLOC', 'SS_COMPATIBLE_FP', \
'USE_CHECKER', 'PYTHONHOME']
'USE_CHECKER', 'PYTHONHOME', 'TARGET_ISA']
# Define a handy 'no-op' action
def no_action(target, source, env):

21
configs/common/FSConfig.py
View file

@ -78,6 +78,27 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
return self
def makeSparcSystem(mem_mode, mdesc = None):
self = SparcSystem()
if not mdesc:
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
self.membus = Bus(bus_id=1)
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
self.physmem.port = self.membus.port
self.rom.port = self.membus.port
self.intrctrl = IntrControl()
self.mem_mode = mem_mode
self.kernel = binary('vmlinux')
self.reset_bin = binary('reset.bin')
self.hypervisor_bin = binary('q.bin')
self.openboot_bin = binary('openboot.bin')
return self
def makeDualRoot(testSystem, driveSystem, dumpfile):
self = Root()
self.testsys = testSystem

1
src/SConscript
View file

@ -74,6 +74,7 @@ base_sources = Split('''
base/loader/aout_object.cc
base/loader/ecoff_object.cc
base/loader/elf_object.cc
base/loader/raw_object.cc
base/loader/object_file.cc
base/loader/symtab.cc
base/stats/events.cc

14
src/arch/alpha/SConscript
View file

@ -48,25 +48,29 @@ Import('env')
# Base sources used by all configurations.
base_sources = Split('''
faults.cc
isa_traits.cc
floatregfile.cc
intregfile.cc
miscregfile.cc
regfile.cc
''')
# Full-system sources
full_system_sources = Split('''
tlb.cc
arguments.cc
ev5.cc
freebsd/system.cc
idle_event.cc
ipr.cc
kernel_stats.cc
linux/system.cc
osfpal.cc
pagetable.cc
stacktrace.cc
vtophys.cc
remote_gdb.cc
system.cc
freebsd/system.cc
linux/system.cc
tlb.cc
tru64/system.cc
vtophys.cc
''')

2
src/arch/alpha/ev5.cc
View file

@ -557,7 +557,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
void
AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
{
for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
for (int i = 0; i < NumInternalProcRegs; ++i) {
dest->setMiscReg(i, src->readMiscReg(i));
}
}

49
src/arch/alpha/floatregfile.cc Normal file
View file

@ -0,0 +1,49 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Gabe Black
* Kevin Lim
*/
#include "arch/alpha/floatregfile.hh"
#include "sim/serialize.hh"
namespace AlphaISA
{
void
FloatRegFile::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(q, NumFloatRegs);
}
void
FloatRegFile::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(q, NumFloatRegs);
}
}

68
src/arch/alpha/floatregfile.hh Normal file
View file

@ -0,0 +1,68 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Gabe Black
*/
#ifndef __ARCH_ALPHA_FLOATREGFILE_HH__
#define __ARCH_ALPHA_FLOATREGFILE_HH__
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/types.hh"
#include <string.h>
#include <iostream>
class Checkpoint;
namespace AlphaISA
{
static inline std::string getFloatRegName(RegIndex)
{
return "";
}
class FloatRegFile
{
public:
union {
uint64_t q[NumFloatRegs]; // integer qword view
double d[NumFloatRegs]; // double-precision floating point view
};
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
{ bzero(d, sizeof(d)); }
};
}
#endif

65
src/arch/alpha/intregfile.cc Normal file
View file

@ -0,0 +1,65 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Gabe Black
* Kevin Lim
*/
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/intregfile.hh"
#include "sim/serialize.hh"
namespace AlphaISA
{
#if FULL_SYSTEM
const int reg_redir[AlphaISA::NumIntRegs] = {
/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
/* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
/* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
#else
const int reg_redir[AlphaISA::NumIntRegs] = {
/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
/* 8 */ 8, 9, 10, 11, 12, 13, 14, 15,
/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
/* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
#endif
void
IntRegFile::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(regs, NumIntRegs);
}
void
IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(regs, NumIntRegs);
}
}

78
src/arch/alpha/intregfile.hh Normal file
View file

@ -0,0 +1,78 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Gabe Black
*/
#ifndef __ARCH_ALPHA_INTREGFILE_HH__
#define __ARCH_ALPHA_INTREGFILE_HH__
#include "arch/alpha/types.hh"
#include <iostream>
#include <strings.h>
class Checkpoint;
namespace AlphaISA
{
static inline std::string getIntRegName(RegIndex)
{
return "";
}
// redirected register map, really only used for the full system case.
extern const int reg_redir[NumIntRegs];
class IntRegFile
{
protected:
IntReg regs[NumIntRegs];
public:
IntReg readReg(int intReg)
{
return regs[intReg];
}
void setReg(int intReg, const IntReg &val)
{
regs[intReg] = val;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
{ bzero(regs, sizeof(regs)); }
};
}
#endif

2
src/arch/alpha/isa/fp.isa
View file

@ -229,7 +229,7 @@ def template FloatingPointExecute {{
%(code)s;
} else {
fesetround(getC99RoundingMode(
xc->readMiscReg(AlphaISA::Fpcr_DepTag)));
xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
%(code)s;
fesetround(FE_TONEAREST);
}

11
src/arch/alpha/isa/main.isa
View file

@ -184,9 +184,9 @@ def operands {{
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1),
'FPCR': ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1),
'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1),
'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),
@ -216,11 +216,6 @@ output header {{
/// live here and not in the AlphaISA namespace.
enum DependenceTags {
FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
Uniq_DepTag = AlphaISA::Uniq_DepTag,
Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
};
/// Constructor.

12
src/arch/alpha/isa_traits.hh
View file

@ -50,13 +50,7 @@ namespace AlphaISA
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 40,
Ctrl_Base_DepTag = 72,
Fpcr_DepTag = 72, // floating point control register
Uniq_DepTag = 73,
Lock_Flag_DepTag = 74,
Lock_Addr_DepTag = 75,
Intr_Flag_DepTag = 76,
IPR_Base_DepTag = 77
Ctrl_Base_DepTag = 72
};
StaticInstPtr decodeInst(ExtMachInst);
@ -120,7 +114,6 @@ namespace AlphaISA
NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
};
// EV5 modes
enum mode_type
{
@ -187,9 +180,6 @@ namespace AlphaISA
// Alpha UNOP (ldq_u r31,0(r0))
const ExtMachInst NoopMachInst = 0x2ffe0000;
// redirected register map, really only used for the full system case.
extern const int reg_redir[NumIntRegs];
};
#endif // __ARCH_ALPHA_ISA_TRAITS_HH__

12
src/arch/alpha/locked_mem.hh
View file

@ -37,7 +37,7 @@
* ISA-specific helper functions for locked memory accesses.
*/
#include "arch/isa_traits.hh"
#include "arch/alpha/miscregfile.hh"
#include "base/misc.hh"
#include "mem/request.hh"
@ -48,8 +48,8 @@ template <class XC>
inline void
handleLockedRead(XC *xc, Request *req)
{
xc->setMiscReg(Lock_Addr_DepTag, req->getPaddr() & ~0xf);
xc->setMiscReg(Lock_Flag_DepTag, true);
xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
xc->setMiscReg(MISCREG_LOCKFLAG, true);
}
@ -63,13 +63,13 @@ handleLockedWrite(XC *xc, Request *req)
req->setScResult(2);
} else {
// standard store conditional
bool lock_flag = xc->readMiscReg(Lock_Flag_DepTag);
Addr lock_addr = xc->readMiscReg(Lock_Addr_DepTag);
bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
// Lock flag not set or addr mismatch in CPU;
// don't even bother sending to memory system
req->setScResult(0);
xc->setMiscReg(Lock_Flag_DepTag, false);
xc->setMiscReg(MISCREG_LOCKFLAG, false);
// the rest of this code is not architectural;
// it's just a debugging aid to help detect
// livelock by warning on long sequences of failed

161
src/arch/alpha/miscregfile.cc Normal file
View file

@ -0,0 +1,161 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Gabe Black
* Kevin Lim
*/
#include "arch/alpha/miscregfile.hh"
#include "base/misc.hh"
namespace AlphaISA
{
void
MiscRegFile::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(fpcr);
SERIALIZE_SCALAR(uniq);
SERIALIZE_SCALAR(lock_flag);
SERIALIZE_SCALAR(lock_addr);
#if FULL_SYSTEM
SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
#endif
}
void
MiscRegFile::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(fpcr);
UNSERIALIZE_SCALAR(uniq);
UNSERIALIZE_SCALAR(lock_flag);
UNSERIALIZE_SCALAR(lock_addr);
#if FULL_SYSTEM
UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
#endif
}
MiscReg
MiscRegFile::readReg(int misc_reg)
{
switch(misc_reg) {
case MISCREG_FPCR:
return fpcr;
case MISCREG_UNIQ:
return uniq;
case MISCREG_LOCKFLAG:
return lock_flag;
case MISCREG_LOCKADDR:
return lock_addr;
case MISCREG_INTR:
return intr_flag;
#if FULL_SYSTEM
default:
assert(misc_reg < NumInternalProcRegs);
return ipr[misc_reg];
#else
default:
panic("Attempt to read an invalid misc register!");
return 0;
#endif
}
}
MiscReg
MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc)
{
#if FULL_SYSTEM
return readIpr(misc_reg, tc);
#else
panic("No faulting misc regs in SE mode!");
return 0;
#endif
}
void
MiscRegFile::setReg(int misc_reg, const MiscReg &val)
{
switch(misc_reg) {
case MISCREG_FPCR:
fpcr = val;
return;
case MISCREG_UNIQ:
uniq = val;
return;
case MISCREG_LOCKFLAG:
lock_flag = val;
return;
case MISCREG_LOCKADDR:
lock_addr = val;
return;
case MISCREG_INTR:
intr_flag = val;
return;
#if FULL_SYSTEM
default:
assert(misc_reg < NumInternalProcRegs);
ipr[misc_reg] = val;
return;
#else
default:
panic("Attempt to write to an invalid misc register!");
#endif
}
}
void
MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val,
ThreadContext *tc)
{
#if FULL_SYSTEM
switch(misc_reg) {
case MISCREG_FPCR:
fpcr = val;
return;
case MISCREG_UNIQ:
uniq = val;
return;
case MISCREG_LOCKFLAG:
lock_flag = val;
return;
case MISCREG_LOCKADDR:
lock_addr = val;
return;
case MISCREG_INTR:
intr_flag = val;
return;
default:
return setIpr(misc_reg, val, tc);
}
#else
//panic("No registers with side effects in SE mode!");
return;
#endif
}
}

123
src/arch/alpha/miscregfile.hh Normal file
View file

@ -0,0 +1,123 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Gabe Black
*/
#ifndef __ARCH_ALPHA_MISCREGFILE_HH__
#define __ARCH_ALPHA_MISCREGFILE_HH__
#include "arch/alpha/ipr.hh"
#include "arch/alpha/types.hh"
#include "config/full_system.hh"
#include "sim/host.hh"
#include "sim/serialize.hh"
#include <iostream>
class Checkpoint;
class ThreadContext;
namespace AlphaISA
{
enum MiscRegIndex
{
MISCREG_FPCR = NumInternalProcRegs,
MISCREG_UNIQ,
MISCREG_LOCKFLAG,
MISCREG_LOCKADDR,
MISCREG_INTR
};
static inline std::string getMiscRegName(RegIndex)
{
return "";
}
class MiscRegFile {
protected:
uint64_t fpcr; // floating point condition codes
uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
Addr lock_addr; // lock address for LL/SC
int intr_flag;
public:
MiscRegFile()
{
#if FULL_SYSTEM
initializeIprTable();
#endif
}
MiscReg readReg(int misc_reg);
MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
//These functions should be removed once the simplescalar cpu model
//has been replaced.
int getInstAsid();
int getDataAsid();
void setReg(int misc_reg, const MiscReg &val);
void setRegWithEffect(int misc_reg, const MiscReg &val,
ThreadContext *tc);
void clear()
{
fpcr = uniq = 0;
lock_flag = 0;
lock_addr = 0;
intr_flag = 0;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
#if FULL_SYSTEM
protected:
typedef uint64_t InternalProcReg;
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
InternalProcReg readIpr(int idx, ThreadContext *tc);
void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
#endif
friend class RegFile;
};
#if FULL_SYSTEM
void copyIprs(ThreadContext *src, ThreadContext *dest);
#endif
}
#endif

63
src/arch/alpha/pagetable.cc Normal file
View file

@ -0,0 +1,63 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/alpha/pagetable.hh"
#include "sim/serialize.hh"
namespace AlphaISA
{
void
PTE::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(tag);
SERIALIZE_SCALAR(ppn);
SERIALIZE_SCALAR(xre);
SERIALIZE_SCALAR(xwe);
SERIALIZE_SCALAR(asn);
SERIALIZE_SCALAR(asma);
SERIALIZE_SCALAR(fonr);
SERIALIZE_SCALAR(fonw);
SERIALIZE_SCALAR(valid);
}
void
PTE::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(tag);
UNSERIALIZE_SCALAR(ppn);
UNSERIALIZE_SCALAR(xre);
UNSERIALIZE_SCALAR(xwe);
UNSERIALIZE_SCALAR(asn);
UNSERIALIZE_SCALAR(asma);
UNSERIALIZE_SCALAR(fonr);
UNSERIALIZE_SCALAR(fonw);
UNSERIALIZE_SCALAR(valid);
}
}

101
src/arch/alpha/regfile.cc Normal file
View file

@ -0,0 +1,101 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Gabe Black
* Kevin Lim
*/
#include "arch/alpha/regfile.hh"
#include "cpu/thread_context.hh"
namespace AlphaISA
{
void
RegFile::serialize(std::ostream &os)
{
intRegFile.serialize(os);
floatRegFile.serialize(os);
miscRegFile.serialize(os);
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
#if FULL_SYSTEM
SERIALIZE_SCALAR(intrflag);
#endif
}
void
RegFile::unserialize(Checkpoint *cp, const std::string &section)
{
intRegFile.unserialize(cp, section);
floatRegFile.unserialize(cp, section);
miscRegFile.unserialize(cp, section);
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
#if FULL_SYSTEM
UNSERIALIZE_SCALAR(intrflag);
#endif
}
void
copyRegs(ThreadContext *src, ThreadContext *dest)
{
// First loop through the integer registers.
for (int i = 0; i < NumIntRegs; ++i) {
dest->setIntReg(i, src->readIntReg(i));
}
// Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
dest->setFloatRegBits(i, src->readFloatRegBits(i));
}
// Copy misc. registers
copyMiscRegs(src, dest);
// Lastly copy PC/NPC
dest->setPC(src->readPC());
dest->setNextPC(src->readNextPC());
}
void
copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
dest->setMiscReg(AlphaISA::MISCREG_FPCR,
src->readMiscReg(AlphaISA::MISCREG_FPCR));
dest->setMiscReg(AlphaISA::MISCREG_UNIQ,
src->readMiscReg(AlphaISA::MISCREG_UNIQ));
dest->setMiscReg(AlphaISA::MISCREG_LOCKFLAG,
src->readMiscReg(AlphaISA::MISCREG_LOCKFLAG));
dest->setMiscReg(AlphaISA::MISCREG_LOCKADDR,
src->readMiscReg(AlphaISA::MISCREG_LOCKADDR));
#if FULL_SYSTEM
copyIprs(src, dest);
#endif
}
}

121
src/arch/alpha/regfile.hh
View file

@ -32,7 +32,9 @@
#define __ARCH_ALPHA_REGFILE_HH__
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/ipr.hh"
#include "arch/alpha/floatregfile.hh"
#include "arch/alpha/intregfile.hh"
#include "arch/alpha/miscregfile.hh"
#include "arch/alpha/types.hh"
#include "sim/faults.hh"
@ -46,119 +48,6 @@ class ThreadContext;
namespace AlphaISA
{
static inline std::string getIntRegName(RegIndex)
{
return "";
}
static inline std::string getFloatRegName(RegIndex)
{
return "";
}
static inline std::string getMiscRegName(RegIndex)
{
return "";
}
class IntRegFile
{
protected:
IntReg regs[NumIntRegs];
public:
IntReg readReg(int intReg)
{
return regs[intReg];
}
Fault setReg(int intReg, const IntReg &val)
{
regs[intReg] = val;
return NoFault;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
{ bzero(regs, sizeof(regs)); }
};
class FloatRegFile
{
public:
union {
uint64_t q[NumFloatRegs]; // integer qword view
double d[NumFloatRegs]; // double-precision floating point view
};
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
{ bzero(d, sizeof(d)); }
};
class MiscRegFile {
protected:
uint64_t fpcr; // floating point condition codes
uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
Addr lock_addr; // lock address for LL/SC
int intr_flag;
public:
MiscRegFile()
{
#if FULL_SYSTEM
initializeIprTable();
#endif
}
MiscReg readReg(int misc_reg);
MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
//These functions should be removed once the simplescalar cpu model
//has been replaced.
int getInstAsid();
int getDataAsid();
void setReg(int misc_reg, const MiscReg &val);
void setRegWithEffect(int misc_reg, const MiscReg &val,
ThreadContext *tc);
void clear()
{
fpcr = uniq = 0;
lock_flag = 0;
lock_addr = 0;
intr_flag = 0;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
#if FULL_SYSTEM
protected:
typedef uint64_t InternalProcReg;
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
InternalProcReg readIpr(int idx, ThreadContext *tc);
void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
#endif
friend class RegFile;
};
class RegFile {
protected:
@ -303,10 +192,6 @@ namespace AlphaISA
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
#if FULL_SYSTEM
void copyIprs(ThreadContext *src, ThreadContext *dest);
#endif
} // namespace AlphaISA
#endif

15
src/arch/sparc/faults.cc
View file

@ -493,21 +493,22 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
void getREDVector(Addr & PC, Addr & NPC)
{
//XXX The following constant might belong in a header file.
const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL;
PC = RSTVAddr | 0xA0;
NPC = PC + sizeof(MachInst);
}
void getHyperVector(Addr & PC, Addr & NPC, MiscReg TT)
void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
{
Addr HTBA ;
Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
NPC = PC + sizeof(MachInst);
}
void getPrivVector(Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
{
Addr TBA ;
Addr TBA = tc->readMiscReg(MISCREG_TBA);
PC = (TBA & ~mask(15)) |
(TL > 1 ? (1 << 14) : 0) |
((TT << 5) & mask(14));
@ -556,17 +557,17 @@ void SparcFaultBase::invoke(ThreadContext * tc)
{
//guest_watchdog fault
doNormalFault(tc, trapType(), true);
getHyperVector(PC, NPC, 2);
getHyperVector(tc, PC, NPC, 2);
}
else if(level == Hyperprivileged)
{
doNormalFault(tc, trapType(), true);
getHyperVector(PC, NPC, trapType());
getHyperVector(tc, PC, NPC, trapType());
}
else
{
doNormalFault(tc, trapType(), false);
getPrivVector(PC, NPC, trapType(), TL+1);
getPrivVector(tc, PC, NPC, trapType(), TL+1);
}
tc->setPC(PC);

197
src/arch/sparc/isa/decoder.isa
View file

@ -346,22 +346,93 @@ decode OP default Unknown::unknown()
0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
}
// XXX might want a format rdipr thing here
0x28: decode RS1 {
0xF: decode I {
0x00: NoPriv::rdy({{Rd = Y;}});
//1 should cause an illegal instruction exception
0x02: NoPriv::rdccr({{Rd = Ccr;}});
0x03: NoPriv::rdasi({{Rd = Asi;}});
0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
0x05: NoPriv::rdpc({{
if(Pstate<3:>)
Rd = (xc->readPC())<31:0>;
else
Rd = xc->readPC();}});
0x06: NoPriv::rdfprs({{
//Wait for all fpops to finish.
Rd = Fprs;
}});
//7-14 should cause an illegal instruction exception
0x0F: decode I {
0x0: Nop::stbar({{/*stuff*/}});
0x1: Nop::membar({{/*stuff*/}});
}
default: rdasr({{
Rd = xc->readMiscRegWithEffect(RS1 + AsrStart);
0x10: Priv::rdpcr({{Rd = Pcr;}});
0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
//0x12 should cause an illegal instruction exception
0x13: NoPriv::rdgsr({{
if(Fprs<2:> == 0 || Pstate<4:> == 0)
Rd = Gsr;
else
fault = new FpDisabled;
}});
//0x14-0x15 should cause an illegal instruction exception
0x16: Priv::rdsoftint({{Rd = Softint;}});
0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
//0x1A-0x1F should cause an illegal instruction exception
}
0x29: decode RS1 {
0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
0x01: HPriv::rdhprhtstate({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Htstate;
}});
//0x02 should cause an illegal instruction exception
0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
//0x04 should cause an illegal instruction exception
0x05: HPriv::rdhprhtba({{Rd = Htba;}});
0x06: HPriv::rdhprhver({{Rd = Hver;}});
//0x07-0x1E should cause an illegal instruction exception
0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
}
0x2A: decode RS1 {
0x00: Priv::rdprtpc({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Tpc;
}});
0x01: Priv::rdprtnpc({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Tnpc;
}});
0x02: Priv::rdprtstate({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Tstate;
}});
0x03: Priv::rdprtt({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Tt;
}});
0x04: Priv::rdprtick({{Rd = Tick;}});
0x05: Priv::rdprtba({{Rd = Tba;}});
0x06: Priv::rdprpstate({{Rd = Pstate;}});
0x07: Priv::rdprtl({{Rd = Tl;}});
0x08: Priv::rdprpil({{Rd = Pil;}});
0x09: Priv::rdprcwp({{Rd = Cwp;}});
0x0A: Priv::rdprcansave({{Rd = Cansave;}});
0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
0x0E: Priv::rdprwstate({{Rd = Wstate;}});
//0x0F should cause an illegal instruction exception
0x10: Priv::rdprgl({{Rd = Gl;}});
//0x11-0x1F should cause an illegal instruction exception
}
0x29: HPriv::rdhpr({{
Rd = xc->readMiscRegWithEffect(RS1 + HprStart);
}});
0x2A: Priv::rdpr({{
Rd = xc->readMiscRegWithEffect(RS1 + PrStart);
}});
0x2B: BasicOperate::flushw({{
if(NWindows - 2 - Cansave == 0)
{
@ -417,9 +488,35 @@ decode OP default Unknown::unknown()
0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
}
0x30: wrasr({{
xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
}});
0x30: decode RD {
0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
//0x01 should cause an illegal instruction exception
0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
//0x04-0x05 should cause an illegal instruction exception
0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
//0x07-0x0E should cause an illegal instruction exception
0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
//0x12 should cause an illegal instruction exception
0x13: NoPriv::wrgsr({{
if(Fprs<2:> == 0 || Pstate<4:> == 0)
return new FpDisabled;
Gsr = Rs1 ^ Rs2_or_imm13;
}});
0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
0x18: NoPriv::wrstick({{
if(!Hpstate<2:>)
return new IllegalInstruction;
Stick = Rs1 ^ Rs2_or_imm13;
}});
0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
//0x1A-0x1F should cause an illegal instruction exception
}
0x31: decode FCN {
0x0: Priv::saved({{
assert(Cansave < NWindows - 2);
@ -440,16 +537,70 @@ decode OP default Unknown::unknown()
Otherwin = Otherwin - 1;
}});
}
0x32: Priv::wrpr({{
// XXX Need to protect with format that traps non-priv
// access
xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
}});
0x33: HPriv::wrhpr({{
// XXX Need to protect with format that traps non-priv/priv
// access
xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
}});
0x32: decode RD {
0x00: Priv::wrprtpc({{
if(Tl == 0)
return new IllegalInstruction;
else
Tpc = Rs1 ^ Rs2_or_imm13;
}});
0x01: Priv::wrprtnpc({{
if(Tl == 0)
return new IllegalInstruction;
else
Tnpc = Rs1 ^ Rs2_or_imm13;
}});
0x02: Priv::wrprtstate({{
if(Tl == 0)
return new IllegalInstruction;
else
Tstate = Rs1 ^ Rs2_or_imm13;
}});
0x03: Priv::wrprtt({{
if(Tl == 0)
return new IllegalInstruction;
else
Tt = Rs1 ^ Rs2_or_imm13;
}});
0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
0x07: Priv::wrprtl({{
if(Pstate<2:> && !Hpstate<2:>)
Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
else
Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
}});
0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
//0x0F should cause an illegal instruction exception
0x10: Priv::wrprgl({{
if(Pstate<2:> && !Hpstate<2:>)
Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
else
Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
}});
//0x11-0x1F should cause an illegal instruction exception
}
0x33: decode RD {
0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
0x01: HPriv::wrhprhtstate({{
if(Tl == 0)
return new IllegalInstruction;
Htstate = Rs1 ^ Rs2_or_imm13;
}});
//0x02 should cause an illegal instruction exception
0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
//0x04 should cause an illegal instruction exception
0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
//0x06-0x01D should cause an illegal instruction exception
0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
}
0x34: decode OPF{
format BasicOperate{
0x01: fmovs({{

24
src/arch/sparc/isa/formats/priv.isa
View file

@ -119,18 +119,34 @@ let {{
return (header_output, decoder_output, exec_output, decode_block)
}};
// Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{
checkCode = "!(Pstate<2:2> || Hpstate<2:2>)"
checkCode = "!(Pstate<2:> || Hpstate<2:>)"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))
checkCode, name, Name, opt_flags)
}};
def format NoPriv(code, *opt_flags) {{
#Instructions which use this format don't really check for
#any particular mode, but the disassembly is performed
#using the control registers actual name
checkCode = "false"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags)
}};
def format PrivCheck(code, extraCheckCode, *opt_flags) {{
checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCheckCode
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags)
}};
def format HPriv(code, *opt_flags) {{
checkCode = "!Hpstate<2:2>"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))
checkCode, name, Name, opt_flags)
}};

1
src/arch/sparc/isa/includes.isa
View file

@ -54,6 +54,7 @@ output decoder {{
#if defined(linux)
#include <fenv.h>
#endif
#include <algorithm>
using namespace SparcISA;
}};

50
src/arch/sparc/isa/operands.isa
View file

@ -80,8 +80,6 @@ def operands {{
'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
'R0': ('IntReg', 'udw', '0', None, 6),
'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
@ -91,24 +89,42 @@ def operands {{
'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43),
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62),
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
# Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)

75
src/arch/sparc/miscregfile.cc
View file

@ -29,7 +29,9 @@
* Ali Saidi
*/
#include "arch/sparc/asi.hh"
#include "arch/sparc/miscregfile.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
@ -62,6 +64,39 @@ string SparcISA::getMiscRegName(RegIndex index)
void MiscRegFile::reset()
{
y = 0;
ccr = 0;
asi = 0;
tick = 0;
fprs = 0;
gsr = 0;
softint = 0;
tick_cmpr = 0;
stick = 0;
stick_cmpr = 0;
memset(tpc, 0, sizeof(tpc));
memset(tnpc, 0, sizeof(tnpc));
memset(tstate, 0, sizeof(tstate));
memset(tt, 0, sizeof(tt));
pstate = 0;
tl = 0;
pil = 0;
cwp = 0;
cansave = 0;
canrestore = 0;
cleanwin = 0;
otherwin = 0;
wstate = 0;
gl = 0;
hpstate = 0;
memset(htstate, 0, sizeof(htstate));
hintp = 0;
htba = 0;
hstick_cmpr = 0;
strandStatusReg = 0;
fsr = 0;
implicitInstAsi = ASI_PRIMARY;
implicitDataAsi = ASI_PRIMARY;
}
MiscReg MiscRegFile::readReg(int miscReg)
@ -78,8 +113,9 @@ MiscReg MiscRegFile::readReg(int miscReg)
case MISCREG_TICK:
return tick;
case MISCREG_PCR:
panic("PCR not implemented\n");
case MISCREG_PIC:
panic("ASR number %d not implemented\n", miscReg - AsrStart);
panic("PIC not implemented\n");
case MISCREG_GSR:
return gsr;
case MISCREG_SOFTINT:
@ -154,8 +190,8 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
switch (miscReg) {
case MISCREG_TICK:
case MISCREG_PRIVTICK:
return tc->getCpuPtr()->curCycle() - tickFields.counter |
tickFields.npt << 63;
return tc->getCpuPtr()->curCycle() - (tick & mask(63)) |
(tick & ~(mask(63))) << 63;
case MISCREG_FPRS:
panic("FPU not implemented\n");
case MISCREG_PCR:
@ -171,7 +207,7 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
SparcSystem *sys;
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
#endif
case MISCREG_HVER:
return NWindows | MaxTL << 8 | MaxGL << 16;
@ -198,8 +234,9 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
tick = val;
break;
case MISCREG_PCR:
panic("PCR not implemented\n");
case MISCREG_PIC:
panic("ASR number %d not implemented\n", miscReg - AsrStart);
panic("PIC not implemented\n");
case MISCREG_GSR:
gsr = val;
break;
@ -303,12 +340,12 @@ inline void MiscRegFile::setImplicitAsis()
if(tl == 0)
{
implicitInstAsi = implicitDataAsi =
pstateFields.cle ? ASI_PRIMARY_LITTLE : ASI_PRIMARY;
(pstate & (1 << 9)) ? ASI_PRIMARY_LITTLE : ASI_PRIMARY;
}
else if(tl <= MaxPTL)
{
implicitInstAsi = ASI_NUCLEUS;
implicitDataAsi = pstateFields.cle ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS;
implicitDataAsi = (pstate & (1 << 9)) ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS;
}
else
{
@ -328,8 +365,8 @@ void MiscRegFile::setRegWithEffect(int miscReg,
#endif
switch (miscReg) {
case MISCREG_TICK:
tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
tickFields.npt = val & Bit64 ? 1 : 0;
tick = tc->getCpuPtr()->curCycle() - val & ~Bit64;
tick |= val & Bit64;
break;
case MISCREG_FPRS:
//Configure the fpu based on the fprs
@ -369,10 +406,10 @@ void MiscRegFile::setRegWithEffect(int miscReg,
if (tickCompare == NULL)
tickCompare = new TickCompareEvent(this, tc);
setReg(miscReg, val);
if (tick_cmprFields.int_dis && tickCompare->scheduled())
if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
tickCompare->deschedule();
time = tick_cmprFields.tick_cmpr - tickFields.counter;
if (!tick_cmprFields.int_dis && time > 0)
time = (tick_cmpr & mask(63)) - (tick & mask(63));
if (!(tick_cmpr & ~mask(63)) && time > 0)
tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
break;
#endif
@ -390,17 +427,17 @@ void MiscRegFile::setRegWithEffect(int miscReg,
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
stickFields.npt = val & Bit64 ? 1 : 0;
stick |= val & Bit64;
break;
case MISCREG_STICK_CMPR:
if (sTickCompare == NULL)
sTickCompare = new STickCompareEvent(this, tc);
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
if (stick_cmprFields.int_dis && sTickCompare->scheduled())
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
sTickCompare->deschedule();
time = stick_cmprFields.tick_cmpr - sys->sysTick;
if (!stick_cmprFields.int_dis && time > 0)
time = (stick_cmpr & mask(63)) - sys->sysTick;
if (!(stick_cmpr & ~mask(63)) && time > 0)
sTickCompare->schedule(time * Clock::Int::ns);
break;
case MISCREG_HSTICK_CMPR:
@ -408,10 +445,10 @@ void MiscRegFile::setRegWithEffect(int miscReg,
hSTickCompare = new HSTickCompareEvent(this, tc);
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
if (hstick_cmprFields.int_dis && hSTickCompare->scheduled())
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
hSTickCompare->deschedule();
int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
if (!hstick_cmprFields.int_dis && time > 0)
int64_t time = (hstick_cmpr & mask(63)) - sys->sysTick;
if (!(hstick_cmpr & ~mask(63)) && time > 0)
hSTickCompare->schedule(time * Clock::Int::ns);
break;
#endif

301
src/arch/sparc/miscregfile.hh
View file

@ -46,59 +46,53 @@ namespace SparcISA
//These functions map register indices to names
std::string getMiscRegName(RegIndex);
const int AsrStart = 0;
const int PrStart = 32;
const int HprStart = 64;
const int MiscStart = 96;
enum MiscRegIndex
{
/** Ancillary State Registers */
MISCREG_Y = AsrStart + 0,
MISCREG_CCR = AsrStart + 2,
MISCREG_ASI = AsrStart + 3,
MISCREG_TICK = AsrStart + 4,
MISCREG_FPRS = AsrStart + 6,
MISCREG_PCR = AsrStart + 16,
MISCREG_PIC = AsrStart + 17,
MISCREG_GSR = AsrStart + 19,
MISCREG_SOFTINT_SET = AsrStart + 20,
MISCREG_SOFTINT_CLR = AsrStart + 21,
MISCREG_SOFTINT = AsrStart + 22,
MISCREG_TICK_CMPR = AsrStart + 23,
MISCREG_STICK = AsrStart + 24,
MISCREG_STICK_CMPR = AsrStart + 25,
MISCREG_Y,
MISCREG_CCR,
MISCREG_ASI,
MISCREG_TICK,
MISCREG_FPRS,
MISCREG_PCR,
MISCREG_PIC,
MISCREG_GSR,
MISCREG_SOFTINT_SET,
MISCREG_SOFTINT_CLR,
MISCREG_SOFTINT,
MISCREG_TICK_CMPR,
MISCREG_STICK,
MISCREG_STICK_CMPR,
/** Privilged Registers */
MISCREG_TPC = PrStart + 0,
MISCREG_TNPC = PrStart + 1,
MISCREG_TSTATE = PrStart + 2,
MISCREG_TT = PrStart + 3,
MISCREG_PRIVTICK = PrStart + 4,
MISCREG_TBA = PrStart + 5,
MISCREG_PSTATE = PrStart + 6,
MISCREG_TL = PrStart + 7,
MISCREG_PIL = PrStart + 8,
MISCREG_CWP = PrStart + 9,
MISCREG_CANSAVE = PrStart + 10,
MISCREG_CANRESTORE = PrStart + 11,
MISCREG_CLEANWIN = PrStart + 12,
MISCREG_OTHERWIN = PrStart + 13,
MISCREG_WSTATE = PrStart + 14,
MISCREG_GL = PrStart + 16,
MISCREG_TPC,
MISCREG_TNPC,
MISCREG_TSTATE,
MISCREG_TT,
MISCREG_PRIVTICK,
MISCREG_TBA,
MISCREG_PSTATE,
MISCREG_TL,
MISCREG_PIL,
MISCREG_CWP,
MISCREG_CANSAVE,
MISCREG_CANRESTORE,
MISCREG_CLEANWIN,
MISCREG_OTHERWIN,
MISCREG_WSTATE,
MISCREG_GL,
/** Hyper privileged registers */
MISCREG_HPSTATE = HprStart + 0,
MISCREG_HTSTATE = HprStart + 1,
MISCREG_HINTP = HprStart + 3,
MISCREG_HTBA = HprStart + 5,
MISCREG_HVER = HprStart + 6,
MISCREG_STRAND_STS_REG = HprStart + 16,
MISCREG_HSTICK_CMPR = HprStart + 31,
MISCREG_HPSTATE,
MISCREG_HTSTATE,
MISCREG_HINTP,
MISCREG_HTBA,
MISCREG_HVER,
MISCREG_STRAND_STS_REG,
MISCREG_HSTICK_CMPR,
/** Floating Point Status Register */
MISCREG_FSR = MiscStart + 0
MISCREG_FSR
};
// The control registers, broken out into fields
@ -107,93 +101,16 @@ namespace SparcISA
private:
/* ASR Registers */
union {
uint64_t y; // Y (used in obsolete multiplication)
struct {
uint64_t value:32; // The actual value stored in y
uint64_t :32; // reserved bits
} yFields;
};
union {
uint8_t ccr; // Condition Code Register
struct {
union {
uint8_t icc:4; // 32-bit condition codes
struct {
uint8_t c:1; // Carry
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
} iccFields;
};
union {
uint8_t xcc:4; // 64-bit condition codes
struct {
uint8_t c:1; // Carry
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
} xccFields;
};
} ccrFields;
};
uint64_t y; // Y (used in obsolete multiplication)
uint8_t ccr; // Condition Code Register
uint8_t asi; // Address Space Identifier
union {
uint64_t tick; // Hardware clock-tick counter
struct {
int64_t counter:63; // Clock-tick count
uint64_t npt:1; // Non-priveleged trap
} tickFields;
};
union {
uint8_t fprs; // Floating-Point Register State
struct {
uint8_t dl:1; // Dirty lower
uint8_t du:1; // Dirty upper
uint8_t fef:1; // FPRS enable floating-Point
} fprsFields;
};
union {
uint64_t gsr; //General Status Register
struct {
uint64_t mask:32;
uint64_t :4;
uint64_t im:1;
uint64_t irnd:2;
uint64_t :17;
uint64_t scale:5;
uint64_t align:3;
} gsrFields;
};
union {
uint64_t softint;
struct {
uint64_t tm:1;
uint64_t int_level:14;
uint64_t sm:1;
} softintFields;
};
union {
uint64_t tick_cmpr; // Hardware tick compare registers
struct {
uint64_t tick_cmpr:63; // Clock-tick count
uint64_t int_dis:1; // Non-priveleged trap
} tick_cmprFields;
};
union {
uint64_t stick; // Hardware clock-tick counter
struct {
int64_t :63; // Not used, storage in SparcSystem
uint64_t npt:1; // Non-priveleged trap
} stickFields;
};
union {
uint64_t stick_cmpr; // Hardware tick compare registers
struct {
uint64_t tick_cmpr:63; // Clock-tick count
uint64_t int_dis:1; // Non-priveleged trap
} stick_cmprFields;
};
uint64_t tick; // Hardware clock-tick counter
uint8_t fprs; // Floating-Point Register State
uint64_t gsr; // General Status Register
uint64_t softint;
uint64_t tick_cmpr; // Hardware tick compare registers
uint64_t stick; // Hardware clock-tick counter
uint64_t stick_cmpr; // Hardware tick compare registers
/* Privileged Registers */
@ -201,37 +118,12 @@ namespace SparcISA
// previous trap level)
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
// previous trap level)
union {
uint64_t tstate[MaxTL]; // Trap State
struct {
//Values are from previous trap level
uint64_t cwp:5; // Current Window Pointer
uint64_t :3; // Reserved bits
uint64_t pstate:13; // Process State
uint64_t :3; // Reserved bits
uint64_t asi:8; // Address Space Identifier
uint64_t ccr:8; // Condition Code Register
uint64_t gl:8; // Global level
} tstateFields[MaxTL];
};
uint64_t tstate[MaxTL]; // Trap State
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
// on the previous level)
uint64_t tba; // Trap Base Address
union {
uint16_t pstate; // Process State Register
struct {
uint16_t :1; // reserved
uint16_t ie:1; // Interrupt enable
uint16_t priv:1; // Privelege mode
uint16_t am:1; // Address mask
uint16_t pef:1; // PSTATE enable floating-point
uint16_t :1; // reserved2
uint16_t mm:2; // Memory Model
uint16_t tle:1; // Trap little-endian
uint16_t cle:1; // Current little-endian
} pstateFields;
};
uint16_t pstate; // Process State Register
uint8_t tl; // Trap Level
uint8_t pil; // Process Interrupt Register
uint8_t cwp; // Current Window Pointer
@ -239,97 +131,20 @@ namespace SparcISA
uint8_t canrestore; // Restorable windows
uint8_t cleanwin; // Clean windows
uint8_t otherwin; // Other windows
union {
uint8_t wstate; // Window State
struct {
uint8_t normal:3; // Bits TT<4:2> are set to on a normal
// register window trap
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
// register window trap
} wstateFields;
};
uint8_t wstate; // Window State
uint8_t gl; // Global level register
/** Hyperprivileged Registers */
union {
uint64_t hpstate; // Hyperprivileged State Register
struct {
uint8_t tlz: 1;
uint8_t :1;
uint8_t hpriv:1;
uint8_t :2;
uint8_t red:1;
uint8_t :4;
uint8_t ibe:1;
uint8_t id:1;
} hpstateFields;
};
uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
uint64_t hpstate; // Hyperprivileged State Register
uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
uint64_t hintp;
uint64_t htba; // Hyperprivileged Trap Base Address register
union {
uint64_t hstick_cmpr; // Hardware tick compare registers
struct {
uint64_t tick_cmpr:63; // Clock-tick count
uint64_t int_dis:1; // Non-priveleged trap
} hstick_cmprFields;
};
uint64_t strandStatusReg; // Per strand status register
uint64_t htba; // Hyperprivileged Trap Base Address register
uint64_t hstick_cmpr; // Hardware tick compare registers
uint64_t strandStatusReg;// Per strand status register
/** Floating point misc registers. */
union {
uint64_t fsr; // Floating-Point State Register
struct {
union {
uint64_t cexc:5; // Current excpetion
struct {
uint64_t nxc:1; // Inexact
uint64_t dzc:1; // Divide by zero
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
} cexcFields;
};
union {
uint64_t aexc:5; // Accrued exception
struct {
uint64_t nxc:1; // Inexact
uint64_t dzc:1; // Divide by zero
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
} aexcFields;
};
uint64_t fcc0:2; // Floating-Point condtion codes
uint64_t :1; // Reserved bits
uint64_t qne:1; // Deferred trap queue not empty
// with no queue, it should read 0
uint64_t ftt:3; // Floating-Point trap type
uint64_t ver:3; // Version (of the FPU)
uint64_t :2; // Reserved bits
uint64_t ns:1; // Nonstandard floating point
union {
uint64_t tem:5; // Trap Enable Mask
struct {
uint64_t nxm:1; // Inexact
uint64_t dzm:1; // Divide by zero
uint64_t ufm:1; // Underflow
uint64_t ofm:1; // Overflow
uint64_t nvm:1; // Invalid operand
} temFields;
};
uint64_t :2; // Reserved bits
uint64_t rd:2; // Rounding direction
uint64_t fcc1:2; // Floating-Point condition codes
uint64_t fcc2:2; // Floating-Point condition codes
uint64_t fcc3:2; // Floating-Point condition codes
uint64_t :26; // Reserved bits
} fsrFields;
};
uint64_t fsr; // Floating-Point State Register
ASI implicitInstAsi;
ASI implicitDataAsi;
@ -391,8 +206,8 @@ namespace SparcISA
protected:
bool isHyperPriv() { return hpstateFields.hpriv; }
bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
bool isHyperPriv() { return (hpstate & (1 << 2)); }
bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
bool isNonPriv() { return !isPriv(); }
inline void setImplicitAsis();
};

3
src/arch/sparc/process.cc
View file

@ -29,6 +29,7 @@
* Ali Saidi
*/
#include "arch/sparc/asi.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/process.hh"
#include "base/loader/object_file.hh"
@ -105,6 +106,8 @@ SparcLiveProcess::startup()
threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
//Set the trap level to 0
threadContexts[0]->setMiscReg(MISCREG_TL, 0);
//Set the ASI register to something fixed
threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
}
m5_auxv_t buildAuxVect(int64_t type, int64_t val)

42
src/arch/sparc/system.cc
View file

@ -42,39 +42,46 @@
using namespace BigEndianGuest;
SparcSystem::SparcSystem(Params *p)
: System(p), sysTick(0)
: System(p), sysTick(0),funcRomPort(p->name + "-fport")
{
resetSymtab = new SymbolTable;
hypervisorSymtab = new SymbolTable;
openbootSymtab = new SymbolTable;
Port *rom_port;
rom_port = params()->rom->getPort("functional");
funcRomPort.setPeer(rom_port);
rom_port->setPeer(&funcRomPort);
/**
* Load the boot code, and hypervisor into memory.
*/
// Read the reset binary
reset = createObjectFile(params()->reset_bin);
reset = createObjectFile(params()->reset_bin, true);
if (reset == NULL)
fatal("Could not load reset binary %s", params()->reset_bin);
// Read the openboot binary
openboot = createObjectFile(params()->openboot_bin);
openboot = createObjectFile(params()->openboot_bin, true);
if (openboot == NULL)
fatal("Could not load openboot bianry %s", params()->openboot_bin);
// Read the hypervisor binary
hypervisor = createObjectFile(params()->hypervisor_bin);
hypervisor = createObjectFile(params()->hypervisor_bin, true);
if (hypervisor == NULL)
fatal("Could not load hypervisor binary %s", params()->hypervisor_bin);
// Load reset binary into memory
reset->loadSections(&functionalPort, SparcISA::LoadAddrMask);
reset->setTextBase(params()->reset_addr);
reset->loadSections(&funcRomPort);
// Load the openboot binary
openboot->loadSections(&functionalPort, SparcISA::LoadAddrMask);
openboot->setTextBase(params()->openboot_addr);
openboot->loadSections(&funcRomPort);
// Load the hypervisor binary
hypervisor->loadSections(&functionalPort, SparcISA::LoadAddrMask);
hypervisor->setTextBase(params()->hypervisor_addr);
hypervisor->loadSections(&funcRomPort);
// load symbols
if (!reset->loadGlobalSymbols(resetSymtab))
@ -141,8 +148,13 @@ SparcSystem::unserialize(Checkpoint *cp, const std::string &section)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
SimObjectParam<PhysicalMemory *> physmem;
SimObjectParam<PhysicalMemory *> rom;
SimpleEnumParam<System::MemoryMode> mem_mode;
Param<Addr> reset_addr;
Param<Addr> hypervisor_addr;
Param<Addr> openboot_addr;
Param<std::string> kernel;
Param<std::string> reset_bin;
Param<std::string> hypervisor_bin;
@ -150,8 +162,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
Param<Tick> boot_cpu_frequency;
Param<std::string> boot_osflags;
Param<uint64_t> system_type;
Param<uint64_t> system_rev;
Param<std::string> readfile;
Param<unsigned int> init_param;
@ -160,8 +170,14 @@ END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
INIT_PARAM(physmem, "phsyical memory"),
INIT_PARAM(rom, "ROM for boot code"),
INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
System::MemoryModeStrings),
INIT_PARAM(reset_addr, "Address that reset should be loaded at"),
INIT_PARAM(hypervisor_addr, "Address that hypervisor should be loaded at"),
INIT_PARAM(openboot_addr, "Address that openboot should be loaded at"),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(reset_bin, "file that contains the reset code"),
INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"),
@ -169,8 +185,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
"a"),
INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10),
INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0)
@ -182,16 +196,18 @@ CREATE_SIM_OBJECT(SparcSystem)
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
p->rom = rom;
p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->reset_addr = reset_addr;
p->hypervisor_addr = hypervisor_addr;
p->openboot_addr = openboot_addr;
p->reset_bin = reset_bin;
p->hypervisor_bin = hypervisor_bin;
p->openboot_bin = openboot_bin;
p->boot_osflags = boot_osflags;
p->init_param = init_param;
p->readfile = readfile;
p->system_type = system_type;
p->system_rev = system_rev;
return new SparcSystem(p);
}

9
src/arch/sparc/system.hh
View file

@ -45,12 +45,14 @@ class SparcSystem : public System
public:
struct Params : public System::Params
{
PhysicalMemory *rom;
Addr reset_addr;
Addr hypervisor_addr;
Addr openboot_addr;
std::string reset_bin;
std::string hypervisor_bin;
std::string openboot_bin;
std::string boot_osflags;
uint64_t system_type;
uint64_t system_rev;
};
SparcSystem(Params *p);
@ -87,6 +89,9 @@ class SparcSystem : public System
/** System Tick for syncronized tick across all cpus. */
Tick sysTick;
/** functional port to ROM */
FunctionalPort funcRomPort;
protected:
const Params *params() const { return (const Params *)_params; }

6
src/base/loader/object_file.cc
View file

@ -45,6 +45,7 @@
#include "base/loader/ecoff_object.hh"
#include "base/loader/aout_object.hh"
#include "base/loader/elf_object.hh"
#include "base/loader/raw_object.hh"
#include "mem/translating_port.hh"
@ -107,7 +108,7 @@ ObjectFile::close()
ObjectFile *
createObjectFile(const string &fname)
createObjectFile(const string &fname, bool raw)
{
// open the file
int fd = open(fname.c_str(), O_RDONLY);
@ -141,6 +142,9 @@ createObjectFile(const string &fname)
return fileObj;
}
if (raw)
return RawObject::tryFile(fname, fd, len, fileData);
// don't know what it is
close(fd);
munmap(fileData, len);

4
src/base/loader/object_file.hh
View file

@ -114,9 +114,11 @@ class ObjectFile
size_t textSize() const { return text.size; }
size_t dataSize() const { return data.size; }
size_t bssSize() const { return bss.size; }
void setTextBase(Addr a) { text.baseAddr = a; }
};
ObjectFile *createObjectFile(const std::string &fname);
ObjectFile *createObjectFile(const std::string &fname, bool raw = false);
#endif // __OBJECT_FILE_HH__

72
src/base/loader/raw_object.cc Normal file
View file

@ -0,0 +1,72 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
*/
#include "base/loader/raw_object.hh"
#include "base/trace.hh"
ObjectFile *
RawObject::tryFile(const std::string &fname, int fd, size_t len, uint8_t *data)
{
return new RawObject(fname, fd, len, data, ObjectFile::UnknownArch,
ObjectFile::UnknownOpSys);
}
RawObject::RawObject(const std::string &_filename, int _fd, size_t _len,
uint8_t *_data, Arch _arch, OpSys _opSys)
: ObjectFile(_filename, _fd, _len, _data, _arch, _opSys)
{
text.baseAddr = 0;
text.size = len;
text.fileImage = fileData;
data.baseAddr = 0;
data.size = 0;
data.fileImage = NULL;
bss.baseAddr = 0;
bss.size = 0;
bss.fileImage = NULL;
DPRINTFR(Loader, "text: 0x%x %d\ndata: 0x%x %d\nbss: 0x%x %d\n",
text.baseAddr, text.size, data.baseAddr, data.size,
bss.baseAddr, bss.size);
}
bool
RawObject::loadGlobalSymbols(SymbolTable *symtab)
{
return true;
}
bool
RawObject::loadLocalSymbols(SymbolTable *symtab)
{
return true;
}

53
src/base/loader/raw_object.hh Normal file
View file

@ -0,0 +1,53 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ali Saidi
*/
#ifndef __BASE_LOADER_RAW_OBJECT_HH__
#define __BASE_LOADER_RAW_OBJECT_HH__
#include "base/loader/object_file.hh"
class RawObject: public ObjectFile
{
protected:
RawObject(const std::string &_filename, int _fd, size_t _len,
uint8_t *_data, Arch _arch, OpSys _opSys);
public:
virtual ~RawObject() {}
virtual bool loadGlobalSymbols(SymbolTable *symtab);
virtual bool loadLocalSymbols(SymbolTable *symtab);
static ObjectFile *tryFile(const std::string &fname, int fd, size_t len,
uint8_t *data);
};
#endif // __BASE_LOADER_RAW_OBJECT_HH__

137
src/cpu/exetrace.cc
View file

@ -37,6 +37,7 @@
#include <sys/shm.h>
#include "arch/regfile.hh"
#include "arch/utility.hh"
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
@ -67,7 +68,6 @@ Trace::InstRecord::dump(ostream &outs)
if (flags[PRINT_REG_DELTA])
{
#if THE_ISA == SPARC_ISA
#if 0
//Don't print what happens for each micro-op, just print out
//once at the last op, and for regular instructions.
if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
@ -83,23 +83,19 @@ Trace::InstRecord::dump(ostream &outs)
uint64_t newVal;
static const char * prefixes[4] = {"G", "O", "L", "I"};
char buf[256];
sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
outs << buf;
sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
outs << buf;
outs << hex;
outs << "PC = " << thread->readNextPC();
outs << " NPC = " << thread->readNextNPC();
newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
if(newVal != ccr)
{
sprintf(buf, " CCR = 0x%016llx", newVal);
outs << buf;
outs << " CCR = " << newVal;
ccr = newVal;
}
newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
if(newVal != y)
{
sprintf(buf, " Y = 0x%016llx", newVal);
outs << buf;
outs << " Y = " << newVal;
y = newVal;
}
for(int y = 0; y < 4; y++)
@ -110,8 +106,7 @@ Trace::InstRecord::dump(ostream &outs)
newVal = thread->readIntReg(index);
if(regs[index] != newVal)
{
sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
outs << buf;
outs << " " << prefixes[y] << dec << x << " = " << hex << newVal;
regs[index] = newVal;
}
}
@ -121,14 +116,12 @@ Trace::InstRecord::dump(ostream &outs)
newVal = thread->readFloatRegBits(2 * y, 64);
if(floats[y] != newVal)
{
sprintf(buf, " F%d = 0x%016llx", 2 * y, newVal);
outs << buf;
outs << " F" << dec << (2 * y) << " = " << hex << newVal;
floats[y] = newVal;
}
}
outs << endl;
outs << dec << endl;
}
#endif
#endif
}
else if (flags[INTEL_FORMAT]) {
@ -231,6 +224,7 @@ Trace::InstRecord::dump(ostream &outs)
//
outs << endl;
}
#if THE_ISA == SPARC_ISA
// Compare
if (flags[LEGION_LOCKSTEP])
{
@ -239,57 +233,76 @@ Trace::InstRecord::dump(ostream &outs)
bool diffInst = false;
bool diffRegs = false;
while (!compared) {
if (shared_data->flags == OWN_M5) {
if (shared_data->pc != PC)
diffPC = true;
if (shared_data->instruction != staticInst->machInst)
diffInst = true;
for (int i = 0; i < TheISA::NumIntRegs; i++) {
if (thread->readIntReg(i) != shared_data->intregs[i])
diffRegs = true;
}
if (diffPC || diffInst || diffRegs ) {
outs << "Differences found between M5 and Legion:";
if (diffPC)
outs << " PC";
if (diffInst)
outs << " Instruction";
if (diffRegs)
outs << " IntRegs";
outs << endl;
outs << "M5 PC: " << setw(20) << "0x" << hex << PC;
outs << "Legion PC: " << setw(20) << "0x" << hex <<
shared_data->pc << endl;
outs << "M5 Instruction: " << staticInst->machInst << "("
<< staticInst->disassemble(PC, debugSymbolTable)
<< ")" << "Legion Instruction: " <<
shared_data->instruction << "("
/*<< legionInst->disassemble(shared_data->pc,
debugSymbolTable)*/
<< ")" << endl;
if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
while (!compared) {
if (shared_data->flags == OWN_M5) {
if (shared_data->pc != PC)
diffPC = true;
if (shared_data->instruction != staticInst->machInst)
diffInst = true;
for (int i = 0; i < TheISA::NumIntRegs; i++) {
outs << setw(16) << "0x" << hex << thread->readIntReg(i)
<< setw(16) << "0x" << hex << shared_data->intregs[i];
if (thread->readIntReg(i) != shared_data->intregs[i])
outs << "<--- Different";
outs << endl;
diffRegs = true;
}
if (diffPC || diffInst || diffRegs ) {
outs << "Differences found between M5 and Legion:";
if (diffPC)
outs << " [PC]";
if (diffInst)
outs << " [Instruction]";
if (diffRegs)
outs << " [IntRegs]";
outs << endl << endl;;
outs << setfill(' ') << setw(15)
<< "M5 PC: " << "0x"<< setw(16) << setfill('0')
<< hex << PC << endl;
outs << setfill(' ') << setw(15)
<< "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
<< shared_data->pc << endl << endl;
outs << setfill(' ') << setw(15)
<< "M5 Inst: " << "0x"<< setw(8)
<< setfill('0') << hex << staticInst->machInst
<< staticInst->disassemble(PC, debugSymbolTable)
<< endl;
StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread));
outs << setfill(' ') << setw(15)
<< " Legion Inst: "
<< "0x" << setw(8) << setfill('0') << hex
<< shared_data->instruction
<< legionInst->disassemble(shared_data->pc, debugSymbolTable)
<< endl;
outs << endl;
static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
for(int y = 0; y < 4; y++)
{
for(int x = 0; x < 8; x++)
{
outs << regtypes[y] << x << " " ;
outs << "0x" << hex << setw(16) << thread->readIntReg(y*8+x);
if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x])
outs << " X ";
else
outs << " | ";
outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x]
<< endl;
}
}
fatal("Differences found between Legion and M5\n");
}
compared = true;
shared_data->flags = OWN_LEGION;
}
compared = true;
shared_data->flags = OWN_LEGION;
}
}
} // while
} // if not microop
}
#endif
}

4
src/cpu/m5legion_interface.h
View file

@ -30,7 +30,7 @@
#include <unistd.h>
#define VERSION 0xA1000001
#define VERSION 0xA1000002
#define OWN_M5 0x000000AA
#define OWN_LEGION 0x00000055
@ -41,7 +41,7 @@ typedef struct {
uint32_t version;
uint64_t pc;
uint64_t instruction;
uint32_t instruction;
uint64_t intregs[32];
} SharedData;

6
src/kern/tru64/tru64.hh
View file

@ -511,7 +511,7 @@ class Tru64 : public OperatingSystem
tc->setFloatRegBits(i, htog(sc->sc_fpregs[i]));
}
tc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr));
tc->setMiscReg(AlphaISA::MISCREG_FPCR, htog(sc->sc_fpcr));
return 0;
}
@ -653,7 +653,7 @@ class Tru64 : public OperatingSystem
ssp->nxm_sysevent = htog(0);
if (i == 0) {
uint64_t uniq = tc->readMiscReg(TheISA::Uniq_DepTag);
uint64_t uniq = tc->readMiscReg(AlphaISA::MISCREG_UNIQ);
ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset));
ssp->nxm_u.nxm_active = htog(uniq | 1);
}
@ -693,7 +693,7 @@ class Tru64 : public OperatingSystem
tc->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0));
tc->setIntReg(27/*t12*/, gtoh(attrp->registers.pc));
tc->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp));
tc->setMiscReg(TheISA::Uniq_DepTag, uniq_val);
tc->setMiscReg(AlphaISA::MISCREG_UNIQ, uniq_val);
tc->setPC(gtoh(attrp->registers.pc));
tc->setNextPC(gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst));

4
src/mem/physical.cc
View file

@ -191,7 +191,9 @@ PhysicalMemory::checkLockedAddrList(Request *req)
void
PhysicalMemory::doFunctionalAccess(PacketPtr pkt)
{
assert(pkt->getAddr() + pkt->getSize() <= params()->addrRange.size());
assert(pkt->getAddr() + pkt->getSize() > params()->addrRange.start &&
pkt->getAddr() + pkt->getSize() <= params()->addrRange.start +
params()->addrRange.size());
if (pkt->isRead()) {
if (pkt->req->isLocked()) {

13
src/python/m5/objects/BaseCPU.py
View file

@ -3,7 +3,9 @@ from m5.params import *
from m5.proxy import *
from m5 import build_env
from AlphaTLB import AlphaDTB, AlphaITB
from SparcTLB import SparcDTB, SparcITB
from Bus import Bus
import sys
class BaseCPU(SimObject):
type = 'BaseCPU'
@ -13,8 +15,15 @@ class BaseCPU(SimObject):
cpu_id = Param.Int("CPU identifier")
if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
if build_env['TARGET_ISA'] == 'sparc':
dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
itb = Param.SparcITB(SparcITB(), "Instruction TLB")
elif build_env['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
else:
print "Unknown architecture, can't pick TLBs"
sys.exit(1)
else:
workload = VectorParam.Process("processes to run")

14
src/python/m5/objects/SparcTLB.py Normal file
View file

@ -0,0 +1,14 @@
from m5.SimObject import SimObject
from m5.params import *
class SparcTLB(SimObject):
type = 'SparcTLB'
abstract = True
size = Param.Int("TLB size")
class SparcDTB(SparcTLB):
type = 'SparcDTB'
size = 64
class SparcITB(SparcTLB):
type = 'SparcITB'
size = 48

19
src/python/m5/objects/System.py
View file

@ -2,6 +2,7 @@ from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from m5 import build_env
from PhysicalMemory import *
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
@ -24,3 +25,21 @@ class AlphaSystem(System):
pal = Param.String("file that contains palcode")
system_type = Param.UInt64("Type of system we are emulating")
system_rev = Param.UInt64("Revision of system we are emulating")
class SparcSystem(System):
type = 'SparcSystem'
_rom_base = 0xfff0000000
# ROM for OBP/Reset/Hypervisor
rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')),
"Memory to hold the ROM data")
reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
"Address to load hypervisor at")
openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
"Address to load openboot at")
reset_bin = Param.String("file that contains the reset code")
hypervisor_bin = Param.String("file that contains the hypervisor code")
openboot_bin = Param.String("file that contains the openboot code")

5
src/python/m5/params.py
View file

@ -369,6 +369,11 @@ class Addr(CheckedInt):
except TypeError:
self.value = long(value)
self._check()
def __add__(self, other):
if isinstance(other, Addr):
return self.value + other.value
else:
return self.value + other
class MetaRange(type):