Add L2 cache option to fs.py --l2cache
--HG-- extra : convert_revision : 5bdd1129c3b23e91d441e7b83f6a824ef7740fab
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2 changed files with 20 additions and 1 deletions
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@ -37,3 +37,10 @@ class L1Cache(BaseCache):
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tgts_per_mshr = 5
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protocol = CoherenceProtocol(protocol='moesi')
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class L2Cache(BaseCache):
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assoc = 8
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block_size = 64
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latency = 10
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mshrs = 20
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tgts_per_mshr = 12
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@ -47,6 +47,7 @@ config_root = os.path.dirname(config_path)
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parser = optparse.OptionParser()
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# Benchmark options
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parser.add_option("--l2cache", action="store_true")
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parser.add_option("--dual", action="store_true",
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help="Simulate two systems attached with an ethernet link")
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parser.add_option("-b", "--benchmark", action="store", type="string",
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@ -93,12 +94,23 @@ else:
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
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np = options.num_cpus
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if options.l2cache:
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test_sys.l2 = L2Cache(size = '2MB')
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test_sys.tol2bus = Bus()
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test_sys.l2.cpu_side = test_sys.tol2bus.port
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test_sys.l2.mem_side = test_sys.membus.port
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test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
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for i in xrange(np):
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if options.caches:
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test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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test_sys.cpu[i].connectMemPorts(test_sys.membus)
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if options.l2cache:
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test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
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else:
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test_sys.cpu[i].connectMemPorts(test_sys.membus)
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if len(bm) == 2:
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drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
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