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Merge zizzer:/bk/newmem

Browse source 
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 8d61b474428d494b1a5382e4cf95934ad54e35dd
This commit is contained in:
Ron Dreslinski 2006-11-14 18:41:37 -05:00
parent 7cd05a998d 069c7c30d1
commit 4fbbb74a5c
1 changed files with 12 additions and 3 deletions
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15
src/cpu/simple/timing.cc
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@ -290,6 +290,8 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// memory system takes ownership of packet
dcache_pkt = NULL;
}
} else {
delete req;
}
// This will need a new way to tell if it has a dcache attached.
@ -375,6 +377,8 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
dcache_pkt = NULL;
}
}
} else {
delete req;
}
// This will need a new way to tell if it's hooked up to a cache or not.
@ -457,6 +461,8 @@ TimingSimpleCPU::fetch()
ifetch_pkt = NULL;
}
} else {
delete ifetch_req;
delete ifetch_pkt;
// fetch fault: advance directly to next instruction (fault handler)
advanceInst(fault);
}
@ -490,13 +496,13 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
_status = Running;
delete pkt->req;
delete pkt;
numCycles += curTick - previousTick;
previousTick = curTick;
if (getState() == SimObject::Draining) {
delete pkt->req;
delete pkt;
completeDrain();
return;
}
@ -528,6 +534,9 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
postExecute();
advanceInst(fault);
}
delete pkt->req;
delete pkt;
}
void