Ali Saidi 92c5a5c8cb More changes to get SPARC fs closer. Now at 1.2M cycles before difference ... configs/common/FSConfig.py: seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config. src/arch/sparc/isa/decoder.isa: change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect src/arch/sparc/miscregfile.cc: For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this). Use instruction count from cpu rather than cycles because that is what legion does we can change it back after were done with legion src/base/bitfield.hh: add a new function mbits() that just masks off bits of interest but doesn't shift src/cpu/base.cc: src/cpu/base.hh: add instruction count to cpu src/cpu/exetrace.cc: src/cpu/m5legion_interface.h: compare instruction count between legion and m5 too src/cpu/simple/atomic.cc: change asserts of packet success to if panics wrapped with NDEBUG defines so we can get some more useful information when we have a bad address src/dev/isa_fake.cc: src/dev/isa_fake.hh: src/python/m5/objects/Device.py: expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses src/python/m5/objects/System.py: convert some tabs to spaces src/python/m5/objects/T1000.py: add more fake devices for each l1 bank and each memory controller --HG-- extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276		2006-12-04 00:54:40 -05:00
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Benchmarks.py	Add mutex test to Benchmarks.py.	2006-10-22 12:52:58 -04:00
Caches.py	Add L2 cache option to fs.py --l2cache	2006-11-15 18:22:15 -05:00
cpu2000.py	Implement a single config file to encompass all of the SPEC	2006-11-16 13:10:38 -08:00
FSConfig.py	More changes to get SPARC fs closer. Now at 1.2M cycles before difference	2006-12-04 00:54:40 -05:00
Options.py	decouple the switch option from the warmup period option - parsing was confused otherwise, oops.	2006-10-30 14:12:15 -05:00
Simulation.py	Include check for making sure caches are enabled.	2006-11-26 11:46:58 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00