2009-10-27 17:24:40 +01:00
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---------- Begin Simulation Statistics ----------
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2013-11-01 16:56:34 +01:00
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sim_seconds 0.000019 # Number of seconds simulated
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2014-05-10 00:58:50 +02:00
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sim_ticks 19030500 # Number of ticks simulated
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final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2009-10-27 17:24:40 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2014-06-22 23:33:09 +02:00
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host_inst_rate 17395 # Simulator instruction rate (inst/s)
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host_op_rate 17394 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 57147442 # Simulator tick rate (ticks/s)
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host_mem_usage 218304 # Number of bytes of host memory used
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host_seconds 0.33 # Real time elapsed on the host
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2012-08-15 16:38:05 +02:00
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sim_insts 5792 # Number of instructions simulated
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sim_ops 5792 # Number of ops (including micro ops) simulated
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2014-01-24 22:29:33 +01:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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2012-11-02 17:50:06 +01:00
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system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
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2014-05-10 00:58:50 +02:00
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system.physmem.bw_read::cpu.inst 1160242768 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 339665274 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1499908042 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1160242768 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1160242768 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1160242768 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 339665274 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1499908042 # Total bandwidth to/from this memory (bytes/s)
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2013-11-01 16:56:34 +01:00
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system.physmem.readReqs 446 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 70 # Per bank write bursts
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system.physmem.perBankRdBursts::1 42 # Per bank write bursts
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system.physmem.perBankRdBursts::2 54 # Per bank write bursts
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system.physmem.perBankRdBursts::3 59 # Per bank write bursts
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system.physmem.perBankRdBursts::4 53 # Per bank write bursts
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system.physmem.perBankRdBursts::5 61 # Per bank write bursts
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system.physmem.perBankRdBursts::6 52 # Per bank write bursts
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system.physmem.perBankRdBursts::7 13 # Per bank write bursts
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system.physmem.perBankRdBursts::8 8 # Per bank write bursts
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system.physmem.perBankRdBursts::9 28 # Per bank write bursts
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system.physmem.perBankRdBursts::10 2 # Per bank write bursts
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system.physmem.perBankRdBursts::11 0 # Per bank write bursts
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system.physmem.perBankRdBursts::12 0 # Per bank write bursts
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system.physmem.perBankRdBursts::13 0 # Per bank write bursts
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system.physmem.perBankRdBursts::14 4 # Per bank write bursts
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system.physmem.perBankRdBursts::15 0 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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2014-05-10 00:58:50 +02:00
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system.physmem.totGap 18902000 # Total gap between requests
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2013-11-01 16:56:34 +01:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 446 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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2014-06-22 23:33:09 +02:00
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system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see
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2013-11-01 16:56:34 +01:00
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system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
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2013-05-30 18:54:18 +02:00
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system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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2013-01-31 13:49:16 +01:00
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
2014-03-23 16:12:19 +01:00
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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|
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|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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|
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|
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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2014-05-10 00:58:50 +02:00
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system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation
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2014-06-22 23:33:09 +02:00
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|
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system.physmem.bytesPerActivate::gmean 199.719469 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 351.121005 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 27 35.06% 35.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 18 23.38% 58.44% # Bytes accessed per row activation
|
2014-05-10 00:58:50 +02:00
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system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation
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2014-06-22 23:33:09 +02:00
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system.physmem.totQLat 3354000 # Total ticks spent queuing
|
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system.physmem.totMemAccLat 11716500 # Total ticks spent from burst creation until serviced by the DRAM
|
2013-11-01 16:56:34 +01:00
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|
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system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.avgQLat 7520.18 # Average queueing delay per DRAM burst
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.avgMemAccLat 26270.18 # Average memory access latency per DRAM burst
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
|
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.busUtil 11.72 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.readRowHits 358 # Number of row buffer hits during reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.avgGap 42381.17 # Average gap between requests
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
|
|
|
|
|
system.physmem.memoryStateTime::REF 520000 # Time in different power states
|
|
|
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
|
|
|
system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
|
|
|
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
|
|
|
system.membus.throughput 1499908042 # Throughput (bytes/s)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.trans_dist::ReadReq 399 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 399 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
|
2013-08-19 09:52:36 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.data_through_bus 28544 # Total data (bytes)
|
|
|
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks)
|
|
|
|
|
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
|
|
|
|
system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks)
|
2014-05-10 00:58:50 +02:00
|
|
|
system.membus.respLayer1.utilization 22.0 # Layer utilization (%)
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.branchPred.lookups 2252 # Number of BP lookups
|
|
|
|
|
system.cpu.branchPred.condPredicted 1816 # Number of conditional branches predicted
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.branchPred.BTBLookups 1865 # Number of BTB lookups
|
|
|
|
|
system.cpu.branchPred.BTBHits 610 # Number of BTB hits
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.branchPred.BTBHitPct 32.707775 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target.
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 9 # Number of system calls
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.numCycles 38062 # number of cpu cycles simulated
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.fetch.icacheStallCycles 7462 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 13226 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 2252 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 809 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 2276 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 1296 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.BlockedCycles 871 # Number of cycles fetch has spent blocked
|
|
|
|
|
system.cpu.fetch.CacheLines 1823 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 11476 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 1.152492 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.564431 # Number of instructions fetched each cycle (Total)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.fetch.rateDist::0 9200 80.17% 80.17% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 178 1.55% 81.72% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 178 1.55% 83.27% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 145 1.26% 84.53% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 228 1.99% 86.52% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 133 1.16% 87.68% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 261 2.27% 89.95% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 110 0.96% 90.91% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 1043 9.09% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.fetch.rateDist::total 11476 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.059167 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 0.347486 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 7479 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 1089 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 2174 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 20 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 714 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch
|
2013-01-31 13:49:16 +01:00
|
|
|
system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.decode.DecodedInsts 11804 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 714 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 7660 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 2016 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 428 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 11368 # Number of instructions processed by rename
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.rename.LQFullEvents 165 # Number of times rename has blocked due to LQ full
|
|
|
|
|
system.cpu.rename.SQFullEvents 241 # Number of times rename has blocked due to SQ full
|
|
|
|
|
system.cpu.rename.RenamedOperands 9753 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 18286 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 18260 # Number of integer rename lookups
|
2013-10-16 16:44:12 +02:00
|
|
|
system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.rename.UndoneMaps 4755 # Number of HB maps that are undone due to squashing
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.rename.skidInsts 259 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 2025 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 1841 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.iqInstsAdded 10356 # Number of instructions added to the IQ (excludes non-spec)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.iqInstsIssued 8929 # Number of instructions issued
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 4296 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 3542 # Number of squashed operands that are examined and possibly removed from graph
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::samples 11476 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 0.778059 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.545863 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::0 8265 72.02% 72.02% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 1011 8.81% 80.83% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 683 5.95% 86.78% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 469 4.09% 90.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 473 4.12% 94.99% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 313 2.73% 97.72% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 182 1.59% 99.30% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 44 0.38% 99.69% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::total 11476 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.fu_full::IntAlu 11 6.21% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 75 42.37% 48.59% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 91 51.41% 100.00% # attempts to use FU when none available
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 5495 61.54% 61.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 1798 20.14% 81.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 1634 18.30% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 8929 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 0.234591 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.019823 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 29690 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 14680 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 9072 # Number of integer alu accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1064 # Number of loads squashed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 795 # Number of stores squashed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 714 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 160 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 10413 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 2025 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 1841 # Number of dispatched store instructions
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.iewExecutedInsts 8526 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 1682 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.exec_refs 3211 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 1353 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 1529 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.224003 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 8294 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 8178 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 4388 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 6958 # num instructions consuming a value
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.wb_rate 0.214860 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.630641 # average fanout of values written-back
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 4620 # The number of squashed insts skipped by commit
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::samples 10762 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.538190 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.389247 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 8538 79.33% 79.33% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 887 8.24% 87.58% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 552 5.13% 92.71% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 240 2.23% 94.94% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 177 1.64% 96.58% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 96 0.89% 97.47% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 118 1.10% 98.57% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 47 0.44% 99.01% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 107 0.99% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 10762 # Number of insts commited each cycle
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.committedInsts 5792 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.refs 2007 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 961 # Number of loads committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.membars 7 # Number of memory barriers committed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.branches 1037 # Number of branches committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.function_calls 103 # Number of function calls committed.
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.rob.rob_reads 21067 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 21539 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 26586 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.committedInsts 5792 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.int_regfile_reads 13502 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 7065 # number of integer regfile writes
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 588250 # Layer occupancy (ticks)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 162000 # Layer occupancy (ticks)
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.tags.tagsinuse 169.076059 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 1380 # Total number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.tags.avg_refs 3.931624 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 169.076059 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.082557 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.082557 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.tags.tag_accesses 3997 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 3997 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1380 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 1380 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 1380 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 1380 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 1380 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 1380 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 443 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 443 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 443 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 443 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 443 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 443 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 29586250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 29586250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 29586250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 29586250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 29586250 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 29586250 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1823 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 1823 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 1823 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 1823 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 1823 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 1823 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243006 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.243006 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.243006 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.243006 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.243006 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.243006 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66786.117381 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 66786.117381 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 66786.117381 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 66786.117381 # average overall miss latency
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24098750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 24098750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24098750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 24098750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24098750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 24098750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192540 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.192540 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.192540 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68657.407407 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68657.407407 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.tags.tagsinuse 199.437860 # Cycle average of tags in use
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.936913 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.500947 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005125 # Average percentage of cache occupancy
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.006086 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 215 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 4070 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 4070 # Number of data accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 7 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 345 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23687250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4073750 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 27761000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3627250 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3627250 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 23687250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7701000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 31388250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 23687250 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7701000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 31388250 # number of overall miss cycles
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses)
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982906 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.982759 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68658.695652 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75439.814815 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69576.441103 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77175.531915 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77175.531915 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 70377.242152 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68658.695652 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76247.524752 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 70377.242152 # average overall miss latency
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2009-10-27 17:24:40 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses
|
2012-07-09 18:35:41 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19339750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3409250 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22749000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3052750 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3052750 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19339750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6462000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 25801750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19339750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6462000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 25801750 # number of overall MSHR miss cycles
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56057.246377 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63134.259259 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57015.037594 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64952.127660 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64952.127660 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.tags.tagsinuse 63.722947 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 2180 # Total number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.tags.avg_refs 21.372549 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 63.722947 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.015557 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.015557 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.tags.tag_accesses 5332 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 5332 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1465 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 1465 # number of ReadReq hits
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 2180 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 2180 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 2180 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 2180 # number of overall hits
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 435 # number of overall misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7380250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 7380250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21128996 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 21128996 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 28509246 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 28509246 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 28509246 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 28509246 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses)
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066284 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.066284 # miss rate for ReadReq accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.166348 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.166348 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.166348 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.166348 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70963.942308 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 70963.942308 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63833.824773 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 63833.824773 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 65538.496552 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 65538.496552 # average overall miss latency
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4139250 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4139250 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3677248 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3677248 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7816498 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7816498 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816498 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7816498 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035054 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035054 # mshr miss rate for ReadReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.039006 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.039006 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75259.090909 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75259.090909 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78239.319149 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78239.319149 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2009-10-27 17:24:40 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
