2011-03-18 01:20:22 +01:00
---------- Begin Simulation Statistics ----------
2016-08-12 15:12:59 +02:00
sim_seconds 2.827853 # Number of seconds simulated
sim_ticks 2827853096000 # Number of ticks simulated
final_tick 2827853096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-03-18 01:20:22 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-08-12 15:12:59 +02:00
host_inst_rate 94322 # Simulator instruction rate (inst/s)
host_op_rate 114411 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2357194570 # Simulator tick rate (ticks/s)
host_mem_usage 589152 # Number of bytes of host memory used
host_seconds 1199.67 # Real time elapsed on the host
sim_insts 113155640 # Number of instructions simulated
sim_ops 137255479 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1322240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9790440 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_read::total 11115048 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1322240 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1322240 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8407168 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_written::total 8424692 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22907 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 153496 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_reads::total 176440 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 131362 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_writes::total 135743 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 362 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 467577 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3462146 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_read::total 3930561 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 467577 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 467577 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2972986 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2979183 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2972986 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 362 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 467577 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3468343 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_total::total 6909744 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 176441 # Number of read requests accepted
system.physmem.writeReqs 135743 # Number of write requests accepted
system.physmem.readBursts 176441 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 135743 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11282432 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue
system.physmem.bytesWritten 8437824 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 11115112 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8424692 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::0 11743 # Per bank write bursts
system.physmem.perBankRdBursts::1 11227 # Per bank write bursts
system.physmem.perBankRdBursts::2 11041 # Per bank write bursts
system.physmem.perBankRdBursts::3 10652 # Per bank write bursts
system.physmem.perBankRdBursts::4 13485 # Per bank write bursts
system.physmem.perBankRdBursts::5 11002 # Per bank write bursts
system.physmem.perBankRdBursts::6 11432 # Per bank write bursts
system.physmem.perBankRdBursts::7 11844 # Per bank write bursts
system.physmem.perBankRdBursts::8 10383 # Per bank write bursts
system.physmem.perBankRdBursts::9 10947 # Per bank write bursts
system.physmem.perBankRdBursts::10 10471 # Per bank write bursts
system.physmem.perBankRdBursts::11 9569 # Per bank write bursts
system.physmem.perBankRdBursts::12 10361 # Per bank write bursts
system.physmem.perBankRdBursts::13 11110 # Per bank write bursts
system.physmem.perBankRdBursts::14 10361 # Per bank write bursts
system.physmem.perBankRdBursts::15 10660 # Per bank write bursts
system.physmem.perBankWrBursts::0 8764 # Per bank write bursts
system.physmem.perBankWrBursts::1 8604 # Per bank write bursts
system.physmem.perBankWrBursts::2 8676 # Per bank write bursts
system.physmem.perBankWrBursts::3 8310 # Per bank write bursts
system.physmem.perBankWrBursts::4 8074 # Per bank write bursts
system.physmem.perBankWrBursts::5 8230 # Per bank write bursts
system.physmem.perBankWrBursts::6 8228 # Per bank write bursts
system.physmem.perBankWrBursts::7 8800 # Per bank write bursts
system.physmem.perBankWrBursts::8 7938 # Per bank write bursts
system.physmem.perBankWrBursts::9 8472 # Per bank write bursts
system.physmem.perBankWrBursts::10 8080 # Per bank write bursts
system.physmem.perBankWrBursts::11 7388 # Per bank write bursts
system.physmem.perBankWrBursts::12 8035 # Per bank write bursts
system.physmem.perBankWrBursts::13 8487 # Per bank write bursts
system.physmem.perBankWrBursts::14 7854 # Per bank write bursts
system.physmem.perBankWrBursts::15 7901 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-08-12 15:12:59 +02:00
system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
system.physmem.totGap 2827852861000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::2 542 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.readPktSize::6 172889 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.writePktSize::6 131362 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 155219 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 17999 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2225 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 829 # What read queue length does an incoming req see
2016-04-09 18:13:40 +02:00
system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.wrQLenPdf::15 2095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2964 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6509 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6942 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6801 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7733 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8271 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9582 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9943 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8295 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 327 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 64990 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 303.434251 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 179.571710 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 325.070143 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 24166 37.18% 37.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 15993 24.61% 61.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6821 10.50% 72.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3792 5.83% 78.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2758 4.24% 82.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1633 2.51% 84.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1086 1.67% 86.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1085 1.67% 88.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7656 11.78% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64990 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6662 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 26.461423 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 559.657587 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6661 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6662 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6662 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.790003 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.288798 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.351415 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5875 88.19% 88.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 70 1.05% 89.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 75 1.13% 90.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 36 0.54% 90.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 259 3.89% 94.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 62 0.93% 95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 25 0.38% 96.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 19 0.29% 96.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 9 0.14% 96.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 7 0.11% 96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 3 0.05% 96.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 4 0.06% 96.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 160 2.40% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 6 0.09% 99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 8 0.12% 99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 2 0.03% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 10 0.15% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.02% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 8 0.12% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.02% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 2 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6662 # Writes before turning the bus around for reads
system.physmem.totQLat 2116192000 # Total ticks spent queuing
system.physmem.totMemAccLat 5421592000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 881440000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12004.17 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-08-12 15:12:59 +02:00
system.physmem.avgMemAccLat 30754.17 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.93 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2016-04-09 18:13:40 +02:00
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
2016-08-12 15:12:59 +02:00
system.physmem.avgWrQLen 23.03 # Average write queue length when enqueuing
system.physmem.readRowHits 145153 # Number of row buffer hits during reads
system.physmem.writeRowHits 97985 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.31 # Row buffer hit rate for writes
system.physmem.avgGap 9058288.90 # Average gap between requests
system.physmem.pageHitRate 78.90 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 256087440 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 139730250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 720922800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 438605280 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 81077227785 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1625589296250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1892923233405 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.386141 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2704185411500 # Time in different power states
system.physmem_0.memoryStateTime::REF 94428100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_0.memoryStateTime::ACT 29235954750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.actEnergy 235236960 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 128353500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 654115800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 415724400 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 80292349755 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1626277785750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1892704929765 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.308944 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2705344853000 # Time in different power states
system.physmem_1.memoryStateTime::REF 94428100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.memoryStateTime::ACT 28080129500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2016-08-12 15:12:59 +02:00
system.cpu.branchPred.lookups 46859222 # Number of BP lookups
system.cpu.branchPred.condPredicted 23995015 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1174256 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 29489294 # Number of BTB lookups
system.cpu.branchPred.BTBHits 13535968 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-08-12 15:12:59 +02:00
system.cpu.branchPred.BTBHitPct 45.901296 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 11745095 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 35189 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 7931554 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 7786304 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 145250 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 60170 # Number of mispredicted indirect branches.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 72426 # Table walker walks requested
system.cpu.dtb.walker.walksShort 72426 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29716 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23400 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 19310 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 53116 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 407.485503 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 2469.018740 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-8191 51917 97.74% 97.74% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-16383 937 1.76% 99.51% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-24575 190 0.36% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-32767 37 0.07% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-04-09 18:13:40 +02:00
system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.walkWaitTime::total 53116 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 17396 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 9637.387905 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 7803.906851 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 6813.601039 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383 15561 89.45% 89.45% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767 1740 10.00% 99.45% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-49151 86 0.49% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::49152-65535 2 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 17396 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 117727604724 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.629848 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.489627 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 117677681224 99.96% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 34838500 0.03% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 7318000 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 4585500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 935500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 533500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 1306000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 397000 0.00% 100.00% # Table walker pending requests distribution
2016-04-09 18:13:40 +02:00
system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.walksPending::total 117727604724 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6471 81.85% 81.85% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1435 18.15% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7906 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72426 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72426 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7906 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7906 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 80332 # Table walker requests started/completed, data/inst
2011-05-23 17:59:13 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2016-08-12 15:12:59 +02:00
system.cpu.dtb.read_hits 25423365 # DTB read hits
system.cpu.dtb.read_misses 62664 # DTB read misses
system.cpu.dtb.write_hits 19868926 # DTB write hits
system.cpu.dtb.write_misses 9762 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-08-12 15:12:59 +02:00
system.cpu.dtb.flush_entries 4289 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2236 # Number of TLB faults due to prefetch
2011-05-23 17:59:13 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu.dtb.perms_faults 1258 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 25486029 # DTB read accesses
system.cpu.dtb.write_accesses 19878688 # DTB write accesses
2011-03-18 01:20:22 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2016-08-12 15:12:59 +02:00
system.cpu.dtb.hits 45292291 # DTB hits
system.cpu.dtb.misses 72426 # DTB misses
system.cpu.dtb.accesses 45364717 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 12855 # Table walker walks requested
system.cpu.itb.walker.walksShort 12855 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3590 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2 7693 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 1572 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 11283 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 605.778605 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 2805.757421 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-8191 10907 96.67% 96.67% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::8192-16383 327 2.90% 99.57% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-24575 40 0.35% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::24576-32767 5 0.04% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 11283 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 4887 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 8961.019030 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 7007.167188 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 7172.888707 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191 3327 68.08% 68.08% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383 829 16.96% 85.04% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575 682 13.96% 99.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::24576-32767 38 0.78% 99.77% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-40959 1 0.02% 99.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::40960-49151 7 0.14% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::49152-57343 1 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 4887 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 23237381212 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.774797 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.417824 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 5234024500 22.52% 22.52% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 18002578212 77.47% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 696500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 23237381212 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12855 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 12855 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 16170 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 66060204 # ITB inst hits
system.cpu.itb.inst_misses 12855 # ITB inst misses
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-08-12 15:12:59 +02:00
system.cpu.itb.flush_entries 3013 # Number of entries that have been flushed from TLB
2011-05-23 17:59:13 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu.itb.perms_faults 2175 # Number of TLB faults due to permissions restrictions
2011-05-23 17:59:13 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2016-08-12 15:12:59 +02:00
system.cpu.itb.inst_accesses 66073059 # ITB inst accesses
system.cpu.itb.hits 66060204 # DTB hits
system.cpu.itb.misses 12855 # DTB misses
system.cpu.itb.accesses 66073059 # DTB accesses
system.cpu.numPwrStateTransitions 6076 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean 887319797.866359 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 17420812025.908409 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu.pwrStateClkGateDist::max_value 499973328096 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON 132175550082 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 264351157 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-08-12 15:12:59 +02:00
system.cpu.fetch.icacheStallCycles 105007140 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 184198118 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46859222 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33067367 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 149125653 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6062128 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 177509 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 8064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 342285 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 500656 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 149 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 66059105 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1061874 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 6140 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 258192520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.869926 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.232240 # Number of instructions fetched each cycle (Total)
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-08-12 15:12:59 +02:00
system.cpu.fetch.rateDist::0 159207105 61.66% 61.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29153243 11.29% 72.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14041371 5.44% 78.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55790801 21.61% 100.00% # Number of instructions fetched each cycle (Total)
2011-03-18 01:20:22 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-08-12 15:12:59 +02:00
system.cpu.fetch.rateDist::total 258192520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.177261 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.696793 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 78121728 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 109293057 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64347286 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3858820 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2571629 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3404933 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 467397 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 157054266 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3508469 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2571629 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83876272 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 10707182 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 75777880 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62454434 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 22805123 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146493829 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 914752 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 447933 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 65579 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 19295 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 20059867 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150297562 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 677265731 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 164029738 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 11047 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 141819290 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 8478266 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2841903 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2646616 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13881588 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26350743 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 21216202 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1694356 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2155521 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143287156 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2116266 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143106706 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 261772 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8147939 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14286308 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 122067 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 258192520 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.554264 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.878016 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-08-12 15:12:59 +02:00
system.cpu.iq.issued_per_cycle::0 169987358 65.84% 65.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45210540 17.51% 83.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31907168 12.36% 95.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10268019 3.98% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 819402 0.32% 100.00% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-08-12 15:12:59 +02:00
system.cpu.iq.issued_per_cycle::total 258192520 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-08-12 15:12:59 +02:00
system.cpu.iq.fu_full::IntAlu 7338606 32.76% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5623411 25.10% 57.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9440852 42.14% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
2016-08-12 15:12:59 +02:00
system.cpu.iq.FU_type_0::IntAlu 95896760 67.01% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 115009 0.08% 67.09% # Type of FU issued
2016-04-09 18:13:40 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
2016-08-12 15:12:59 +02:00
system.cpu.iq.FU_type_0::SimdFloatMisc 8592 0.01% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26141404 18.27% 85.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 20942604 14.63% 100.00% # Type of FU issued
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-08-12 15:12:59 +02:00
system.cpu.iq.FU_type_0::total 143106706 # Type of FU issued
system.cpu.iq.rate 0.541351 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22402901 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156547 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 567034934 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 153556562 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 140052264 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35671 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13288 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11499 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 165483986 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23284 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 324130 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-08-12 15:12:59 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1434023 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 698 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18538 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 619510 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-08-12 15:12:59 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 88631 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6598 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-08-12 15:12:59 +02:00
system.cpu.iew.iewSquashCycles 2571629 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 994929 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 316385 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 145584227 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-08-12 15:12:59 +02:00
system.cpu.iew.iewDispLoadInsts 26350743 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 21216202 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1093451 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17658 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 280514 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18538 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 277676 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 470698 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 748374 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 142207045 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25746206 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 827350 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-08-12 15:12:59 +02:00
system.cpu.iew.exec_nop 180805 # number of nop insts executed
system.cpu.iew.exec_refs 46576895 # number of memory reference insts executed
system.cpu.iew.exec_branches 26509940 # Number of branches executed
system.cpu.iew.exec_stores 20830689 # Number of stores executed
system.cpu.iew.exec_rate 0.537948 # Inst execution rate
system.cpu.iew.wb_sent 141837731 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 140063763 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63261975 # num instructions producing a value
system.cpu.iew.wb_consumers 95760288 # num instructions consuming a value
system.cpu.iew.wb_rate 0.529840 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660628 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7362260 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1994199 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 714821 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 255299551 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.538232 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.139550 # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-08-12 15:12:59 +02:00
system.cpu.commit.committed_per_cycle::0 181839086 71.23% 71.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43295063 16.96% 88.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15470047 6.06% 94.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4367483 1.71% 95.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6400805 2.51% 98.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1643674 0.64% 99.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 799411 0.31% 99.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 417134 0.16% 99.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1066848 0.42% 100.00% # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-08-12 15:12:59 +02:00
system.cpu.commit.committed_per_cycle::total 255299551 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113310545 # Number of instructions committed
system.cpu.commit.committedOps 137410384 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2016-08-12 15:12:59 +02:00
system.cpu.commit.refs 45513412 # Number of memory references committed
system.cpu.commit.loads 24916720 # Number of loads committed
system.cpu.commit.membars 814165 # Number of memory barriers committed
system.cpu.commit.branches 26044798 # Number of branches committed
system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions.
system.cpu.commit.int_insts 120233477 # Number of committed integer instructions.
system.cpu.commit.function_calls 4891928 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu.commit.op_class_0::IntAlu 91774855 66.79% 66.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 113526 0.08% 66.87% # Class of committed instruction
2014-10-30 05:18:29 +01:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu.commit.op_class_0::SimdFloatMisc 8591 0.01% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 24916720 18.13% 85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20596692 14.99% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu.commit.op_class_0::total 137410384 # Class of committed instruction
system.cpu.commit.bw_lim_events 1066848 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 376774257 # The number of ROB reads
system.cpu.rob.rob_writes 292425270 # The number of ROB writes
system.cpu.timesIdled 893722 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 6158637 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5391355036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113155640 # Number of Instructions Simulated
system.cpu.committedOps 137255479 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.336173 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.336173 # CPI: Total CPI of All Threads
system.cpu.ipc 0.428050 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.428050 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 155596461 # number of integer regfile reads
system.cpu.int_regfile_writes 88540193 # number of integer regfile writes
system.cpu.fp_regfile_reads 9674 # number of floating regfile reads
2014-10-30 05:18:29 +01:00
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
2016-08-12 15:12:59 +02:00
system.cpu.cc_regfile_reads 502394909 # number of cc regfile reads
system.cpu.cc_regfile_writes 53149715 # number of cc regfile writes
system.cpu.misc_regfile_reads 449419252 # number of misc regfile reads
system.cpu.misc_regfile_writes 1520020 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 839084 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.954165 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40069527 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 839596 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.724771 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 270911500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.954165 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu.dcache.tags.tag_accesses 179200286 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179200286 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 23273566 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23273566 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15547100 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15547100 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 345314 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345314 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441102 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441102 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 459566 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 459566 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38820666 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38820666 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39165980 # number of overall hits
system.cpu.dcache.overall_hits::total 39165980 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 709196 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 709196 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3610101 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3610101 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 177382 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 177382 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 26835 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 26835 # number of LoadLockedReq misses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.demand_misses::cpu.data 4319297 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4319297 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4496679 # number of overall misses
system.cpu.dcache.overall_misses::total 4496679 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10317292500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10317292500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 150336233192 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 150336233192 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 369753500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 369753500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 213000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 213000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 160653525692 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 160653525692 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 160653525692 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 160653525692 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23982762 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23982762 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19157201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19157201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 522696 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 522696 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467937 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 467937 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 459571 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 459571 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43139963 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43139963 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43662659 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43662659 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029571 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029571 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188446 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.188446 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339360 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.339360 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057347 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057347 # miss rate for LoadLockedReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.100123 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.100123 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102987 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102987 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14547.871815 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14547.871815 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41643.220838 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41643.220838 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13778.777716 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13778.777716 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42600 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42600 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37194.368827 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37194.368827 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35727.150124 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35727.150124 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 590933 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.dcache.blocked::no_mshrs 7520 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.581516 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.dcache.writebacks::writebacks 696178 # number of writebacks
system.cpu.dcache.writebacks::total 696178 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295013 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 295013 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309632 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3309632 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18459 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18459 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3604645 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3604645 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3604645 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3604645 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414183 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 414183 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300469 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 300469 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119358 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 119358 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8376 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8376 # number of LoadLockedReq MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 714652 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 714652 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 834010 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 834010 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5890415000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5890415000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13426039479 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13426039479 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1622684000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1622684000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 130358500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 130358500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 208000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 208000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19316454479 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 19316454479 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20939138479 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 20939138479 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279502000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279502000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6279502000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6279502000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017270 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017270 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015684 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015684 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228351 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228351 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017900 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017900 # mshr miss rate for LoadLockedReq accesses
2016-04-09 18:13:40 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016566 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016566 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019101 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019101 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13595.100454 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13595.100454 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15563.335721 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15563.335721 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41600 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41600 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27029.175709 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27029.175709 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25106.579632 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25106.579632 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201738.105182 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201738.105182 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.141098 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.141098 # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1887810 # number of replacements
system.cpu.icache.tags.tagsinuse 511.341026 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64075895 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1888322 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 33.932716 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 13715039500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.341026 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.998713 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.998713 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.tag_accesses 67944454 # Number of tag accesses
system.cpu.icache.tags.data_accesses 67944454 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 64075895 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64075895 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64075895 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 64075895 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 64075895 # number of overall hits
system.cpu.icache.overall_hits::total 64075895 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1980206 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1980206 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1980206 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1980206 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1980206 # number of overall misses
system.cpu.icache.overall_misses::total 1980206 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 26984355494 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 26984355494 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 26984355494 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 26984355494 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 26984355494 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 26984355494 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 66056101 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 66056101 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 66056101 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 66056101 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 66056101 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 66056101 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029978 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.029978 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.029978 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.029978 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.029978 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.029978 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13627.044607 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13627.044607 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13627.044607 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13627.044607 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 2643 # number of cycles access was blocked
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked
2014-09-03 13:42:59 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 21.144000 # average number of cycles each access was blocked
2014-09-03 13:42:59 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.icache.writebacks::writebacks 1887810 # number of writebacks
system.cpu.icache.writebacks::total 1887810 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91852 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 91852 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 91852 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 91852 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 91852 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 91852 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888354 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1888354 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1888354 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1888354 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1888354 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1888354 # number of overall MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24226536497 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 24226536497 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24226536497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 24226536497 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24226536497 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 24226536497 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 229048500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 229048500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 229048500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 229048500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028587 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.028587 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.028587 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12829.446437 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12829.446437 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12829.446437 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12829.446437 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12829.446437 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12829.446437 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76273.226773 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76273.226773 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76273.226773 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76273.226773 # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 103423 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65159.012032 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5300281 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 168782 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 31.403118 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 93779484000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.961762 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.729813 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10177.791609 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 54967.528848 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000152 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155301 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.838738 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.994248 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65345 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5571 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59599 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997086 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 43992446 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 43992446 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54341 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10212 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 64553 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 696178 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 696178 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1850381 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1850381 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2757 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 2757 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 158824 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 158824 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868353 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1868353 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527348 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 527348 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 54341 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 10212 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1868353 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 686172 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2619078 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 54341 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 10212 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1868353 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 686172 # number of overall hits
system.cpu.l2cache.overall_hits::total 2619078 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 22 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 139010 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 139010 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19937 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 19937 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14436 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 14436 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 19937 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 153446 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 173405 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 16 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 19937 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 153446 # number of overall misses
system.cpu.l2cache.overall_misses::total 173405 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1497500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 502000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1999500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 167000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 167000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11275740500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 11275740500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1659086000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1659086000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1242944500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1242944500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1497500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 502000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1659086000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12518685000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 14179770500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1497500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 502000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1659086000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12518685000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 14179770500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54357 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10218 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 64575 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 696178 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 696178 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1850381 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1850381 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses)
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 297834 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 297834 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1888290 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1888290 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 541784 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 541784 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54357 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 10218 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1888290 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 839618 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2792483 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54357 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 10218 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1888290 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 839618 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2792483 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000294 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000587 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000341 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003974 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003974 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.466737 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.466737 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010558 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010558 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026645 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026645 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000294 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000587 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010558 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.182757 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.062097 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000294 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000587 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010558 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.182757 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.062097 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93593.750000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83666.666667 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 90886.363636 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29136.363636 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29136.363636 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83500 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81114.599669 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81114.599669 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83216.431760 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83216.431760 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86100.339429 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86100.339429 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93593.750000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83666.666667 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83216.431760 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81583.651578 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81772.558461 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93593.750000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83666.666667 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83216.431760 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81583.651578 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81772.558461 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.writebacks::writebacks 95172 # number of writebacks
system.cpu.l2cache.writebacks::total 95172 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.demand_mshr_hits::total 135 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.overall_mshr_hits::total 135 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 16 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 22 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139010 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 139010 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19914 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19914 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14324 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14324 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 16 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 19914 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 153334 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 173270 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 16 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19914 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 153334 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 173270 # number of overall MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34130 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61714 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1337500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 442000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1779500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 210500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 210500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 147000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 147000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9885640500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9885640500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1458480000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1458480000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1091561500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1091561500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1337500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1458480000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10977202000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 12437461500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1337500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1458480000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10977202000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 12437461500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191510500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5890404500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6081915000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191510500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5890404500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6081915000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000341 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003974 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003974 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.466737 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.466737 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010546 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026439 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026439 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.062049 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.062049 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80886.363636 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19136.363636 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19136.363636 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71114.599669 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71114.599669 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73238.927388 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73238.927388 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76205.075398 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76205.075398 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189237.783917 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178198.505713 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100328.805505 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98550.004861 # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests 5488560 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2760615 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44763 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 238 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 238 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 129622 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2559974 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 791350 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1887810 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 151157 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 297834 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 297834 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888354 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 542004 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 4368 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670459 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2641503 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29194 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130873 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8472029 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241718384 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98487773 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40872 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 217428 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 340464457 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 139207 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 6232532 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 2995964 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.025358 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.157210 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_fanout::0 2919992 97.46% 97.46% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 75972 2.54% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_fanout::total 2995964 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5405204997 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 383377 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 2836467127 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 1305988986 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 18982487 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 76565899 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30182 # Transaction distribution
system.iobus.trans_dist::ReadResp 30182 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 43094500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer1.occupancy 101000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer8.occupancy 649500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer23.occupancy 6172500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer24.occupancy 33854000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer25.occupancy 187760330 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36423 # number of replacements
system.iocache.tags.tagsinuse 1.000676 # Cycle average of tags in use
2016-04-09 18:13:40 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks.
2016-04-09 18:13:40 +02:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.iocache.tags.warmup_cycle 252706881000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.000676 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.iocache.tags.tag_accesses 328113 # Number of tag accesses
system.iocache.tags.data_accesses 328113 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses
system.iocache.ReadReq_misses::total 233 # number of ReadReq misses
2016-04-09 18:13:40 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-08-12 15:12:59 +02:00
system.iocache.demand_misses::realview.ide 36457 # number of demand (read+write) misses
system.iocache.demand_misses::total 36457 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36457 # number of overall misses
system.iocache.overall_misses::total 36457 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 28964877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28964877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4277512453 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4277512453 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4306477330 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4306477330 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4306477330 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4306477330 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.iocache.demand_accesses::realview.ide 36457 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36457 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36457 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36457 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2016-04-09 18:13:40 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124312.776824 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118124.841046 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118124.841046 # average overall miss latency
2016-04-21 10:48:24 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-04-21 10:48:24 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-09 18:13:40 +02:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses
2016-04-09 18:13:40 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.demand_mshr_misses::realview.ide 36457 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36457 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36457 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36457 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 17314877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 17314877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464212681 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2464212681 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2481527558 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2481527558 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2481527558 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2481527558 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2016-04-09 18:13:40 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency
system.membus.snoop_filter.tot_requests 349590 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 144366 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 34130 # Transaction distribution
system.membus.trans_dist::ReadResp 68622 # Transaction distribution
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
system.membus.trans_dist::WritebackDirty 131362 # Transaction distribution
system.membus.trans_dist::CleanEvict 8484 # Transaction distribution
system.membus.trans_dist::UpgradeReq 130 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::ReadExReq 138891 # Transaction distribution
system.membus.trans_dist::ReadExResp 138891 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 34493 # Transaction distribution
2016-04-09 18:13:40 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465445 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 573007 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72895 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72895 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 645902 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17222620 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17385997 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_size::total 19703117 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 497 # Total snoops (count)
system.membus.snoopTraffic 31680 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 271454 # Request fanout histogram
system.membus.snoop_fanout::mean 0.017933 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.132708 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::0 266586 98.21% 98.21% # Request fanout histogram
system.membus.snoop_fanout::1 4868 1.79% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::total 271454 # Request fanout histogram
system.membus.reqLayer0.occupancy 84464500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer2.occupancy 1723499 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer5.occupancy 908168519 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer2.occupancy 1012308500 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer3.occupancy 1273123 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-08-12 15:12:59 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states
2011-05-23 17:59:13 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2016-08-12 15:12:59 +02:00
system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed
2011-03-18 01:20:22 +01:00
---------- End Simulation Statistics ----------
