2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
2016-08-12 15:12:59 +02:00
sim_seconds 2.870001 # Number of seconds simulated
sim_ticks 2870000710000 # Number of ticks simulated
final_tick 2870000710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-08-12 15:12:59 +02:00
host_inst_rate 371570 # Simulator instruction rate (inst/s)
host_op_rate 449436 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 8101953096 # Simulator tick rate (ticks/s)
host_mem_usage 621024 # Number of bytes of host memory used
host_seconds 354.24 # Real time elapsed on the host
sim_insts 131623434 # Number of instructions simulated
sim_ops 159206188 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2016-05-31 12:07:18 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_read::cpu0.inst 1182180 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1312420 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8596224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 150484 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 578772 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 396096 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_read::total 12217776 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1182180 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 150484 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1332664 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8789056 # Number of bytes written to this memory
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_written::total 8806620 # Number of bytes written to this memory
2016-05-31 12:07:18 +02:00
system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
2014-12-23 15:31:20 +01:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_reads::cpu0.inst 26925 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 21026 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 134316 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2506 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 6189 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_reads::total 200051 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 137329 # Number of write requests responded to by this memory
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_writes::total 141720 # Number of write requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
2014-12-23 15:31:20 +01:00
system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_read::cpu0.inst 411909 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 457289 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2995199 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 52433 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 201663 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 138013 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4257064 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 411909 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 52433 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 464343 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3062388 # Write bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_write::total 3068508 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3062388 # Total bandwidth to/from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
2014-12-23 15:31:20 +01:00
system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_total::cpu0.inst 411909 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 463395 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2995199 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 52433 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 201677 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 138013 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7325572 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 200051 # Number of read requests accepted
system.physmem.writeReqs 141720 # Number of write requests accepted
system.physmem.readBursts 200051 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 141720 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12793920 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
system.physmem.bytesWritten 8819520 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12217776 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8806620 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
2016-05-31 12:07:18 +02:00
system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::0 11709 # Per bank write bursts
system.physmem.perBankRdBursts::1 12160 # Per bank write bursts
system.physmem.perBankRdBursts::2 12038 # Per bank write bursts
system.physmem.perBankRdBursts::3 12178 # Per bank write bursts
system.physmem.perBankRdBursts::4 20671 # Per bank write bursts
system.physmem.perBankRdBursts::5 12806 # Per bank write bursts
system.physmem.perBankRdBursts::6 12086 # Per bank write bursts
system.physmem.perBankRdBursts::7 12477 # Per bank write bursts
system.physmem.perBankRdBursts::8 12638 # Per bank write bursts
system.physmem.perBankRdBursts::9 12504 # Per bank write bursts
system.physmem.perBankRdBursts::10 11795 # Per bank write bursts
system.physmem.perBankRdBursts::11 11324 # Per bank write bursts
system.physmem.perBankRdBursts::12 11594 # Per bank write bursts
system.physmem.perBankRdBursts::13 11843 # Per bank write bursts
system.physmem.perBankRdBursts::14 11003 # Per bank write bursts
system.physmem.perBankRdBursts::15 11079 # Per bank write bursts
system.physmem.perBankWrBursts::0 8559 # Per bank write bursts
system.physmem.perBankWrBursts::1 9022 # Per bank write bursts
system.physmem.perBankWrBursts::2 9017 # Per bank write bursts
system.physmem.perBankWrBursts::3 8844 # Per bank write bursts
system.physmem.perBankWrBursts::4 8437 # Per bank write bursts
system.physmem.perBankWrBursts::5 9230 # Per bank write bursts
system.physmem.perBankWrBursts::6 8825 # Per bank write bursts
system.physmem.perBankWrBursts::7 8866 # Per bank write bursts
system.physmem.perBankWrBursts::8 9056 # Per bank write bursts
system.physmem.perBankWrBursts::9 8974 # Per bank write bursts
system.physmem.perBankWrBursts::10 8482 # Per bank write bursts
system.physmem.perBankWrBursts::11 8329 # Per bank write bursts
system.physmem.perBankWrBursts::12 8472 # Per bank write bursts
system.physmem.perBankWrBursts::13 8225 # Per bank write bursts
system.physmem.perBankWrBursts::14 7833 # Per bank write bursts
system.physmem.perBankWrBursts::15 7634 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-08-12 15:12:59 +02:00
system.physmem.numWrRetry 37 # Number of times write queue was full causing retry
system.physmem.totGap 2870000192000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.readPktSize::2 9732 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 28 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.readPktSize::6 190291 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.writePktSize::6 137329 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 139673 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 16007 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 10455 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8865 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7050 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 5558 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 4708 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 3913 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3442 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see
2016-07-21 18:19:18 +02:00
system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.rdQLenPdf::11 43 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
2016-07-21 18:19:18 +02:00
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
2016-05-31 12:07:18 +02:00
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
2014-12-02 12:08:25 +01:00
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3656 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4613 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5803 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6737 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6707 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8644 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10413 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8708 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 10166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7446 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 368 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 301 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 123 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see
2016-07-21 18:19:18 +02:00
system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.wrQLenPdf::44 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 78 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 85925 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 251.537690 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 143.363316 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 306.826134 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 42893 49.92% 49.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18336 21.34% 71.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6281 7.31% 78.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3896 4.53% 83.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2533 2.95% 86.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1590 1.85% 87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1050 1.22% 89.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 985 1.15% 90.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8361 9.73% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 85925 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6834 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 29.251244 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 562.918265 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6833 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6834 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6834 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.164618 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.651361 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.320527 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5790 84.72% 84.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 323 4.73% 89.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 59 0.86% 90.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 46 0.67% 90.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 267 3.91% 94.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 35 0.51% 95.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 21 0.31% 95.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 28 0.41% 96.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 23 0.34% 96.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 7 0.10% 96.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 4 0.06% 96.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 12 0.18% 96.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 155 2.27% 99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 3 0.04% 99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 5 0.07% 99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 6 0.09% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 12 0.18% 99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.03% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.03% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.01% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.01% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.01% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 2 0.03% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6834 # Writes before turning the bus around for reads
system.physmem.totQLat 4674239132 # Total ticks spent queuing
system.physmem.totMemAccLat 8422457882 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 999525000 # Total ticks spent in databus transfers
system.physmem.avgQLat 23382.30 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-08-12 15:12:59 +02:00
system.physmem.avgMemAccLat 42132.30 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.07 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2014-12-23 15:31:20 +01:00
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2016-08-12 15:12:59 +02:00
system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing
system.physmem.readRowHits 166683 # Number of row buffer hits during reads
system.physmem.writeRowHits 85101 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 61.75 # Row buffer hit rate for writes
system.physmem.avgGap 8397436.27 # Average gap between requests
system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 335240640 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 182919000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 827767200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 458784000 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 84698340030 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1647701064750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1921658314500 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.568191 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2740964082488 # Time in different power states
system.physmem_0.memoryStateTime::REF 95835480000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_0.memoryStateTime::ACT 33201034512 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.actEnergy 314352360 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 171521625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 731484000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 434192400 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 83981561895 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1648329817500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1921417128660 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.484154 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2742009812705 # Time in different power states
system.physmem_1.memoryStateTime::REF 95835480000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.memoryStateTime::ACT 32151144795 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2014-11-03 17:14:42 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 7878 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 7878 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1506 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6372 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 7878 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 7878 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 7878 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 6484 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12295.265268 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11397.219739 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 5676.180841 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 5980 92.23% 92.23% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 464 7.16% 99.38% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkCompletionTime::total 6484 # Table walker service (enqueue to completion) latency
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkPageSizes::4K 5017 77.38% 77.38% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1467 22.62% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6484 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7878 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7878 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6484 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6484 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 14362 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.read_hits 25174501 # DTB read hits
system.cpu0.dtb.read_misses 6776 # DTB read misses
system.cpu0.dtb.write_hits 18763964 # DTB write hits
system.cpu0.dtb.write_misses 1102 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.flush_entries 3391 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.prefetch_faults 1765 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.read_accesses 25181277 # DTB read accesses
system.cpu0.dtb.write_accesses 18765066 # DTB write accesses
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.hits 43938465 # DTB hits
system.cpu0.dtb.misses 7878 # DTB misses
system.cpu0.dtb.accesses 43946343 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walks 3349 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.walkCompletionTime::mean 12613.587655 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11778.875659 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 5637.639193 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 386 16.55% 16.55% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 1666 71.41% 87.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 225 9.64% 97.60% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 98.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.11% 99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.itb.inst_hits 119077538 # ITB inst hits
2016-05-31 12:07:18 +02:00
system.cpu0.itb.inst_misses 3349 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-06-21 17:42:04 +02:00
system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-08-12 15:12:59 +02:00
system.cpu0.itb.inst_accesses 119080887 # ITB inst accesses
system.cpu0.itb.hits 119077538 # DTB hits
2016-05-31 12:07:18 +02:00
system.cpu0.itb.misses 3349 # DTB misses
2016-08-12 15:12:59 +02:00
system.cpu0.itb.accesses 119080887 # DTB accesses
system.cpu0.numPwrStateTransitions 3762 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 1881 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 1452265205.015417 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 23608911235.366570 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 1082 57.52% 57.52% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 794 42.21% 99.73% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu0.pwrStateClkGateDist::max_value 499963656512 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 1881 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 138289859366 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731710850634 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 5740001420 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-08-12 15:12:59 +02:00
system.cpu0.kern.inst.quiesce 1881 # number of quiesce instructions executed
system.cpu0.committedInsts 115412619 # Number of instructions committed
system.cpu0.committedOps 139453859 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 123427491 # Number of integer alu accesses
2016-07-21 18:19:18 +02:00
system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses
2016-08-12 15:12:59 +02:00
system.cpu0.num_func_calls 12678366 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 15706258 # number of instructions that are conditional controls
system.cpu0.num_int_insts 123427491 # number of integer instructions
2016-07-21 18:19:18 +02:00
system.cpu0.num_fp_insts 9820 # number of float instructions
2016-08-12 15:12:59 +02:00
system.cpu0.num_int_register_reads 227200136 # number of times the integer registers were read
system.cpu0.num_int_register_writes 85767213 # number of times the integer registers were written
2016-07-21 18:19:18 +02:00
system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read
2016-05-31 12:07:18 +02:00
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
2016-08-12 15:12:59 +02:00
system.cpu0.num_cc_register_reads 505219370 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 52317118 # number of times the CC registers were written
system.cpu0.num_mem_refs 45075192 # number of memory refs
system.cpu0.num_load_insts 25426401 # Number of load instructions
system.cpu0.num_store_insts 19648791 # Number of store instructions
system.cpu0.num_idle_cycles 5463421701.266096 # Number of idle cycles
system.cpu0.num_busy_cycles 276579718.733904 # Number of busy cycles
system.cpu0.not_idle_fraction 0.048185 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.951815 # Percentage of idle cycles
system.cpu0.Branches 29123439 # Number of branches fetched
2016-05-31 12:07:18 +02:00
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
2016-08-12 15:12:59 +02:00
system.cpu0.op_class::IntAlu 98023875 68.44% 68.44% # Class of executed instruction
system.cpu0.op_class::IntMult 109907 0.08% 68.52% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction
system.cpu0.op_class::MemRead 25426401 17.75% 86.28% # Class of executed instruction
system.cpu0.op_class::MemWrite 19648791 13.72% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-08-12 15:12:59 +02:00
system.cpu0.op_class::total 143219456 # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 693439 # number of replacements
system.cpu0.dcache.tags.tagsinuse 491.449824 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 43066582 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 693951 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 62.059975 # Average number of references to valid blocks.
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.449824 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959863 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.959863 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.tags.tag_accesses 88514427 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88514427 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 23911425 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 23911425 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 18032865 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18032865 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319065 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 319065 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365782 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 365782 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362736 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 362736 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 41944290 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 41944290 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 42263355 # number of overall hits
system.cpu0.dcache.overall_hits::total 42263355 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 397667 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 397667 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 324388 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 324388 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127754 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 127754 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21573 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 21573 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19602 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 19602 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 722055 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 722055 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 849809 # number of overall misses
system.cpu0.dcache.overall_misses::total 849809 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5269907000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5269907000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5597938000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 5597938000 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327322000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 327322000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 460475500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 460475500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1158000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1158000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 10867845000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 10867845000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 10867845000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 10867845000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 24309092 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 24309092 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 18357253 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 18357253 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446819 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 446819 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387355 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 387355 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382338 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 382338 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 42666345 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 42666345 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 43113164 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 43113164 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017671 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.017671 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285919 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285919 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055693 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055693 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051269 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051269 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016923 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.016923 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13252.060141 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13252.060141 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17256.920725 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17256.920725 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15172.762249 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15172.762249 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23491.250893 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23491.250893 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15051.270333 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15051.270333 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12788.573668 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12788.573668 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.writebacks::writebacks 693439 # number of writebacks
system.cpu0.dcache.writebacks::total 693439 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25271 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 25271 # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15260 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15260 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 25271 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 25271 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 25271 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 25271 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372396 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 372396 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324388 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 324388 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100689 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 100689 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6313 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6313 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19602 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 19602 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 696784 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 696784 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 797473 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 797473 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31786 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60249 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4503432000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4503432000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5273550000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5273550000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615902000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615902000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94571500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94571500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440907500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440907500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1124000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1124000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9776982000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9776982000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11392884000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 11392884000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628627500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628627500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628627500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628627500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015319 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015319 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017671 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017671 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225346 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225346 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016298 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016298 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051269 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051269 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016331 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.016331 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12093.126672 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12093.126672 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16256.920725 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16256.920725 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16048.446206 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16048.446206 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14980.437193 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14980.437193 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22492.985410 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22492.985410 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14031.582241 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14031.582241 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14286.231634 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14286.231634 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208539.215378 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208539.215378 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110020.539760 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110020.539760 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1105141 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.449200 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 117971876 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1105653 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 106.698825 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 14058125000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449200 # Average occupied blocks per requestor
2016-05-31 12:07:18 +02:00
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.tag_accesses 239260738 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 239260738 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 117971876 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 117971876 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 117971876 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 117971876 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 117971876 # number of overall hits
system.cpu0.icache.overall_hits::total 117971876 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1105662 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1105662 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1105662 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1105662 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1105662 # number of overall misses
system.cpu0.icache.overall_misses::total 1105662 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11445416000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11445416000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 11445416000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11445416000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 11445416000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11445416000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 119077538 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 119077538 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 119077538 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 119077538 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 119077538 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 119077538 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009285 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.009285 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009285 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.009285 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009285 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.009285 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.640917 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.640917 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10351.640917 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10351.640917 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.icache.writebacks::writebacks 1105141 # number of writebacks
system.cpu0.icache.writebacks::total 1105141 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1105662 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1105662 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1105662 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1105662 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1105662 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1105662 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10892585000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10892585000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10892585000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10892585000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10892585000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10892585000 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009285 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009285 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009285 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9851.640917 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9851.640917 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9851.640917 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836809 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1836835 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.prefetcher.pfSpanPage 235109 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 260353 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15640.705301 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 1686155 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 275976 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.109789 # Average number of references to valid blocks.
2015-07-30 09:42:27 +02:00
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.tags.occ_blocks::writebacks 14471.492082 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.272651 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.132938 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1167.807630 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.883270 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000078 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071277 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.954633 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15308 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 29 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 131 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 144 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 815 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6065 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6346 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1905 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018982 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934326 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 61385527 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 61385527 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9987 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4390 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 14377 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 478787 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 478787 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 1291925 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 1291925 # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226376 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 226376 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1043295 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1043295 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 377938 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 377938 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9987 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4390 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1043295 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 604314 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1661986 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9987 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4390 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1043295 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 604314 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1661986 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 261 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 141 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 402 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55107 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 55107 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19598 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 19598 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42905 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 42905 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62367 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 62367 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101460 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 101460 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 261 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 141 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 62367 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 144365 # number of demand (read+write) misses
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system.cpu0.l2cache.WritebackDirty_accesses::total 478787 # number of WritebackDirty accesses(hits+misses)
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2016-05-31 12:07:18 +02:00
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system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2015-11-06 09:26:50 +01:00
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system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-08-12 15:12:59 +02:00
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system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
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system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 566.497904 # average UpgradeReq miss latency
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system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 484.768854 # average SCUpgradeReq miss latency
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system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 267874.500000 # average SCUpgradeFailReq miss latency
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system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 47306.780830 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29874.315001 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29874.315001 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24143.678161 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23514.184397 # average overall miss latency
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system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24143.678161 # average overall miss latency
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system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35124.974890 # average overall miss latency
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2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
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system.cpu0.l2cache.writebacks::total 227687 # number of writebacks
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2015-05-05 09:22:39 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable
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2015-05-05 09:22:39 +02:00
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2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses
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system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4089460000 # number of overall MSHR miss cycles
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2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
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2016-05-31 12:07:18 +02:00
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2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373927500 # number of overall MSHR uncacheable cycles
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2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
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2016-05-31 12:07:18 +02:00
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2015-11-06 09:26:50 +01:00
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
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2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
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system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056407 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211578 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211578 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110166 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.249260 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17922.885572 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53346.929538 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17108.334694 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17108.334694 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15005.995510 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15005.995510 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 216874.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 216874.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40084.971472 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40084.971472 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41306.780830 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23832.746722 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23832.746722 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32406.137544 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44091.685230 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200526.253697 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174418.716918 # average ReadReq mshr uncacheable latency
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105793.083703 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102751.209020 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 3740310 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1886004 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27868 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 209163 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 207471 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1692 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 61471 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1694410 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 706729 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 1319793 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 79890 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 307615 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 87684 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41751 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 111919 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 288494 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 284839 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1105662 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 565382 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 3277 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3334509 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561453 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10930 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24498 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 5931390 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141527480 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96553100 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18124 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 238139696 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 885320 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 18675332 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 2797680 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.089870 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.288103 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.snoop_fanout::0 2547944 91.07% 91.07% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 248044 8.87% 99.94% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 1692 0.06% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.snoop_fanout::total 2797680 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 3721587498 # Layer occupancy (ticks)
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.snoopLayer0.occupancy 113922479 # Layer occupancy (ticks)
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer0.occupancy 1667515000 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer1.occupancy 1206437474 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer3.occupancy 14255489 # Layer occupancy (ticks)
2014-09-20 23:18:53 +02:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 3379 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 3379 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 3379 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 3379 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 3379 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 2609 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12498.275201 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11540.409783 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 5547.212388 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 616 23.61% 23.61% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1660 63.63% 87.24% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 255 9.77% 97.01% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 67 2.57% 99.58% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 5 0.19% 99.77% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 2609 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -2073200828 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -2073200828 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -2073200828 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.13% 74.13% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 675 25.87% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2609 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3379 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3379 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2609 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2609 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 5988 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.read_hits 3943912 # DTB read hits
system.cpu1.dtb.read_misses 2863 # DTB read misses
system.cpu1.dtb.write_hits 3421052 # DTB write hits
system.cpu1.dtb.write_misses 516 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.flush_entries 1981 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.prefetch_faults 312 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.read_accesses 3946775 # DTB read accesses
system.cpu1.dtb.write_accesses 3421568 # DTB write accesses
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.hits 7364964 # DTB hits
system.cpu1.dtb.misses 3379 # DTB misses
system.cpu1.dtb.accesses 7368343 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walks 1746 # Table walker walks requested
system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.walkCompletionTime::mean 13079.042457 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12148.751119 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5740.258970 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191 165 14.91% 14.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287 593 53.57% 68.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 84.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575 63 5.69% 95.21% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.56% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.10% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.37% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% # Table walker service (enqueue to completion) latency
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.walksPending::samples -2073744828 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -2073744828 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -2073744828 # Table walker pending requests distribution
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.itb.inst_hits 16566340 # ITB inst hits
2016-05-31 12:07:18 +02:00
system.cpu1.itb.inst_misses 1746 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-06-21 17:42:04 +02:00
system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-08-12 15:12:59 +02:00
system.cpu1.itb.inst_accesses 16568086 # ITB inst accesses
system.cpu1.itb.hits 16566340 # DTB hits
2016-05-31 12:07:18 +02:00
system.cpu1.itb.misses 1746 # DTB misses
2016-08-12 15:12:59 +02:00
system.cpu1.itb.accesses 16568086 # DTB accesses
system.cpu1.numPwrStateTransitions 5497 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 2749 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 1034540641.602037 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 25769735768.471432 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 1960 71.30% 71.30% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 783 28.48% 99.78% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu1.pwrStateClkGateDist::max_value 929980464320 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 2749 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 26048486236 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843952223764 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 5739069639 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-08-12 15:12:59 +02:00
system.cpu1.kern.inst.quiesce 2749 # number of quiesce instructions executed
system.cpu1.committedInsts 16210815 # Number of instructions committed
system.cpu1.committedOps 19752329 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 17813732 # Number of integer alu accesses
2016-05-31 12:07:18 +02:00
system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses
2016-08-12 15:12:59 +02:00
system.cpu1.num_func_calls 1029438 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1815045 # number of instructions that are conditional controls
system.cpu1.num_int_insts 17813732 # number of integer instructions
2016-05-31 12:07:18 +02:00
system.cpu1.num_fp_insts 1857 # number of float instructions
2016-08-12 15:12:59 +02:00
system.cpu1.num_int_register_reads 32326512 # number of times the integer registers were read
system.cpu1.num_int_register_writes 12493939 # number of times the integer registers were written
2016-05-31 12:07:18 +02:00
system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
2016-08-12 15:12:59 +02:00
system.cpu1.num_cc_register_reads 72207765 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 6423893 # number of times the CC registers were written
system.cpu1.num_mem_refs 7598514 # number of memory refs
system.cpu1.num_load_insts 4055507 # Number of load instructions
system.cpu1.num_store_insts 3543007 # Number of store instructions
system.cpu1.num_idle_cycles 5686981123.489185 # Number of idle cycles
system.cpu1.num_busy_cycles 52088515.510815 # Number of busy cycles
system.cpu1.not_idle_fraction 0.009076 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.990924 # Percentage of idle cycles
system.cpu1.Branches 2922923 # Number of branches fetched
2016-05-31 12:07:18 +02:00
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
2016-08-12 15:12:59 +02:00
system.cpu1.op_class::IntAlu 12474914 62.05% 62.05% # Class of executed instruction
system.cpu1.op_class::IntMult 26468 0.13% 62.19% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 3329 0.02% 62.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction
system.cpu1.op_class::MemRead 4055507 20.17% 82.38% # Class of executed instruction
system.cpu1.op_class::MemWrite 3543007 17.62% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-08-12 15:12:59 +02:00
system.cpu1.op_class::total 20103291 # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 186972 # number of replacements
system.cpu1.dcache.tags.tagsinuse 469.131643 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 7097155 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 187306 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 37.890698 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 127531940000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.131643 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916273 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.916273 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 14948788 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 14948788 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 3631994 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 3631994 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 3232351 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 3232351 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48894 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 48894 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78959 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 78959 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70892 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 70892 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 6864345 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 6864345 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 6913239 # number of overall hits
system.cpu1.dcache.overall_hits::total 6913239 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 133677 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 133677 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 91948 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 91948 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30343 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30343 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16973 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 16973 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23209 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23209 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 225625 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 225625 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 255968 # number of overall misses
system.cpu1.dcache.overall_misses::total 255968 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2021367000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2021367000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2373794500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 2373794500 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317489000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 317489000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544203500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 544203500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1998500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 4395161500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 4395161500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 4395161500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 4395161500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 3765671 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 3765671 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 3324299 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 3324299 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79237 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 79237 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95932 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 95932 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94101 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 94101 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 7089970 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 7089970 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 7169207 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 7169207 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035499 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027659 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.027659 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382940 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382940 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176927 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176927 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246639 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246639 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031823 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.031823 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035704 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.035704 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15121.277407 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15121.277407 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25816.706182 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25816.706182 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18705.532316 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18705.532316 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23447.951226 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23447.951226 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19479.940166 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19479.940166 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17170.745953 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17170.745953 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.writebacks::writebacks 186972 # number of writebacks
system.cpu1.dcache.writebacks::total 186972 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12048 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12048 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133394 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 133394 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91948 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 91948 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29641 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 29641 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23209 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23209 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 225342 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 225342 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 254983 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 254983 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3099 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3099 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5549 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5549 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1881488500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1881488500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2281846500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2281846500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 500338500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 500338500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85063000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85063000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521039500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521039500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1953500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1953500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4163335000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4163335000 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4663673500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4663673500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443787500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443787500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443787500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443787500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035424 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035424 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027659 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027659 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374080 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374080 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051338 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051338 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246639 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246639 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031783 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.031783 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.035566 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14104.746091 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14104.746091 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24816.706182 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24816.706182 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16879.946695 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16879.946695 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17271.675127 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17271.675127 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22449.890129 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22449.890129 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18475.628156 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18475.628156 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18290.135029 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18290.135029 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143203.452727 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143203.452727 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79976.121824 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79976.121824 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 505656 # number of replacements
system.cpu1.icache.tags.tagsinuse 498.477037 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 16060167 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 506168 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 31.728926 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 85274966000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.477037 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973588 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.973588 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu1.icache.tags.tag_accesses 33638838 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 33638838 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 16060167 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 16060167 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 16060167 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 16060167 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 16060167 # number of overall hits
system.cpu1.icache.overall_hits::total 16060167 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 506168 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 506168 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 506168 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 506168 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 506168 # number of overall misses
system.cpu1.icache.overall_misses::total 506168 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4710776500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 4710776500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 4710776500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 4710776500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4710776500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4710776500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 16566335 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 16566335 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 16566335 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 16566335 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 16566335 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 16566335 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030554 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.030554 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030554 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.030554 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030554 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.030554 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9306.744994 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9306.744994 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9306.744994 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9306.744994 # average overall miss latency
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.icache.writebacks::writebacks 505656 # number of writebacks
system.cpu1.icache.writebacks::total 505656 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506168 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 506168 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 506168 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 506168 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 506168 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 506168 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4457692500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4457692500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4457692500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 4457692500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4457692500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 4457692500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15627500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15627500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15627500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 15627500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030554 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.030554 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.030554 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8806.744994 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88290.960452 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88290.960452 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 198543 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 198543 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.prefetcher.pfSpanPage 58537 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 43670 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 14604.323800 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 603874 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 58010 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 10.409826 # Average number of references to valid blocks.
2014-12-02 12:08:25 +01:00
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.tags.occ_blocks::writebacks 14211.070638 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.100990 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.057181 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 388.094990 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.867375 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000189 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023687 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.891377 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 327 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14000 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 304 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2815 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10290 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019958 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 24332814 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 24332814 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3764 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1983 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 5747 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 114262 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 114262 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 567214 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 567214 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27479 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 27479 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 484841 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 484841 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98007 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 98007 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3764 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1983 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 484841 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 125486 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 616074 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3764 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1983 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 484841 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 125486 # number of overall hits
system.cpu1.l2cache.overall_hits::total 616074 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 441 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 340 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 781 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29645 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 29645 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23207 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 23207 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34824 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 34824 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21327 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 21327 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69953 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 69953 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 441 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 340 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 21327 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 104777 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 126885 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 441 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 340 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 21327 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 104777 # number of overall misses
system.cpu1.l2cache.overall_misses::total 126885 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9030000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6837500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 15867500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14606500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 14606500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16450500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16450500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1885500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1885500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1331294000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1331294000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 775115000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 775115000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1573819000 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1573819000 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9030000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6837500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 775115000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 2905113000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 3696095500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9030000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6837500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 775115000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 2905113000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 3696095500 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4205 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2323 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 6528 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114262 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 114262 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 567214 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 567214 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29645 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 29645 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23207 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23207 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62303 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 62303 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506168 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 506168 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167960 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 167960 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4205 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2323 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 506168 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 230263 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 742959 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4205 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2323 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 506168 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 230263 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 742959 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.104875 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.146362 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.119638 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.558946 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.558946 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042134 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042134 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.416486 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.416486 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.104875 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.146362 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042134 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.455032 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.170783 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.104875 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.146362 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042134 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.455032 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.170783 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20476.190476 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20110.294118 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20316.901408 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 492.713780 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 492.713780 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 708.859396 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 708.859396 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 942750 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 942750 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38229.209740 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38229.209740 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36344.305341 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36344.305341 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22498.234529 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22498.234529 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20476.190476 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20110.294118 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36344.305341 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27726.628936 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 29129.491272 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20476.190476 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20110.294118 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36344.305341 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27726.628936 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 29129.491272 # average overall miss latency
2015-07-19 22:03:30 +02:00
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-07-19 22:03:30 +02:00
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2015-07-19 22:03:30 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.unused_prefetches 787 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 33133 # number of writebacks
system.cpu1.l2cache.writebacks::total 33133 # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 84 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 84 # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 84 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 84 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 441 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 340 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25691 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 25691 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29645 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29645 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23207 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23207 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34740 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 34740 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21327 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21327 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69953 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69953 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 441 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 340 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21327 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104693 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 126801 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 441 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 340 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21327 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104693 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25691 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 152492 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3099 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3276 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5549 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5726 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6384000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4797500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11181500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 812147618 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 812147618 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453420500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453420500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 346968500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 346968500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1615500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1615500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1114497500 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1114497500 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 647153000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 647153000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1154101000 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1154101000 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6384000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4797500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 647153000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2268598500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 2926933000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6384000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4797500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 647153000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2268598500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 812147618 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 3739080618 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14300000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418649000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432949000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14300000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418649000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432949000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119638 # mshr miss rate for ReadReq accesses
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2016-02-10 10:08:27 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.557598 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.557598 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042134 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.416486 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.416486 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170670 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.205250 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14316.901408 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31612.145031 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15295.007590 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15295.007590 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14951.027707 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14951.027707 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 807750 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 807750 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32081.102476 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32081.102476 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30344.305341 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16498.234529 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16498.234529 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23082.885782 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24519.847717 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135091.642465 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132157.814408 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75445.846098 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75611.072302 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 1488311 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751924 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 112911 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104591 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 12675 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 724258 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 148574 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 578366 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 28228 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 30717 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 71065 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40939 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 85439 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 36 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 69452 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 66978 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506168 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 262948 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518346 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839098 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5647 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10280 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2373371 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64757444 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29422876 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9292 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16820 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 94206432 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 332481 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 4905948 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 1059226 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.359953 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.snoop_fanout::0 928762 87.68% 87.68% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 122144 11.53% 99.21% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 8320 0.79% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.snoop_fanout::total 1059226 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 1442372000 # Layer occupancy (ticks)
2016-05-31 12:07:18 +02:00
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.snoopLayer0.occupancy 79594348 # Layer occupancy (ticks)
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer0.occupancy 759429000 # Layer occupancy (ticks)
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer1.occupancy 376190500 # Layer occupancy (ticks)
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks)
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer3.occupancy 6075998 # Layer occupancy (ticks)
2014-09-20 23:18:53 +02:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2016-05-31 12:07:18 +02:00
system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
2016-02-10 10:08:27 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 48721500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer7.occupancy 94000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer24.occupancy 32045000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer25.occupancy 187728827 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2016-05-31 12:07:18 +02:00
system.iocache.tags.replacements 36445 # number of replacements
2016-08-12 15:12:59 +02:00
system.iocache.tags.tagsinuse 14.386151 # Cycle average of tags in use
2014-11-12 15:05:25 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2016-05-31 12:07:18 +02:00
system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
2014-11-12 15:05:25 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.iocache.tags.warmup_cycle 289285136000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.386151 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.899134 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.899134 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-02-10 10:08:27 +01:00
system.iocache.tags.tag_accesses 328311 # Number of tag accesses
system.iocache.tags.data_accesses 328311 # Number of data accesses
2016-08-12 15:12:59 +02:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36479 # number of overall misses
system.iocache.overall_misses::total 36479 # number of overall misses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_miss_latency::realview.ide 34821377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 34821377 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4306604450 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4306604450 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4341425827 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4341425827 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4341425827 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4341425827 # number of overall miss cycles
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-04-21 10:48:24 +02:00
system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 136554.419608 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 136554.419608 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118888.152882 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118888.152882 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 119011.645796 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 119011.645796 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-05-31 12:07:18 +02:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 22071377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 22071377 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493082245 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2493082245 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2515153622 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2515153622 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2515153622 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2515153622 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86554.419608 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 86554.419608 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68824.046074 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.046074 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 137913 # number of replacements
system.l2c.tags.tagsinuse 65077.078827 # Cycle average of tags in use
system.l2c.tags.total_refs 526584 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 203352 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.589520 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 102405123000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 6467.156176 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.052663 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.040623 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 7119.410088 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6998.473757 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.432069 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.004586 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1431.375532 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3211.021288 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2361.112045 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.098681 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy
2016-05-31 12:07:18 +02:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.l2c.tags.occ_percent::cpu0.inst 0.108634 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.106788 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571982 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.021841 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.048996 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036028 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.992997 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 34227 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 31208 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 194 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 4904 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 29129 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 1170 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 29939 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.522263 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.476196 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6120881 # Number of tag accesses
system.l2c.tags.data_accesses 6120881 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 260820 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 260820 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 40104 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 5060 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 45164 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2347 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 2252 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 4599 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 4026 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1389 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5415 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 108 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 44456 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 52767 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45168 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 38 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 18981 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 11141 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5391 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 178148 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 108 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 44456 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 56793 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 45168 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 18981 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 12530 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 5391 # number of demand (read+write) hits
system.l2c.demand_hits::total 183563 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 108 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits
system.l2c.overall_hits::cpu0.inst 44456 # number of overall hits
system.l2c.overall_hits::cpu0.data 56793 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 45168 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits
system.l2c.overall_hits::cpu1.inst 18981 # number of overall hits
system.l2c.overall_hits::cpu1.data 12530 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 5391 # number of overall hits
system.l2c.overall_hits::total 183563 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 439 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 262 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 701 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 134 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 214 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 11600 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8098 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 19698 # number of ReadExReq misses
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses
2015-07-03 16:15:03 +02:00
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_misses::cpu0.inst 17911 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 9058 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134486 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 2346 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 949 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6189 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 170949 # number of ReadSharedReq misses
2016-05-31 12:07:18 +02:00
system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
2014-12-23 15:31:20 +01:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
2016-08-12 15:12:59 +02:00
system.l2c.demand_misses::cpu0.inst 17911 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 20658 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 134486 # number of demand (read+write) misses
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2016-05-31 12:07:18 +02:00
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2014-12-23 15:31:20 +01:00
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2016-08-12 15:12:59 +02:00
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2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles
2016-08-12 15:12:59 +02:00
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system.l2c.ReadSharedReq_miss_latency::total 16317041696 # number of ReadSharedReq miss cycles
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2016-05-31 12:07:18 +02:00
system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles
2016-08-12 15:12:59 +02:00
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2016-05-31 12:07:18 +02:00
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2016-08-12 15:12:59 +02:00
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system.l2c.WritebackDirty_accesses::writebacks 260820 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 260820 # number of WritebackDirty accesses(hits+misses)
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system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010828 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.049230 # miss rate for UpgradeReq accesses
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system.l2c.overall_miss_rate::total 0.509465 # miss rate for overall accesses
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system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3616.412214 # average UpgradeReq miss latency
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2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency
2016-08-12 15:12:59 +02:00
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2016-05-31 12:07:18 +02:00
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2016-08-12 15:12:59 +02:00
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2016-05-31 12:07:18 +02:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
2016-08-12 15:12:59 +02:00
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system.l2c.overall_avg_miss_latency::total 94926.810786 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 12 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
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system.l2c.overall_mshr_hits::total 6 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 3904 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 3904 # number of CleanEvict MSHR misses
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2016-05-31 12:07:18 +02:00
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2015-07-03 16:15:03 +02:00
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2016-08-12 15:12:59 +02:00
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2016-05-31 12:07:18 +02:00
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2014-12-23 15:31:20 +01:00
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2016-08-12 15:12:59 +02:00
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2016-05-31 12:07:18 +02:00
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2014-12-23 15:31:20 +01:00
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2016-08-12 15:12:59 +02:00
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system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134486 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2341 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 9047 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6189 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 190641 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 44081 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses
2015-05-05 09:22:39 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5546 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 74994 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10668500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5960000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 16628500 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3486500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1878000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 5364500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 998115000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 585374501 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1583489501 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 543500 # number of ReadSharedReq MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1296016500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 707494000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11722877577 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 79500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 172535500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 74994000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 632508125 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 14607202702 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 543500 # number of demand (read+write) MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 1296016500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 1705609000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11722877577 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 79500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 172535500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 660368501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 632508125 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 16190692203 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 543500 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 1296016500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 1705609000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11722877577 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 79500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 172535500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 660368501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 632508125 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 16190692203 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801764501 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11113500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362869500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6757102501 # number of ReadReq MSHR uncacheable cycles
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801764501 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11113500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362869500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6757102501 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-08-12 15:12:59 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010828 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.049230 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.015284 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.054010 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034305 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.044463 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.742352 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853589 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.784375 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146510 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078495 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.489672 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.266723 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.419289 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.509449 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.266723 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.419289 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.509449 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 24301.822323 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22748.091603 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23721.112696 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26018.656716 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23475 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25067.757009 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86044.396552 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72286.305384 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 80388.338968 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average ReadSharedReq mshr miss latency
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78107.087657 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79024.236038 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85450.721597 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
2016-08-12 15:12:59 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82564.091393 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72993.091743 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 84927.650416 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
2016-08-12 15:12:59 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82564.091393 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72993.091743 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 84927.650416 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182525.781822 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117205.910853 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153288.321522 # average ReadReq mshr uncacheable latency
2016-05-31 12:07:18 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96296.444771 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.047962 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 90101.908166 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 504508 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 283356 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2016-05-31 12:07:18 +02:00
system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 44081 # Transaction distribution
system.membus.trans_dist::ReadResp 215279 # Transaction distribution
system.membus.trans_dist::WriteReq 30913 # Transaction distribution
system.membus.trans_dist::WriteResp 30913 # Transaction distribution
system.membus.trans_dist::WritebackDirty 137329 # Transaction distribution
system.membus.trans_dist::CleanEvict 16651 # Transaction distribution
system.membus.trans_dist::UpgradeReq 64792 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 38133 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::ReadExReq 40131 # Transaction distribution
system.membus.trans_dist::ReadExResp 19681 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 171198 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13736 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650114 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 771800 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_count::total 844739 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27472 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18707276 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18897612 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_size::total 21214732 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 123049 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 37632 # Total snoop traffic (bytes)
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::samples 425474 # Request fanout histogram
system.membus.snoop_fanout::mean 0.012172 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.109655 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::0 420295 98.78% 98.78% # Request fanout histogram
system.membus.snoop_fanout::1 5179 1.22% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::total 425474 # Request fanout histogram
system.membus.reqLayer0.occupancy 88273000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer2.occupancy 11470000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer5.occupancy 976922430 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer2.occupancy 1118158241 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer3.occupancy 1366131 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-08-12 15:12:59 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 1015113 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 540228 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 174806 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 29447 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 28379 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 1068 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 44084 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 511780 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 361959 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 119582 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 109939 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 42732 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 152671 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 51282 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 51282 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 467698 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 4573 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1273273 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316945 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1590218 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35272632 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5631700 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 40904332 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 389588 # Total snoops (count)
system.toL2Bus.snoopTraffic 15743116 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 889230 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.395392 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.491385 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.toL2Bus.snoop_fanout::0 538704 60.58% 60.58% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 349458 39.30% 99.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 1068 0.12% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.toL2Bus.snoop_fanout::total 889230 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 894701567 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.toL2Bus.respLayer0.occupancy 677372101 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.toL2Bus.respLayer1.occupancy 239236747 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
