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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sim_seconds 1.196134 # Number of seconds simulated
sim_ticks 1196134388000 # Number of ticks simulated
final_tick 1196134388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
host_inst_rate 708523 # Simulator instruction rate (inst/s)
host_op_rate 902798 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 13791811883 # Simulator tick rate (ticks/s)
host_mem_usage 403420 # Number of bytes of host memory used
host_seconds 86.73 # Real time elapsed on the host
sim_insts 61448705 # Number of instructions simulated
sim_ops 78297711 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4724852 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.bytes_read::cpu1.inst 323996 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4798512 # Number of bytes read from this memory
system.physmem.bytes_read::total 62145764 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 323996 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4112768 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
system.physmem.bytes_written::total 7140112 # Number of bytes written to this memory
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 73898 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.num_reads::cpu1.inst 5144 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 75003 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6654482 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 64262 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
system.physmem.num_writes::total 821098 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 43393546 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.bw_read::cpu0.inst 328876 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 3950101 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.bw_read::cpu1.inst 270869 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 4011683 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51955503 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 328876 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 270869 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 599745 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3438383 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 2516727 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 5969323 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3438383 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 43393546 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.bw_total::cpu0.inst 328876 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3964314 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.bw_total::cpu1.inst 270869 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6528410 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 57924826 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 6654482 # Number of read requests accepted
system.physmem.writeReqs 821098 # Number of write requests accepted
system.physmem.readBursts 6654482 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 821098 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 425858048 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 28800 # Total number of bytes read from write queue
system.physmem.bytesWritten 7268928 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 62145764 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7140112 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 450 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 707519 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 11807 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 415388 # Per bank write bursts
system.physmem.perBankRdBursts::1 415219 # Per bank write bursts
system.physmem.perBankRdBursts::2 415339 # Per bank write bursts
system.physmem.perBankRdBursts::3 415675 # Per bank write bursts
system.physmem.perBankRdBursts::4 422391 # Per bank write bursts
system.physmem.perBankRdBursts::5 415542 # Per bank write bursts
system.physmem.perBankRdBursts::6 415783 # Per bank write bursts
system.physmem.perBankRdBursts::7 415483 # Per bank write bursts
system.physmem.perBankRdBursts::8 416074 # Per bank write bursts
system.physmem.perBankRdBursts::9 415577 # Per bank write bursts
system.physmem.perBankRdBursts::10 415272 # Per bank write bursts
system.physmem.perBankRdBursts::11 414856 # Per bank write bursts
system.physmem.perBankRdBursts::12 415143 # Per bank write bursts
system.physmem.perBankRdBursts::13 415555 # Per bank write bursts
system.physmem.perBankRdBursts::14 415537 # Per bank write bursts
system.physmem.perBankRdBursts::15 415198 # Per bank write bursts
system.physmem.perBankWrBursts::0 6998 # Per bank write bursts
system.physmem.perBankWrBursts::1 6842 # Per bank write bursts
system.physmem.perBankWrBursts::2 7022 # Per bank write bursts
system.physmem.perBankWrBursts::3 7170 # Per bank write bursts
system.physmem.perBankWrBursts::4 7417 # Per bank write bursts
system.physmem.perBankWrBursts::5 7181 # Per bank write bursts
system.physmem.perBankWrBursts::6 7437 # Per bank write bursts
system.physmem.perBankWrBursts::7 7180 # Per bank write bursts
system.physmem.perBankWrBursts::8 7616 # Per bank write bursts
system.physmem.perBankWrBursts::9 7218 # Per bank write bursts
system.physmem.perBankWrBursts::10 7106 # Per bank write bursts
system.physmem.perBankWrBursts::11 6658 # Per bank write bursts
system.physmem.perBankWrBursts::12 6803 # Per bank write bursts
system.physmem.perBankWrBursts::13 7016 # Per bank write bursts
system.physmem.perBankWrBursts::14 7092 # Per bank write bursts
system.physmem.perBankWrBursts::15 6821 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.totGap 1196129800000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 6825 # Read request sizes (log2)
system.physmem.readPktSize::3 6488064 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.readPktSize::6 159593 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 756836 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.writePktSize::6 64262 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 634838 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 481612 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 482409 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1579414 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1125551 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1120257 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1116869 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 25458 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 24379 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 9272 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 9173 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 9118 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 8948 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 8870 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 8835 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 8809 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 205 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 5164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.bytesPerActivate::samples 74428 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 5819.401301 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 396.636644 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 13081.491079 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71 25728 34.57% 34.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135 15292 20.55% 55.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199 3262 4.38% 59.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263 2304 3.10% 62.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327 1614 2.17% 64.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391 1322 1.78% 66.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455 1040 1.40% 67.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519 1190 1.60% 69.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583 729 0.98% 70.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647 570 0.77% 71.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711 569 0.76% 72.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775 665 0.89% 72.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839 312 0.42% 73.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903 285 0.38% 73.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967 210 0.28% 74.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031 384 0.52% 74.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095 194 0.26% 74.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159 136 0.18% 74.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223 150 0.20% 75.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287 155 0.21% 75.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351 121 0.16% 75.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415 2260 3.04% 78.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479 133 0.18% 78.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543 107 0.14% 78.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607 57 0.08% 78.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671 59 0.08% 79.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735 48 0.06% 79.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799 56 0.08% 79.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863 51 0.07% 79.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927 23 0.03% 79.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991 16 0.02% 79.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055 212 0.28% 79.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119 17 0.02% 79.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183 23 0.03% 79.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247 26 0.03% 79.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311 105 0.14% 79.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375 15 0.02% 79.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439 24 0.03% 79.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503 24 0.03% 79.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567 92 0.12% 80.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631 21 0.03% 80.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695 14 0.02% 80.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759 18 0.02% 80.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823 21 0.03% 80.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887 12 0.02% 80.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951 19 0.03% 80.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015 7 0.01% 80.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079 116 0.16% 80.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143 25 0.03% 80.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207 8 0.01% 80.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271 13 0.02% 80.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335 99 0.13% 80.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463 8 0.01% 80.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527 17 0.02% 80.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591 23 0.03% 80.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655 8 0.01% 80.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719 15 0.02% 80.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783 32 0.04% 80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847 26 0.03% 80.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911 18 0.02% 80.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975 6 0.01% 80.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103 126 0.17% 80.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167 5 0.01% 80.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231 7 0.01% 80.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295 15 0.02% 80.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359 80 0.11% 81.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423 4 0.01% 81.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487 15 0.02% 81.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615 38 0.05% 81.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679 14 0.02% 81.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807 3 0.00% 81.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871 85 0.11% 81.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935 8 0.01% 81.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999 9 0.01% 81.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063 16 0.02% 81.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127 156 0.21% 81.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319 7 0.01% 81.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383 15 0.02% 81.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447 169 0.23% 81.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575 1 0.00% 81.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639 88 0.12% 82.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895 23 0.03% 82.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151 97 0.13% 82.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407 26 0.03% 82.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663 83 0.11% 82.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791 1 0.00% 82.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919 16 0.02% 82.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175 158 0.21% 82.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7303 1 0.00% 82.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431 74 0.10% 82.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687 17 0.02% 82.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943 18 0.02% 82.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199 158 0.21% 82.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8263 1 0.00% 82.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455 22 0.03% 82.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8583 1 0.00% 82.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711 18 0.02% 83.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967 80 0.11% 83.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223 161 0.22% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479 14 0.02% 83.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9607 1 0.00% 83.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735 83 0.11% 83.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991 26 0.03% 83.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247 95 0.13% 83.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503 23 0.03% 83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759 85 0.11% 83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10887 1 0.00% 83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015 14 0.02% 83.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11072-11079 2 0.00% 83.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11143 1 0.00% 83.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271 160 0.21% 84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11328-11335 1 0.00% 84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527 71 0.10% 84.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783 35 0.05% 84.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039 73 0.10% 84.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295 102 0.14% 84.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551 14 0.02% 84.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807 14 0.02% 84.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063 79 0.11% 84.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319 90 0.12% 84.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575 6 0.01% 84.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831 79 0.11% 84.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13959 1 0.00% 84.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087 82 0.11% 84.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14215 1 0.00% 84.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343 173 0.23% 85.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14407 1 0.00% 85.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599 28 0.04% 85.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855 20 0.03% 85.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111 17 0.02% 85.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15303 1 0.00% 85.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367 165 0.22% 85.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623 18 0.02% 85.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15687 1 0.00% 85.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879 85 0.11% 85.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16007 2 0.00% 85.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135 16 0.02% 85.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16263 3 0.00% 85.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391 274 0.37% 85.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647 28 0.04% 86.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903 83 0.11% 86.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17088-17095 1 0.00% 86.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159 19 0.03% 86.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17216-17223 1 0.00% 86.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415 163 0.22% 86.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17472-17479 1 0.00% 86.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17600-17607 1 0.00% 86.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671 16 0.02% 86.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17799 1 0.00% 86.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17856-17863 1 0.00% 86.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927 18 0.02% 86.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18048-18055 1 0.00% 86.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183 25 0.03% 86.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18304-18311 2 0.00% 86.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439 168 0.23% 86.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695 83 0.11% 86.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951 80 0.11% 86.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207 10 0.01% 86.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19392-19399 1 0.00% 86.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463 84 0.11% 87.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19648-19655 1 0.00% 87.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719 79 0.11% 87.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975 12 0.02% 87.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231 18 0.02% 87.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487 106 0.14% 87.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743 76 0.10% 87.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20928-20935 1 0.00% 87.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999 32 0.04% 87.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255 72 0.10% 87.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21376-21383 1 0.00% 87.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21440-21447 1 0.00% 87.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511 147 0.20% 87.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767 16 0.02% 87.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023 88 0.12% 87.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22144-22151 1 0.00% 87.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279 18 0.02% 87.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535 92 0.12% 88.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22592-22599 1 0.00% 88.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791 29 0.04% 88.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047 83 0.11% 88.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303 10 0.01% 88.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559 156 0.21% 88.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815 72 0.10% 88.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071 14 0.02% 88.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327 23 0.03% 88.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583 162 0.22% 88.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24768-24775 2 0.00% 88.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839 25 0.03% 88.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24896-24903 1 0.00% 88.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095 16 0.02% 88.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25216-25223 1 0.00% 88.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25280-25287 2 0.00% 88.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351 74 0.10% 88.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607 153 0.21% 89.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25728-25735 1 0.00% 89.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863 12 0.02% 89.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119 84 0.11% 89.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375 23 0.03% 89.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26432-26439 2 0.00% 89.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631 91 0.12% 89.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887 22 0.03% 89.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143 88 0.12% 89.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399 18 0.02% 89.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655 143 0.19% 89.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911 72 0.10% 89.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167 33 0.04% 89.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28224-28231 1 0.00% 89.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423 78 0.10% 90.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679 106 0.14% 90.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935 16 0.02% 90.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191 11 0.01% 90.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447 79 0.11% 90.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29568-29575 1 0.00% 90.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703 86 0.12% 90.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959 2 0.00% 90.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215 79 0.11% 90.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471 88 0.12% 90.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30528-30535 1 0.00% 90.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727 164 0.22% 90.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30848-30855 2 0.00% 90.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983 26 0.03% 90.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239 20 0.03% 90.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495 12 0.02% 91.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751 163 0.22% 91.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007 12 0.02% 91.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32064-32071 1 0.00% 91.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263 82 0.11% 91.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519 24 0.03% 91.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775 278 0.37% 91.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32896-32903 2 0.00% 91.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031 21 0.03% 91.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287 92 0.12% 91.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33344-33351 3 0.00% 91.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33472-33479 1 0.00% 91.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543 12 0.02% 91.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799 159 0.21% 92.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311 20 0.03% 92.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567 27 0.04% 92.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34688-34695 1 0.00% 92.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823 160 0.21% 92.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34944-34951 1 0.00% 92.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079 84 0.11% 92.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335 78 0.10% 92.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591 3 0.00% 92.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847 85 0.11% 92.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103 78 0.10% 92.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359 11 0.01% 92.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615 15 0.02% 92.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871 99 0.13% 93.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127 73 0.10% 93.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37312-37319 1 0.00% 93.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383 31 0.04% 93.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639 71 0.10% 93.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895 147 0.20% 93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151 15 0.02% 93.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407 87 0.12% 93.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663 22 0.03% 93.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919 90 0.12% 93.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39104-39111 2 0.00% 93.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175 24 0.03% 93.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431 84 0.11% 93.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39488-39495 1 0.00% 93.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687 9 0.01% 93.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39808-39815 2 0.00% 93.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943 152 0.20% 94.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199 74 0.10% 94.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40256-40263 2 0.00% 94.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711 22 0.03% 94.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40768-40775 2 0.00% 94.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967 160 0.21% 94.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479 14 0.02% 94.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735 72 0.10% 94.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991 153 0.21% 94.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42112-42119 1 0.00% 94.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247 11 0.01% 94.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503 81 0.11% 94.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759 25 0.03% 95.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015 90 0.12% 95.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43136-43143 1 0.00% 95.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271 18 0.02% 95.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43392-43399 1 0.00% 95.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527 87 0.12% 95.29% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.29% # Bytes accessed per row activation
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.bytesPerActivate::43776-43783 17 0.02% 95.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039 146 0.20% 95.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295 71 0.10% 95.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44416-44423 1 0.00% 95.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551 32 0.04% 95.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44608-44615 1 0.00% 95.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807 75 0.10% 95.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063 96 0.13% 95.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319 16 0.02% 95.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575 9 0.01% 95.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831 79 0.11% 96.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087 86 0.12% 96.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343 3 0.00% 96.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46720-46727 1 0.00% 96.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46784-46791 1 0.00% 96.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855 84 0.11% 96.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111 165 0.22% 96.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367 25 0.03% 96.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623 19 0.03% 96.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879 18 0.02% 96.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135 184 0.25% 96.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48256-48263 2 0.00% 96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391 42 0.06% 97.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48448-48455 1 0.00% 97.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647 81 0.11% 97.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903 14 0.02% 97.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967 7 0.01% 97.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031 10 0.01% 97.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095 7 0.01% 97.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159 2105 2.83% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 74428 # Bytes accessed per row activation
system.physmem.totQLat 159442536500 # Total ticks spent queuing
system.physmem.totMemAccLat 202459287750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 33270160000 # Total ticks spent in databus transfers
system.physmem.totBankLat 9746591250 # Total ticks spent accessing banks
system.physmem.avgQLat 23961.79 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 1464.76 # Average bank access latency per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.avgMemAccLat 30426.56 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.83 # Data bus utilization in percentage
system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.avgWrQLen 12.52 # Average write queue length when enqueuing
system.physmem.readRowHits 6598367 # Number of row buffer hits during reads
system.physmem.writeRowHits 94814 # Number of row buffer hits during writes
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes
system.physmem.avgGap 160004.95 # Average gap between requests
system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 4.95 # Percentage of time for which DRAM has all the banks in precharge state
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s)
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s)
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.throughput 59941628 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 7703327 # Transaction distribution
system.membus.trans_dist::ReadResp 7703327 # Transaction distribution
system.membus.trans_dist::WriteReq 767563 # Transaction distribution
system.membus.trans_dist::WriteResp 767563 # Transaction distribution
system.membus.trans_dist::Writeback 64262 # Transaction distribution
system.membus.trans_dist::UpgradeReq 31362 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 17250 # Transaction distribution
system.membus.trans_dist::UpgradeResp 11807 # Transaction distribution
system.membus.trans_dist::ReadExReq 137774 # Transaction distribution
system.membus.trans_dist::ReadExResp 137331 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382556 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4365438 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.pkt_count::total 17341566 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389866 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17381364 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 19793730 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.tot_pkt_size::total 71698242 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 71698242 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.reqLayer0.occupancy 1224728000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.reqLayer2.occupancy 9233500 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.reqLayer5.occupancy 782000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.reqLayer6.occupancy 9211169999 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.respLayer1.occupancy 5081009046 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.membus.respLayer2.occupancy 14657682249 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 1.2 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 69474 # number of replacements
system.l2c.tags.tagsinuse 52958.436277 # Cycle average of tags in use
system.l2c.tags.total_refs 1673866 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 134633 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 12.432806 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.tags.occ_blocks::writebacks 40141.137275 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.tags.occ_blocks::cpu0.inst 3711.443492 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4231.516476 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742470 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2812.646868 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2058.946054 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.612505 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.056632 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.064568 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.tags.occ_percent::cpu1.inst 0.042918 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.031417 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.808082 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65154 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1929 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 8108 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 55070 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.994171 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 17208079 # Number of tag accesses
system.l2c.tags.data_accesses 17208079 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 3830 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1752 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 419673 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 205846 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 5350 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1845 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 464495 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 143269 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1246060 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 570845 # number of Writeback hits
system.l2c.Writeback_hits::total 570845 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 1159 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 560 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1719 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 314 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 56634 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 52596 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 109230 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 3830 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1752 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 419673 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 262480 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5350 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1845 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 464495 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 195865 # number of demand (read+write) hits
system.l2c.demand_hits::total 1355290 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 3830 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1752 # number of overall hits
system.l2c.overall_hits::cpu0.inst 419673 # number of overall hits
system.l2c.overall_hits::cpu0.data 262480 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5350 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1845 # number of overall hits
system.l2c.overall_hits::cpu1.inst 464495 # number of overall hits
system.l2c.overall_hits::cpu1.data 195865 # number of overall hits
system.l2c.overall_hits::total 1355290 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 7847 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_misses::cpu1.inst 5057 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 3618 # number of ReadReq misses
system.l2c.ReadReq_misses::total 22263 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 4707 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 3611 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 8318 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 563 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 483 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1046 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 67314 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 72460 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 139774 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 75161 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_misses::cpu1.inst 5057 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 76078 # number of demand (read+write) misses
system.l2c.demand_misses::total 162037 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses
system.l2c.overall_misses::cpu0.data 75161 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_misses::cpu1.inst 5057 # number of overall misses
system.l2c.overall_misses::cpu1.data 76078 # number of overall misses
system.l2c.overall_misses::total 162037 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_miss_latency::cpu0.inst 409552750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 583496999 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 333250 # number of ReadReq miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_miss_latency::cpu1.inst 367800500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 284508500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1645947999 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 13156432 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 12072481 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 25228913 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1791423 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2509392 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 4300815 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4530126409 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 5459163398 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9989289807 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_miss_latency::cpu0.inst 409552750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 5113623408 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 333250 # number of demand (read+write) miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_miss_latency::cpu1.inst 367800500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 5743671898 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 11635237806 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_miss_latency::cpu0.inst 409552750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 5113623408 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 333250 # number of overall miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_miss_latency::cpu1.inst 367800500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 5743671898 # number of overall miss cycles
system.l2c.overall_miss_latency::total 11635237806 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 3831 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1754 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 425406 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 213693 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5354 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1846 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 469552 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 146887 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1268323 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 570845 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 570845 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 5866 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4171 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 10037 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 777 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 583 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1360 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 123948 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 125056 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 249004 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 3831 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 1754 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 425406 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 337641 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 5354 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1846 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 469552 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 271943 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1517327 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 3831 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 1754 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 425406 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 337641 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 5354 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1846 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 469552 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 271943 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1517327 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000261 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001140 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013477 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.036721 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000747 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000542 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010770 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.024631 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.017553 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.802421 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.865740 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.828734 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.724582 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.828473 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.769118 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.543083 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.579420 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.561332 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000261 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001140 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.013477 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.222606 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000747 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.000542 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.010770 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.279757 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.106791 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000261 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001140 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.013477 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.222606 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000747 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.000542 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.010770 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.279757 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.106791 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71437.772545 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74359.245444 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83312.500000 # average ReadReq miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72730.966976 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 78636.954118 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 73931.994745 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2795.077969 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3343.251454 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 3033.050373 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3181.923623 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5195.428571 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 4111.677820 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67298.428395 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75340.372592 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 71467.438916 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_avg_miss_latency::cpu0.inst 71437.772545 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 68035.595695 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83312.500000 # average overall miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_avg_miss_latency::cpu1.inst 72730.966976 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 75497.146324 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71806.055444 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_avg_miss_latency::cpu0.inst 71437.772545 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 68035.595695 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83312.500000 # average overall miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_avg_miss_latency::cpu1.inst 72730.966976 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 75497.146324 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71806.055444 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.writebacks::writebacks 64262 # number of writebacks
system.l2c.writebacks::total 64262 # number of writebacks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 7847 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_mshr_misses::cpu1.inst 5057 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 3618 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 22262 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 4707 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 3611 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 8318 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 563 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 483 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1046 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 67314 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 72460 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 139774 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 75161 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_mshr_misses::cpu1.inst 5057 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 76078 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 162036 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 75161 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_mshr_misses::cpu1.inst 5057 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 76078 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 162036 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20000 # number of ReadReq MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 336863000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 485632499 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 283250 # number of ReadReq MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 303733000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 239532500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1366251749 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47084205 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36188103 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 83272308 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5633061 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4838482 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10471543 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3661300587 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4536666102 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8197966689 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 20000 # number of demand (read+write) MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 336863000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 4146933086 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 283250 # number of demand (read+write) MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_mshr_miss_latency::cpu1.inst 303733000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 4776198602 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 9564218438 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20000 # number of overall MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 336863000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 4146933086 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 283250 # number of overall MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_mshr_miss_latency::cpu1.inst 303733000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 4776198602 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 9564218438 # number of overall MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344713750 # number of ReadReq MSHR uncacheable cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12451303994 # number of ReadReq MSHR uncacheable cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5149250 # number of ReadReq MSHR uncacheable cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154289743997 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167090910991 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1043284995 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15722213658 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 16765498653 # number of WriteReq MSHR uncacheable cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344713750 # number of overall MSHR uncacheable cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13494588989 # number of overall MSHR uncacheable cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5149250 # number of overall MSHR uncacheable cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170011957655 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183856409644 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000261 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001140 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013474 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036721 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000747 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000542 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010770 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024631 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.017552 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.802421 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865740 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.828734 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724582 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.828473 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769118 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543083 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.579420 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.561332 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000261 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001140 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013474 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.222606 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000747 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000542 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010770 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.279757 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.106790 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000261 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001140 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013474 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.222606 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000747 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000542 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010770 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.279757 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.106790 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58768.841591 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61887.663948 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000 # average ReadReq mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60061.894404 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66205.776672 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 61371.473767 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.017846 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.629189 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.097379 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10005.436945 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.561077 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.035373 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54391.368616 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62609.247888 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 58651.585338 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58768.841591 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55174.000958 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000 # average overall mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60061.894404 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62780.286049 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59025.268693 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58768.841591 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55174.000958 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000 # average overall mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60061.894404 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62780.286049 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59025.268693 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.toL2Bus.throughput 119504988 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2535165 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2535165 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 767563 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 767563 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 570845 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 30638 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 17564 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 48202 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 260860 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 260860 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864640 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226897 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6150 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12700 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939820 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600271 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6172 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15273 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7671923 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41401460 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15324 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30051724 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39586058 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7384 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21416 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 138342918 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 138342918 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 4601108 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4758624958 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.toL2Bus.respLayer0.occupancy 1926201968 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.toL2Bus.respLayer1.occupancy 1755625353 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.toL2Bus.respLayer4.occupancy 2116407722 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 2924723840 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.toL2Bus.respLayer6.occupancy 4326499 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.toL2Bus.respLayer7.occupancy 9919749 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.throughput 45391537 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7671396 # Transaction distribution
system.iobus.trans_dist::ReadResp 7671396 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.trans_dist::WriteReq 7946 # Transaction distribution
system.iobus.trans_dist::WriteResp 7946 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8052 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.pkt_count_system.bridge.master::total 2382556 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.pkt_count::total 15358684 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16104 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.tot_pkt_size_system.bridge.master::total 2389866 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.tot_pkt_size::total 54294378 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 54294378 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.reqLayer1.occupancy 4032000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.respLayer0.occupancy 2374610000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iobus.respLayer1.occupancy 17778098751 # Layer occupancy (ticks)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dtb.read_hits 7069308 # DTB read hits
system.cpu0.dtb.read_misses 3747 # DTB read misses
system.cpu0.dtb.write_hits 5655300 # DTB write hits
system.cpu0.dtb.write_misses 806 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dtb.flush_entries 1799 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dtb.read_accesses 7073055 # DTB read accesses
system.cpu0.dtb.write_accesses 5656106 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dtb.hits 12724608 # DTB hits
system.cpu0.dtb.misses 4553 # DTB misses
system.cpu0.dtb.accesses 12729161 # DTB accesses
system.cpu0.itb.inst_hits 29565201 # ITB inst hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.inst_misses 2205 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.itb.inst_accesses 29567406 # ITB inst accesses
system.cpu0.itb.hits 29565201 # DTB hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.misses 2205 # DTB misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.itb.accesses 29567406 # DTB accesses
system.cpu0.numCycles 2392268776 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.committedInsts 28867316 # Number of instructions committed
system.cpu0.committedOps 37205643 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 33092917 # Number of integer alu accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.num_func_calls 1241596 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4372519 # number of instructions that are conditional controls
system.cpu0.num_int_insts 33092917 # number of integer instructions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.num_fp_insts 3860 # number of float instructions
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.num_int_register_reads 190017972 # number of times the integer registers were read
system.cpu0.num_int_register_writes 36219842 # number of times the integer registers were written
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.num_mem_refs 13392372 # number of memory refs
system.cpu0.num_load_insts 7406786 # Number of load instructions
system.cpu0.num_store_insts 5985586 # Number of store instructions
system.cpu0.num_idle_cycles 2246456550.382122 # Number of idle cycles
system.cpu0.num_busy_cycles 145812225.617878 # Number of busy cycles
system.cpu0.not_idle_fraction 0.060951 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.939049 # Percentage of idle cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.kern.inst.quiesce 46712 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 425445 # number of replacements
system.cpu0.icache.tags.tagsinuse 509.359322 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 29139226 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 425957 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 68.408844 # Average number of references to valid blocks.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359322 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994842 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.994842 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 29991142 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 29991142 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 29139226 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29139226 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29139226 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 29139226 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29139226 # number of overall hits
system.cpu0.icache.overall_hits::total 29139226 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses
system.cpu0.icache.overall_misses::total 425958 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5905644218 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 5905644218 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 5905644218 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 5905644218 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 5905644218 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 5905644218 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 29565184 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 29565184 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 29565184 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 29565184 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 29565184 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 29565184 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014407 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014407 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014407 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014407 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014407 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014407 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13864.381507 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13864.381507 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13864.381507 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13864.381507 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13864.381507 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13864.381507 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425958 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 425958 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 425958 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 425958 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 425958 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 425958 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5051503782 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5051503782 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5051503782 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5051503782 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5051503782 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5051503782 # number of overall MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393750 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393750 # number of overall MSHR uncacheable cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014407 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014407 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014407 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014407 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014407 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014407 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11859.159311 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11859.159311 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11859.159311 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11859.159311 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11859.159311 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11859.159311 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.replacements 330301 # number of replacements
system.cpu0.dcache.tags.tagsinuse 454.615886 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 12269300 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 330813 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 37.088325 # Average number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 454.615886 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.887922 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.887922 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 50897043 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 50897043 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6599288 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6599288 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5350353 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5350353 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147935 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 147935 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149626 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 149626 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11949641 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 11949641 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11949641 # number of overall hits
system.cpu0.dcache.overall_hits::total 11949641 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 227704 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 227704 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 141542 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 141542 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9305 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9305 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7516 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7516 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 369246 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 369246 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 369246 # number of overall misses
system.cpu0.dcache.overall_misses::total 369246 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3302919746 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 3302919746 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5684238795 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 5684238795 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91447249 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 91447249 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44459563 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 44459563 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 8987158541 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 8987158541 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 8987158541 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 8987158541 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6826992 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6826992 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491895 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5491895 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157240 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 157240 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157142 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 157142 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12318887 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12318887 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12318887 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12318887 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033353 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.033353 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025773 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.025773 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059177 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059177 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047829 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047829 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029974 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.029974 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029974 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.029974 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14505.321584 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14505.321584 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40159.378806 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40159.378806 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9827.753788 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9827.753788 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5915.322379 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5915.322379 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24339.217056 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 24339.217056 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24339.217056 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 24339.217056 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.writebacks::writebacks 305829 # number of writebacks
system.cpu0.dcache.writebacks::total 305829 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227704 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 227704 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141542 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 141542 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9305 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9305 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7514 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7514 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 369246 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 369246 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 369246 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 369246 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2845576254 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2845576254 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5370172205 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5370172205 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72789751 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72789751 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29432437 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29432437 # number of StoreCondReq MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8215748459 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 8215748459 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8215748459 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 8215748459 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13558596000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13558596000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167114500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167114500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14725710500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14725710500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033353 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033353 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025773 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025773 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059177 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059177 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047817 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047817 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029974 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029974 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12496.821549 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12496.821549 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37940.485545 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37940.485545 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7822.649221 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7822.649221 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3917.013175 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3917.013175 # average StoreCondReq mshr miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22250.067595 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22250.067595 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22250.067595 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22250.067595 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.dtb.read_hits 8311308 # DTB read hits
system.cpu1.dtb.read_misses 3642 # DTB read misses
system.cpu1.dtb.write_hits 5827742 # DTB write hits
system.cpu1.dtb.write_misses 1438 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.dtb.read_accesses 8314950 # DTB read accesses
system.cpu1.dtb.write_accesses 5829180 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.dtb.hits 14139050 # DTB hits
system.cpu1.dtb.misses 5080 # DTB misses
system.cpu1.dtb.accesses 14144130 # DTB accesses
system.cpu1.itb.inst_hits 33191969 # ITB inst hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.inst_misses 2171 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.itb.inst_accesses 33194140 # ITB inst accesses
system.cpu1.itb.hits 33191969 # DTB hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.misses 2171 # DTB misses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.itb.accesses 33194140 # DTB accesses
system.cpu1.numCycles 2390799575 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.committedInsts 32581389 # Number of instructions committed
system.cpu1.committedOps 41092068 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 37316324 # Number of integer alu accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.num_func_calls 962102 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3732829 # number of instructions that are conditional controls
system.cpu1.num_int_insts 37316324 # number of integer instructions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.num_fp_insts 6793 # number of float instructions
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.num_int_register_reads 213681333 # number of times the integer registers were read
system.cpu1.num_int_register_writes 39457808 # number of times the integer registers were written
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.num_mem_refs 14676854 # number of memory refs
system.cpu1.num_load_insts 8633232 # Number of load instructions
system.cpu1.num_store_insts 6043622 # Number of store instructions
system.cpu1.num_idle_cycles 1874349488.166457 # Number of idle cycles
system.cpu1.num_busy_cycles 516450086.833543 # Number of busy cycles
system.cpu1.not_idle_fraction 0.216016 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.783984 # Percentage of idle cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.kern.inst.quiesce 43916 # number of quiesce instructions executed
system.cpu1.icache.tags.replacements 469558 # number of replacements
system.cpu1.icache.tags.tagsinuse 478.567582 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 32721895 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 470070 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 69.610686 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 93987592500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.567582 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934702 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.934702 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 33662035 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 33662035 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 32721895 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 32721895 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 32721895 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 32721895 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 32721895 # number of overall hits
system.cpu1.icache.overall_hits::total 32721895 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 470070 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 470070 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 470070 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 470070 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 470070 # number of overall misses
system.cpu1.icache.overall_misses::total 470070 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6444934971 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6444934971 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6444934971 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6444934971 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6444934971 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6444934971 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 33191965 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 33191965 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 33191965 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 33191965 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 33191965 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 33191965 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014162 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.014162 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014162 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.014162 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014162 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.014162 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13710.585596 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13710.585596 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13710.585596 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13710.585596 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13710.585596 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13710.585596 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470070 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 470070 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 470070 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 470070 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 470070 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 470070 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5502849027 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5502849027 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5502849027 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5502849027 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5502849027 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5502849027 # number of overall MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6483750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6483750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6483750 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 6483750 # number of overall MSHR uncacheable cycles
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014162 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014162 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014162 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.014162 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014162 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.014162 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11706.445906 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11706.445906 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11706.445906 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11706.445906 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11706.445906 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11706.445906 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.dcache.tags.replacements 292078 # number of replacements
system.cpu1.dcache.tags.tagsinuse 471.633961 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 11962120 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 292453 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 40.902709 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 85275256250 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.633961 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921160 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.921160 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 361 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 49437007 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 49437007 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 6946722 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 6946722 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4827432 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4827432 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81845 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 81845 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82747 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 82747 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 11774154 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 11774154 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 11774154 # number of overall hits
system.cpu1.dcache.overall_hits::total 11774154 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 170562 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 170562 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 149956 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 149956 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11055 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11055 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10053 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10053 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 320518 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 320518 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 320518 # number of overall misses
system.cpu1.dcache.overall_misses::total 320518 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219519248 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2219519248 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6569366202 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 6569366202 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92844750 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 92844750 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52203482 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 52203482 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 8788885450 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 8788885450 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 8788885450 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 8788885450 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117284 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 7117284 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977388 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 4977388 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92900 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 92900 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92800 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 92800 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 12094672 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 12094672 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 12094672 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 12094672 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023964 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.023964 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030127 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.030127 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118999 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118999 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108330 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108330 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026501 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.026501 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026501 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.026501 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13012.976208 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13012.976208 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43808.625210 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 43808.625210 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8398.439620 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8398.439620 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5192.826221 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5192.826221 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27420.879483 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 27420.879483 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27420.879483 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 27420.879483 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.dcache.writebacks::writebacks 265016 # number of writebacks
system.cpu1.dcache.writebacks::total 265016 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170562 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 170562 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149956 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 149956 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11055 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11055 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10052 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10052 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 320518 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 320518 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 320518 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 320518 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877722752 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877722752 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6246095798 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6246095798 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70722250 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70722250 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32100518 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32100518 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8123818550 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 8123818550 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8123818550 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 8123818550 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168605274000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168605274000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182596842 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182596842 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193787870842 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193787870842 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023964 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023964 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030127 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.118999 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.118999 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108319 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108319 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026501 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026501 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026501 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026501 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11009.033384 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11009.033384 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41652.856825 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41652.856825 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6397.308910 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6397.308910 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3193.445881 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3193.445881 # average StoreCondReq mshr miss latency
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25345.904286 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25345.904286 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25345.904286 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25345.904286 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651789578751 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 651789578751 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651789578751 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 651789578751 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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