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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
sim_seconds 1.183003 # Number of seconds simulated
sim_ticks 1183003114000 # Number of ticks simulated
final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
host_inst_rate 673901 # Simulator instruction rate (inst/s)
host_op_rate 858757 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 12970235901 # Simulator tick rate (ticks/s)
host_mem_usage 408748 # Number of bytes of host memory used
host_seconds 91.21 # Real time elapsed on the host
sim_insts 61465824 # Number of instructions simulated
sim_ops 78326377 # Number of ops (including micro ops) simulated
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory
system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 6654023 # Total number of read requests seen
system.physmem.writeReqs 820738 # Total number of write requests seen
system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 425857472 # Total number of bytes read from memory
system.physmem.bytesWritten 52527232 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.totGap 1182998675500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6825 # Categorize read packet sizes
system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readPktSize::6 159134 # Categorize read packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 756836 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.writePktSize::6 63902 # categorize write packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests
system.physmem.totBusLat 33269555000 # Total cycles spent in databus access
system.physmem.totBankLat 9041986250 # Total cycles spent in bank access
system.physmem.avgQLat 22090.22 # Average queueing delay per request
system.physmem.avgBankLat 1358.90 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 28449.12 # Average memory access latency
system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.16 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.16 # Average read queue length over time
system.physmem.avgWrQLen 12.54 # Average write queue length over time
system.physmem.readRowHits 6611960 # Number of row buffer hits during reads
system.physmem.writeRowHits 800133 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.49 # Row buffer hit rate for writes
system.physmem.avgGap 158265.75 # Average gap between requests
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.replacements 69015 # number of replacements
system.l2c.tagsinuse 53041.665406 # Cycle average of tags in use
system.l2c.total_refs 1678594 # Total number of references to valid blocks.
system.l2c.sampled_refs 134211 # Sample count of references to valid blocks.
system.l2c.avg_refs 12.507127 # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.occ_blocks::writebacks 40191.767552 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.003100 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 3723.993423 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 4235.450091 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 2.742043 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2826.235882 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2061.472909 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.613278 # Average percentage of cache occupancy
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.occ_percent::cpu0.inst 0.056824 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.064628 # Average percentage of cache occupancy
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.occ_percent::cpu1.inst 0.043125 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.031456 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.809352 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 3013 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1662 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 349398 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 169915 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 6389 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 534803 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 180813 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1247936 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 573205 # number of Writeback hits
system.l2c.Writeback_hits::total 573205 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 1121 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 611 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1732 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 229 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 78 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 47508 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 62580 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 3013 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1662 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 349398 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 217423 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 6389 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 534803 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 243393 # number of demand (read+write) hits
system.l2c.demand_hits::total 1358024 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 3013 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1662 # number of overall hits
system.l2c.overall_hits::cpu0.inst 349398 # number of overall hits
system.l2c.overall_hits::cpu0.data 217423 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 6389 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits
system.l2c.overall_hits::cpu1.inst 534803 # number of overall hits
system.l2c.overall_hits::cpu1.data 243393 # number of overall hits
system.l2c.overall_hits::total 1358024 # number of overall hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 5520 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 7838 # number of ReadReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_misses::cpu1.inst 5255 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 3644 # number of ReadReq misses
system.l2c.ReadReq_misses::total 22265 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 3583 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4723 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 8306 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 461 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1032 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 63840 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 75452 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 139292 # number of ReadExReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 5520 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 71678 # number of demand (read+write) misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_misses::cpu1.inst 5255 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 79096 # number of demand (read+write) misses
system.l2c.demand_misses::total 161557 # number of demand (read+write) misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 5520 # number of overall misses
system.l2c.overall_misses::cpu0.data 71678 # number of overall misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_misses::cpu1.inst 5255 # number of overall misses
system.l2c.overall_misses::cpu1.data 79096 # number of overall misses
system.l2c.overall_misses::total 161557 # number of overall misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 151500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 286631500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 416021500 # number of ReadReq miss cycles
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_miss_latency::cpu1.inst 290826000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 222550500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1216497500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 10882997 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 13761999 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 24644996 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1755500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2248500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 4004000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 2848043983 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3574373499 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6422417482 # number of ReadExReq miss cycles
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_miss_latency::cpu0.itb.walker 151500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 286631500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3264065483 # number of demand (read+write) miss cycles
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_miss_latency::cpu1.inst 290826000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 3796923999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 7638914982 # number of demand (read+write) miss cycles
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_miss_latency::cpu0.itb.walker 151500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 286631500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3264065483 # number of overall miss cycles
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_miss_latency::cpu1.inst 290826000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 3796923999 # number of overall miss cycles
system.l2c.overall_miss_latency::total 7638914982 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 3014 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1665 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 354918 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 177753 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 6393 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1943 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 540058 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 184457 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1270201 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 573205 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 573205 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 4704 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5334 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 10038 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 800 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 539 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1339 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 111348 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 138032 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 249380 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 3014 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 1665 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 354918 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 289101 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 6393 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1943 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 540058 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 322489 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1519581 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 3014 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 1665 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 354918 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 289101 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 6393 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1943 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 540058 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 322489 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1519581 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001802 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015553 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.044095 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.009730 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.019755 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.017529 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.761692 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.885452 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.827456 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.713750 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.855288 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.770724 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.573338 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.546627 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.558553 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001802 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.015553 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.247934 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.009730 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.245267 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.106317 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001802 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.015553 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.247934 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.009730 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.245267 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.106317 # miss rate for overall accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 50500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51925.996377 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 53077.507017 # average ReadReq miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55342.721218 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 61073.133919 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 54637.210869 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3037.397991 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2913.825746 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 2967.131712 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3074.430823 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4877.440347 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 3879.844961 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44612.217779 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47372.813166 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 46107.583221 # average ReadExReq miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 47283.095019 # average overall miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 47283.095019 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.writebacks::writebacks 63902 # number of writebacks
system.l2c.writebacks::total 63902 # number of writebacks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 5519 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 7838 # number of ReadReq MSHR misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_mshr_misses::cpu1.inst 5255 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 3644 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 22264 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 3583 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4723 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 8306 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 571 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 461 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1032 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 63840 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 75452 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 139292 # number of ReadExReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 5519 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 71678 # number of demand (read+write) MSHR misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_mshr_misses::cpu1.inst 5255 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 79096 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 161556 # number of demand (read+write) MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 5519 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 71678 # number of overall MSHR misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_mshr_misses::cpu1.inst 5255 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 79096 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 161556 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56252 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 113756 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 217401709 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 318301323 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 197508 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 225003397 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 176993433 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 938067378 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 35910048 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47375165 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 83285213 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5731560 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4624957 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10356517 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2039757737 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2629528179 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4669285916 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 113756 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 217401709 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2358059060 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197508 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 225003397 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 2806521612 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5607353294 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56252 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 113756 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 217401709 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2358059060 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197508 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 225003397 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 2806521612 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5607353294 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209640082 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11218408858 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3082174 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155565109792 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166996240906 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 994820748 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214915040 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 9209735788 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209640082 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12213229606 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082174 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 163780024832 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 176205976694 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044095 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019755 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.017528 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.761692 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.885452 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.827456 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.713750 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.855288 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770724 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573338 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.546627 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.558553 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.106316 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.106316 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40610.018244 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48571.194566 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 42133.820428 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.341055 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.735761 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.114496 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.758319 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.444685 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.384690 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31951.092372 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34850.344312 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 33521.565603 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.read_hits 5883553 # DTB read hits
system.cpu0.dtb.read_misses 2148 # DTB read misses
system.cpu0.dtb.write_hits 4842455 # DTB write hits
system.cpu0.dtb.write_misses 405 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 5885701 # DTB read accesses
system.cpu0.dtb.write_accesses 4842860 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.hits 10726008 # DTB hits
system.cpu0.dtb.misses 2553 # DTB misses
system.cpu0.dtb.accesses 10728561 # DTB accesses
system.cpu0.itb.inst_hits 24779849 # ITB inst hits
system.cpu0.itb.inst_misses 1350 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses
system.cpu0.itb.hits 24779849 # DTB hits
system.cpu0.itb.misses 1350 # DTB misses
system.cpu0.itb.accesses 24781199 # DTB accesses
system.cpu0.numCycles 2364565551 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.committedInsts 24381823 # Number of instructions committed
system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses
system.cpu0.num_func_calls 1070639 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls
system.cpu0.num_int_insts 28075203 # number of integer instructions
system.cpu0.num_fp_insts 4364 # number of float instructions
system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read
system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written
system.cpu0.num_mem_refs 11318426 # number of memory refs
system.cpu0.num_load_insts 6163151 # Number of load instructions
system.cpu0.num_store_insts 5155275 # Number of store instructions
system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles
system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles
system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed
system.cpu0.icache.replacements 354669 # number of replacements
system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use
system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits
system.cpu0.icache.overall_hits::total 24424650 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses
system.cpu0.icache.overall_misses::total 355182 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355182 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 355182 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 355182 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 355182 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 355182 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 355182 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4166869500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4166869500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4166869500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4166869500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4166869500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4166869500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014334 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014334 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014334 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11731.646029 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.replacements 279602 # number of replacements
system.cpu0.dcache.tagsinuse 452.516720 # Cycle average of tags in use
system.cpu0.dcache.total_refs 10326636 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 279931 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 130225 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10049347 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 10049347 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10049347 # number of overall hits
system.cpu0.dcache.overall_hits::total 10049347 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 191756 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 191756 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 126522 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 126522 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8645 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 8645 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7703 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7703 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 318278 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 318278 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 318278 # number of overall misses
system.cpu0.dcache.overall_misses::total 318278 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2678719000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 2678719000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3810145000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 3810145000 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 78655500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 78655500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45606000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 45606000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 6488864000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 6488864000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 6488864000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 6488864000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5669311 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 5669311 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4698314 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4698314 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138005 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 138005 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137928 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 137928 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 10367625 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 10367625 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 10367625 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 10367625 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033824 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.033824 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062643 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062643 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.055848 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.055848 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030699 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.030699 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030699 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.030699 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13969.414256 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13969.414256 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30114.486018 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30114.486018 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks
system.cpu0.dcache.writebacks::total 257540 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.read_hits 9504194 # DTB read hits
system.cpu1.dtb.read_misses 5263 # DTB read misses
system.cpu1.dtb.write_hits 6646220 # DTB write hits
system.cpu1.dtb.write_misses 1833 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 9509457 # DTB read accesses
system.cpu1.dtb.write_accesses 6648053 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.hits 16150414 # DTB hits
system.cpu1.dtb.misses 7096 # DTB misses
system.cpu1.dtb.accesses 16157510 # DTB accesses
system.cpu1.itb.inst_hits 37994467 # ITB inst hits
system.cpu1.itb.inst_misses 3017 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses
system.cpu1.itb.hits 37994467 # DTB hits
system.cpu1.itb.misses 3017 # DTB misses
system.cpu1.itb.accesses 37997484 # DTB accesses
system.cpu1.numCycles 2366006228 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.committedInsts 37084001 # Number of instructions committed
system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses
system.cpu1.num_func_calls 1133542 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls
system.cpu1.num_int_insts 42360540 # number of integer instructions
system.cpu1.num_fp_insts 5457 # number of float instructions
system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read
system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written
system.cpu1.num_mem_refs 16764021 # number of memory refs
system.cpu1.num_load_insts 9884261 # Number of load instructions
system.cpu1.num_store_insts 6879760 # Number of store instructions
system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles
system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles
system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed
system.cpu1.icache.replacements 540342 # number of replacements
system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use
system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits
system.cpu1.icache.overall_hits::total 37453609 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses
system.cpu1.icache.overall_misses::total 540854 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 540854 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 540854 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 540854 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 540854 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 540854 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 540854 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6219845500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 6219845500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6219845500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 6219845500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6219845500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 6219845500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4396000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4396000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4396000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 4396000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014235 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.014235 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.014235 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11500.045299 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dcache.replacements 343957 # number of replacements
system.cpu1.dcache.tagsinuse 473.088021 # Cycle average of tags in use
system.cpu1.dcache.total_refs 13916365 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 344469 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 83709904000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 473.088021 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.924000 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.924000 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 8074934 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 8074934 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 5611325 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 5611325 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100335 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 100335 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102214 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 102214 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 13686259 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 13686259 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 13686259 # number of overall hits
system.cpu1.dcache.overall_hits::total 13686259 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 207178 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 207178 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 165249 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 165249 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11790 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11790 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9834 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 9834 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 372427 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 372427 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 372427 # number of overall misses
system.cpu1.dcache.overall_misses::total 372427 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2639135500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2639135500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4834942000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 4834942000 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 103120000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 103120000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50505000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 50505000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 7474077500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 7474077500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 7474077500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 7474077500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 8282112 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 8282112 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5776574 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 5776574 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112125 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 112125 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112048 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 112048 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 14058686 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 14058686 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 14058686 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 14058686 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.025015 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.025015 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.105151 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.105151 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087766 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087766 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026491 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.026491 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026491 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.026491 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12738.492987 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12738.492987 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29258.525014 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 29258.525014 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8746.395250 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8746.395250 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5135.753508 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5135.753508 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20068.570485 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20068.570485 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks
system.cpu1.dcache.writebacks::total 315665 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_refs nan # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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