2011-08-19 22:08:09 +02:00
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---------- Begin Simulation Statistics ----------
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2012-10-25 19:14:42 +02:00
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sim_seconds 1.182883 # Number of seconds simulated
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2012-10-25 19:15:59 +02:00
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sim_ticks 1182883275000 # Number of ticks simulated
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final_tick 1182883275000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-08-19 22:08:09 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-10-25 19:15:59 +02:00
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host_inst_rate 656929 # Simulator instruction rate (inst/s)
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host_op_rate 837075 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 12645375755 # Simulator tick rate (ticks/s)
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host_mem_usage 400812 # Number of bytes of host memory used
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host_seconds 93.54 # Real time elapsed on the host
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sim_insts 61450949 # Number of instructions simulated
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sim_ops 78302298 # Number of ops (including micro ops) simulated
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2012-10-15 14:12:21 +02:00
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system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
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2012-10-25 19:14:42 +02:00
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
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2012-10-25 19:15:59 +02:00
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system.physmem.bytes_read::cpu0.data 4708212 # Number of bytes read from this memory
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2012-10-25 19:14:42 +02:00
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system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
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2012-10-25 19:15:59 +02:00
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system.physmem.bytes_read::cpu1.data 4780336 # Number of bytes read from this memory
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system.physmem.bytes_read::total 62110052 # Number of bytes read from this memory
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2012-10-25 19:14:42 +02:00
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system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
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2012-10-25 19:15:59 +02:00
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system.physmem.bytes_written::writebacks 4085888 # Number of bytes written to this memory
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2012-10-15 14:12:21 +02:00
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
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2012-10-25 19:15:59 +02:00
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system.physmem.bytes_written::total 7113232 # Number of bytes written to this memory
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2012-10-15 14:12:21 +02:00
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system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
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2012-10-25 19:14:42 +02:00
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
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2012-10-25 19:15:59 +02:00
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system.physmem.num_reads::cpu0.data 73638 # Number of read requests responded to by this memory
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2012-10-25 19:14:42 +02:00
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system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
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2012-10-25 19:15:59 +02:00
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system.physmem.num_reads::cpu1.data 74719 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 6653924 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 63842 # Number of write requests responded to by this memory
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2012-10-15 14:12:21 +02:00
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
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2012-10-25 19:15:59 +02:00
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system.physmem.num_writes::total 820678 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 43879657 # Total read bandwidth from this memory (bytes/s)
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2012-10-25 19:14:42 +02:00
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system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s)
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2012-10-25 19:15:59 +02:00
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system.physmem.bw_read::cpu0.data 3980285 # Total read bandwidth from this memory (bytes/s)
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2012-10-25 19:14:42 +02:00
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system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s)
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2012-10-25 19:15:59 +02:00
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system.physmem.bw_read::cpu1.data 4041258 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 52507338 # Total read bandwidth from this memory (bytes/s)
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2012-10-25 19:14:42 +02:00
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system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s)
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2012-10-25 19:15:59 +02:00
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system.physmem.bw_write::writebacks 3454177 # Write bandwidth from this memory (bytes/s)
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2012-10-25 19:14:42 +02:00
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system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s)
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2012-10-25 19:15:59 +02:00
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system.physmem.bw_write::total 6013469 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3454177 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 43879657 # Total bandwidth to/from this memory (bytes/s)
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2012-10-25 19:14:42 +02:00
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system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s)
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2012-10-25 19:15:59 +02:00
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system.physmem.bw_total::cpu0.data 3994656 # Total bandwidth to/from this memory (bytes/s)
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2012-10-25 19:14:42 +02:00
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system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s)
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2012-10-25 19:15:59 +02:00
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system.physmem.bw_total::cpu1.data 6586178 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 58520807 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 6653924 # Total number of read requests seen
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system.physmem.writeReqs 820678 # Total number of write requests seen
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system.physmem.cpureqs 271841 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 425851136 # Total number of bytes read from memory
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system.physmem.bytesWritten 52523392 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 62110052 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7113232 # bytesWritten derated as per pkt->getSize()
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2012-10-25 19:14:42 +02:00
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system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q
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2012-10-25 19:15:59 +02:00
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system.physmem.neitherReadNorWrite 11752 # Reqs where no action is needed
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2012-10-25 19:14:42 +02:00
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system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis
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2012-10-25 19:15:59 +02:00
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system.physmem.perBankRdReqs::3 415464 # Track reads on a per bank basis
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2012-10-25 19:14:42 +02:00
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system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis
|
2012-10-25 19:15:59 +02:00
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system.physmem.perBankWrReqs::3 50650 # Track writes on a per bank basis
|
2012-10-25 19:14:42 +02:00
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system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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2012-10-25 19:15:59 +02:00
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system.physmem.totGap 1182878800500 # Total gap between requests
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2012-10-25 19:14:42 +02:00
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 6825 # Categorize read packet sizes
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system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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2012-10-25 19:15:59 +02:00
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system.physmem.readPktSize::6 159035 # Categorize read packet sizes
|
2012-10-25 19:14:42 +02:00
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 756836 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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2012-10-25 19:15:59 +02:00
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system.physmem.writePktSize::6 63842 # categorize write packet sizes
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2012-10-25 19:14:42 +02:00
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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2012-10-25 19:15:59 +02:00
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system.physmem.neitherpktsize::6 11752 # categorize neither packet sizes
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2012-10-25 19:14:42 +02:00
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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2012-10-25 19:15:59 +02:00
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system.physmem.rdQLenPdf::0 6596894 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 41002 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 11213 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1803 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 662 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 504 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 410 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 308 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 169 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see
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|
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system.physmem.rdQLenPdf::11 127 # What read queue length does an incoming req see
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|
|
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system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
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|
|
system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see
|
2012-10-25 19:15:59 +02:00
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|
|
system.physmem.rdQLenPdf::14 67 # What read queue length does an incoming req see
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|
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system.physmem.rdQLenPdf::15 40 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 14 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
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|
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
|
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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|
|
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
|
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
|
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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|
|
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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|
|
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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|
|
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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|
|
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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|
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see
|
2012-10-25 19:15:59 +02:00
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|
system.physmem.wrQLenPdf::15 35681 # What write queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.totQLat 3569461684 # Total cycles spent in queuing delays
|
|
|
|
|
system.physmem.totMemAccLat 123099843684 # Sum of mem lat for all requests
|
|
|
|
|
system.physmem.totBusLat 26615168000 # Total cycles spent in databus access
|
|
|
|
|
system.physmem.totBankLat 92915214000 # Total cycles spent in bank access
|
|
|
|
|
system.physmem.avgQLat 536.46 # Average queueing delay per request
|
|
|
|
|
system.physmem.avgBankLat 13964.25 # Average bank access latency per request
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgBusLat 4000.00 # Average bus latency per request
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.avgMemAccLat 18500.71 # Average memory access latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s
|
|
|
|
|
system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgConsumedWrBW 6.01 # Average consumed write bandwidth in MB/s
|
|
|
|
|
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
|
|
|
|
system.physmem.busUtil 2.53 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.avgRdQLen 0.10 # Average read queue length over time
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.avgWrQLen 15.10 # Average write queue length over time
|
|
|
|
|
system.physmem.readRowHits 6624970 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 788587 # Number of row buffer hits during writes
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
|
|
|
|
|
system.physmem.writeRowHitRate 96.09 # Row buffer hit rate for writes
|
2012-10-25 19:15:59 +02:00
|
|
|
system.physmem.avgGap 158253.08 # Average gap between requests
|
2012-10-23 10:49:48 +02:00
|
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
|
2012-10-23 10:49:48 +02:00
|
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
|
2012-10-23 10:49:48 +02:00
|
|
|
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
|
2012-10-25 19:14:42 +02:00
|
|
|
system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.replacements 68922 # number of replacements
|
|
|
|
|
system.l2c.tagsinuse 53038.398444 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 1676342 # Total number of references to valid blocks.
|
|
|
|
|
system.l2c.sampled_refs 134082 # Sample count of references to valid blocks.
|
|
|
|
|
system.l2c.avg_refs 12.502364 # Average number of references to valid blocks.
|
2011-08-19 22:08:09 +02:00
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.occ_blocks::writebacks 40183.482743 # Average occupied blocks per requestor
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.occ_blocks::cpu0.dtb.walker 0.000405 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.itb.walker 0.001414 # Average occupied blocks per requestor
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.occ_blocks::cpu0.inst 3728.899373 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.data 4237.689144 # Average occupied blocks per requestor
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.occ_blocks::cpu1.dtb.walker 2.742166 # Average occupied blocks per requestor
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.occ_blocks::cpu1.inst 2823.942801 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu1.data 2061.640399 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_percent::writebacks 0.613151 # Average percentage of cache occupancy
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.occ_percent::cpu0.inst 0.056898 # Average percentage of cache occupancy
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.occ_percent::cpu0.data 0.064662 # Average percentage of cache occupancy
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu1.inst 0.043090 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu1.data 0.031458 # Average percentage of cache occupancy
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.occ_percent::total 0.809302 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 4216 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 1874 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.inst 419651 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.data 206094 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 5524 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 1914 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.inst 464156 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.data 143505 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 1246934 # number of ReadReq hits
|
|
|
|
|
system.l2c.Writeback_hits::writebacks 571634 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 571634 # number of Writeback hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::cpu0.data 1136 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::total 1711 # number of UpgradeReq hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 215 # number of SCUpgradeReq hits
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::total 314 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::cpu0.data 56997 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::cpu1.data 52866 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::total 109863 # number of ReadExReq hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.dtb.walker 4216 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.itb.walker 1874 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.inst 419651 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.data 263091 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.dtb.walker 5524 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.itb.walker 1914 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.inst 464156 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.data 196371 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::total 1356797 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.dtb.walker 4216 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.itb.walker 1874 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.inst 419651 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.data 263091 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.dtb.walker 5524 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.itb.walker 1914 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.inst 464156 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.data 196371 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::total 1356797 # number of overall hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu0.data 7859 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu1.data 3621 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 22264 # number of ReadReq misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.UpgradeReq_misses::cpu0.data 4681 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3591 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::total 8272 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 561 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 470 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::total 1031 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::cpu0.data 67060 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::cpu1.data 72161 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 139221 # number of ReadExReq misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_misses::cpu0.data 74919 # number of demand (read+write) misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_misses::cpu1.data 75782 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::total 161485 # number of demand (read+write) misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_misses::cpu0.data 74919 # number of overall misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_misses::cpu1.data 75782 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::total 161485 # number of overall misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 67500 # number of ReadReq miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 285527000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 405599500 # number of ReadReq miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 259776000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 211385500 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_latency::total 1162672000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 12888997 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 11730499 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency::total 24619496 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1705500 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2384500 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency::total 4090000 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 2999097972 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 3428190491 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_latency::total 6427288463 # number of ReadExReq miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 67500 # number of demand (read+write) miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_miss_latency::cpu0.inst 285527000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu0.data 3404697472 # number of demand (read+write) miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_miss_latency::cpu1.inst 259776000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::cpu1.data 3639575991 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_latency::total 7589960463 # number of demand (read+write) miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 67500 # number of overall miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_miss_latency::cpu0.inst 285527000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu0.data 3404697472 # number of overall miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_miss_latency::cpu1.inst 259776000 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::cpu1.data 3639575991 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_latency::total 7589960463 # number of overall miss cycles
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4217 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 1876 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.inst 425384 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.data 213953 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5528 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 1914 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.inst 469200 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.data 147126 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 1269198 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::writebacks 571634 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 571634 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 5817 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 4166 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 9983 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::total 1345 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::cpu0.data 124057 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::cpu1.data 125027 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 249084 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 4217 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.itb.walker 1876 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.inst 425384 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.data 338010 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 5528 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.itb.walker 1914 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.inst 469200 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.data 272153 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::total 1518282 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 4217 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.itb.walker 1876 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.inst 425384 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.data 338010 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 5528 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.itb.walker 1914 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.inst 469200 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.data 272153 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::total 1518282 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001066 # miss rate for ReadReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013477 # miss rate for ReadReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.036732 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for ReadReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.024612 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::total 0.017542 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.804710 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.861978 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::total 0.828609 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.722938 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826011 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.766543 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.540558 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.577163 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::total 0.558932 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001066 # miss rate for demand accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.013477 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.data 0.221647 # miss rate for demand accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for demand accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_miss_rate::cpu1.data 0.278454 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total 0.106360 # miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001066 # miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.013477 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.data 0.221647 # miss rate for overall accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_miss_rate::cpu1.data 0.278454 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total 0.106360 # miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 33750 # average ReadReq miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49804.116518 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 51609.555923 # average ReadReq miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51501.982554 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 58377.658105 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total 52222.062522 # average ReadReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2753.470840 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3266.638541 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 2976.244681 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3040.106952 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5073.404255 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 3967.022308 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44722.606203 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47507.524716 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total 46166.084592 # average ReadExReq miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total 47001.024634 # average overall miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total 47001.024634 # average overall miss latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.writebacks::writebacks 63842 # number of writebacks
|
|
|
|
|
system.l2c.writebacks::total 63842 # number of writebacks
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
|
2012-05-11 01:04:29 +02:00
|
|
|
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
|
2012-05-11 01:04:29 +02:00
|
|
|
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
|
2012-05-11 01:04:29 +02:00
|
|
|
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 7859 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 3621 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses::total 22263 # number of ReadReq MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 4681 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 3591 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_misses::total 8272 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 561 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 470 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1031 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 67060 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 72161 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_misses::total 139221 # number of ReadExReq MSHR misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_mshr_misses::cpu0.data 74919 # number of demand (read+write) MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_mshr_misses::cpu1.data 75782 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.demand_mshr_misses::total 161484 # number of demand (read+write) MSHR misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_misses::cpu0.data 74919 # number of overall MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_misses::cpu1.data 75782 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_misses::total 161484 # number of overall MSHR misses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56002 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 42004 # number of ReadReq MSHR miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 212718377 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 304840627 # number of ReadReq MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 196008 # number of ReadReq MSHR miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 195716490 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 165149154 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency::total 878718662 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 46986078 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 35996056 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 82982134 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5623056 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4727457 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10350513 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2155048026 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2506935370 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 4661983396 # number of ReadExReq MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 42004 # number of demand (read+write) MSHR miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 212718377 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 2459888653 # number of demand (read+write) MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 196008 # number of demand (read+write) MSHR miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 195716490 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 2672084524 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_latency::total 5540702058 # number of demand (read+write) MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56002 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 42004 # number of overall MSHR miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 212718377 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 2459888653 # number of overall MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 196008 # number of overall MSHR miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 195716490 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 2672084524 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_latency::total 5540702058 # number of overall MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 197971583 # number of ReadReq MSHR uncacheable cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12452500109 # number of ReadReq MSHR uncacheable cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3031674 # number of ReadReq MSHR uncacheable cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154310795041 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 166964298407 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000517750 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209233939 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 9209751689 # number of WriteReq MSHR uncacheable cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 197971583 # number of overall MSHR uncacheable cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13453017859 # number of overall MSHR uncacheable cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3031674 # number of overall MSHR uncacheable cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162520028980 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency::total 176174050096 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for ReadReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for ReadReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036732 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024612 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.804710 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.861978 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.828609 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.722938 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826011 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.766543 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540558 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577163 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.558932 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for demand accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for demand accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for demand accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total 0.106360 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for overall accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total 0.106360 # mshr miss rate for overall accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38788.729737 # average ReadReq mshr miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45608.714167 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 39469.912501 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.615467 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.964355 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.689313 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10023.272727 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.419149 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.294859 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.117298 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34740.862377 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 33486.208230 # average ReadExReq mshr miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency
|
2012-10-25 19:14:42 +02:00
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
|
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
|
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dtb.read_hits 7072907 # DTB read hits
|
|
|
|
|
system.cpu0.dtb.read_misses 3765 # DTB read misses
|
|
|
|
|
system.cpu0.dtb.write_hits 5658426 # DTB write hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dtb.write_misses 809 # DTB write misses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dtb.read_accesses 7076672 # DTB read accesses
|
|
|
|
|
system.cpu0.dtb.write_accesses 5659235 # DTB write accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dtb.hits 12731333 # DTB hits
|
|
|
|
|
system.cpu0.dtb.misses 4574 # DTB misses
|
|
|
|
|
system.cpu0.dtb.accesses 12735907 # DTB accesses
|
|
|
|
|
system.cpu0.itb.inst_hits 29570611 # ITB inst hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.itb.inst_misses 2205 # ITB inst misses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.itb.inst_accesses 29572816 # ITB inst accesses
|
|
|
|
|
system.cpu0.itb.hits 29570611 # DTB hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.itb.misses 2205 # DTB misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.itb.accesses 29572816 # DTB accesses
|
|
|
|
|
system.cpu0.numCycles 2365766550 # number of cpu cycles simulated
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.committedInsts 28872677 # Number of instructions committed
|
|
|
|
|
system.cpu0.committedOps 37219640 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu0.num_int_alu_accesses 33106294 # Number of integer alu accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.num_func_calls 1241693 # number of times a function call or return occured
|
|
|
|
|
system.cpu0.num_conditional_control_insts 4373343 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu0.num_int_insts 33106294 # number of integer instructions
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.num_fp_insts 3860 # number of float instructions
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.num_int_register_reads 190095681 # number of times the integer registers were read
|
|
|
|
|
system.cpu0.num_int_register_writes 36231150 # number of times the integer registers were written
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
|
|
|
|
|
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.num_mem_refs 13399479 # number of memory refs
|
|
|
|
|
system.cpu0.num_load_insts 7410420 # Number of load instructions
|
|
|
|
|
system.cpu0.num_store_insts 5989059 # Number of store instructions
|
|
|
|
|
system.cpu0.num_idle_cycles 2224930438.354119 # Number of idle cycles
|
|
|
|
|
system.cpu0.num_busy_cycles 140836111.645881 # Number of busy cycles
|
|
|
|
|
system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.kern.inst.quiesce 46695 # number of quiesce instructions executed
|
|
|
|
|
system.cpu0.icache.replacements 425420 # number of replacements
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.icache.total_refs 29144662 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.sampled_refs 425932 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.avg_refs 68.425622 # Average number of references to valid blocks.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 29144662 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.ReadReq_hits::total 29144662 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.demand_hits::cpu0.inst 29144662 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.demand_hits::total 29144662 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.overall_hits::cpu0.inst 29144662 # number of overall hits
|
|
|
|
|
system.cpu0.icache.overall_hits::total 29144662 # number of overall hits
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 425932 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::total 425932 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.demand_misses::cpu0.inst 425932 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.demand_misses::total 425932 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.overall_misses::cpu0.inst 425932 # number of overall misses
|
|
|
|
|
system.cpu0.icache.overall_misses::total 425932 # number of overall misses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794628000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_latency::total 5794628000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 5794628000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.icache.demand_miss_latency::total 5794628000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 5794628000 # number of overall miss cycles
|
|
|
|
|
system.cpu0.icache.overall_miss_latency::total 5794628000 # number of overall miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570594 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses::total 29570594 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 29570594 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.demand_accesses::total 29570594 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 29570594 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_accesses::total 29570594 # number of overall (read+write) accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::total 0.014404 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014404 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::total 0.014404 # miss rate for overall accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.584769 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.584769 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13604.584769 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13604.584769 # average overall miss latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425932 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 425932 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 425932 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.icache.demand_mshr_misses::total 425932 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 425932 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.icache.overall_mshr_misses::total 425932 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942764000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942764000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942764000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4942764000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942764000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4942764000 # number of overall MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288882000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 288882000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014404 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.014404 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.014404 # mshr miss rate for overall accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.584769 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.replacements 330832 # number of replacements
|
|
|
|
|
system.cpu0.dcache.tagsinuse 453.835370 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.dcache.total_refs 12275735 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.sampled_refs 331344 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.avg_refs 37.048309 # Average number of references to valid blocks.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit.
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 453.835370 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.886397 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.dcache.occ_percent::total 0.886397 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6602660 # number of ReadReq hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_hits::total 6602660 # number of ReadReq hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 5353299 # number of WriteReq hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_hits::total 5353299 # number of WriteReq hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147927 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 147927 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149680 # number of StoreCondReq hits
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_hits::total 149680 # number of StoreCondReq hits
|
|
|
|
|
system.cpu0.dcache.demand_hits::cpu0.data 11955959 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.dcache.demand_hits::total 11955959 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.dcache.overall_hits::cpu0.data 11955959 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.overall_hits::total 11955959 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 227931 # number of ReadReq misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_misses::total 227931 # number of ReadReq misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 141702 # number of WriteReq misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_misses::total 141702 # number of WriteReq misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9328 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 9328 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses
|
|
|
|
|
system.cpu0.dcache.demand_misses::cpu0.data 369633 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.dcache.demand_misses::total 369633 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.dcache.overall_misses::cpu0.data 369633 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.overall_misses::total 369633 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3133125500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 3133125500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4126730000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 4126730000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88286000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 88286000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44416500 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 44416500 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 7259855500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_miss_latency::total 7259855500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 7259855500 # number of overall miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_miss_latency::total 7259855500 # number of overall miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6830591 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.ReadReq_accesses::total 6830591 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495001 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.WriteReq_accesses::total 5495001 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157255 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 157255 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157172 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 157172 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12325592 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.demand_accesses::total 12325592 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12325592 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_accesses::total 12325592 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033369 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.033369 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025787 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.025787 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059318 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059318 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047668 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047668 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029989 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.demand_miss_rate::total 0.029989 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029989 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::total 0.029989 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13745.938464 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13745.938464 # average ReadReq miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29122.595306 # average WriteReq miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 29122.595306 # average WriteReq miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9464.622642 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9464.622642 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5928.523759 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5928.523759 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 19640.712545 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 19640.712545 # average overall miss latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.writebacks::writebacks 306514 # number of writebacks
|
|
|
|
|
system.cpu0.dcache.writebacks::total 306514 # number of writebacks
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227931 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 227931 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141702 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 141702 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9328 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9328 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 369633 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_misses::total 369633 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 369633 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_misses::total 369633 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2677263500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2677263500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3843326000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3843326000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69630000 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69630000 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29442500 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29442500 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6520589500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 6520589500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6520589500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 6520589500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13560077000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13560077000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128521500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128521500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688598500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688598500 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033369 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025787 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025787 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059318 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059318 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047648 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047648 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029989 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029989 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.938464 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.938464 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27122.595306 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27122.595306 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7464.622642 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7464.622642 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3931.432768 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3931.432768 # average StoreCondReq mshr miss latency
|
2012-09-10 17:57:37 +02:00
|
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
|
|
|
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dtb.read_hits 8308581 # DTB read hits
|
|
|
|
|
system.cpu1.dtb.read_misses 3643 # DTB read misses
|
|
|
|
|
system.cpu1.dtb.write_hits 5825594 # DTB write hits
|
|
|
|
|
system.cpu1.dtb.write_misses 1436 # DTB write misses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dtb.read_accesses 8312224 # DTB read accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.dtb.write_accesses 5827030 # DTB write accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dtb.hits 14134175 # DTB hits
|
|
|
|
|
system.cpu1.dtb.misses 5079 # DTB misses
|
|
|
|
|
system.cpu1.dtb.accesses 14139254 # DTB accesses
|
|
|
|
|
system.cpu1.itb.inst_hits 33188757 # ITB inst hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.itb.inst_misses 2171 # ITB inst misses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.itb.inst_accesses 33190928 # ITB inst accesses
|
|
|
|
|
system.cpu1.itb.hits 33188757 # DTB hits
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.itb.misses 2171 # DTB misses
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.itb.accesses 33190928 # DTB accesses
|
|
|
|
|
system.cpu1.numCycles 2364324282 # number of cpu cycles simulated
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.committedInsts 32578272 # Number of instructions committed
|
|
|
|
|
system.cpu1.committedOps 41082658 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu1.num_int_alu_accesses 37307259 # Number of integer alu accesses
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
|
|
|
|
|
system.cpu1.num_func_calls 961975 # number of times a function call or return occured
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.num_conditional_control_insts 3732574 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu1.num_int_insts 37307259 # number of integer instructions
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.num_fp_insts 6793 # number of float instructions
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.num_int_register_reads 213628675 # number of times the integer registers were read
|
|
|
|
|
system.cpu1.num_int_register_writes 39450611 # number of times the integer registers were written
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
|
|
|
|
|
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.num_mem_refs 14671912 # number of memory refs
|
|
|
|
|
system.cpu1.num_load_insts 8630468 # Number of load instructions
|
|
|
|
|
system.cpu1.num_store_insts 6041444 # Number of store instructions
|
|
|
|
|
system.cpu1.num_idle_cycles 1868307269.461274 # Number of idle cycles
|
|
|
|
|
system.cpu1.num_busy_cycles 496017012.538726 # Number of busy cycles
|
|
|
|
|
system.cpu1.not_idle_fraction 0.209792 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu1.idle_fraction 0.790208 # Percentage of idle cycles
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.kern.inst.quiesce 43897 # number of quiesce instructions executed
|
|
|
|
|
system.cpu1.icache.replacements 469210 # number of replacements
|
|
|
|
|
system.cpu1.icache.tagsinuse 478.783126 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.icache.total_refs 32719031 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.sampled_refs 469722 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.avg_refs 69.656160 # Average number of references to valid blocks.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit.
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 478.783126 # Average occupied blocks per requestor
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 32719031 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.ReadReq_hits::total 32719031 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.demand_hits::cpu1.inst 32719031 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.demand_hits::total 32719031 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.overall_hits::cpu1.inst 32719031 # number of overall hits
|
|
|
|
|
system.cpu1.icache.overall_hits::total 32719031 # number of overall hits
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 469722 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::total 469722 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.demand_misses::cpu1.inst 469722 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.demand_misses::total 469722 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.overall_misses::cpu1.inst 469722 # number of overall misses
|
|
|
|
|
system.cpu1.icache.overall_misses::total 469722 # number of overall misses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6346616500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_latency::total 6346616500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 6346616500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_latency::total 6346616500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 6346616500 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_latency::total 6346616500 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188753 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses::total 33188753 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 33188753 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.demand_accesses::total 33188753 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 33188753 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_accesses::total 33188753 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13511.431230 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13511.431230 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13511.431230 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13511.431230 # average overall miss latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469722 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 469722 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 469722 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_misses::total 469722 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 469722 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_misses::total 469722 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5407172500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5407172500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5407172500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 5407172500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5407172500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 5407172500 # number of overall MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11511.431230 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.replacements 291698 # number of replacements
|
|
|
|
|
system.cpu1.dcache.tagsinuse 472.096881 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.dcache.total_refs 11957476 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.sampled_refs 292067 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.avg_refs 40.940866 # Average number of references to valid blocks.
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.dcache.warmup_cycle 83625331000 # Cycle when the warmup percentage was hit.
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 472.096881 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.922064 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.occ_percent::total 0.922064 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 6944335 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_hits::total 6944335 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4825513 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits::total 4825513 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81763 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 81763 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82710 # number of StoreCondReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::total 82710 # number of StoreCondReq hits
|
|
|
|
|
system.cpu1.dcache.demand_hits::cpu1.data 11769848 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.demand_hits::total 11769848 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.overall_hits::cpu1.data 11769848 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.overall_hits::total 11769848 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 170295 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::total 170295 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 149789 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::total 149789 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11069 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 11069 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10034 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10034 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.demand_misses::cpu1.data 320084 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.demand_misses::total 320084 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.overall_misses::cpu1.data 320084 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.overall_misses::total 320084 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2151167000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 2151167000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4518557500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 4518557500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92001000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 92001000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51654000 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 51654000 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 6669724500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_miss_latency::total 6669724500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 6669724500 # number of overall miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_miss_latency::total 6669724500 # number of overall miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114630 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::total 7114630 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975302 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::total 4975302 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92832 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 92832 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92744 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 92744 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 12089932 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.demand_accesses::total 12089932 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 12089932 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_accesses::total 12089932 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023936 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.023936 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030107 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.030107 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119237 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119237 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108190 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108190 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026475 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::total 0.026475 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026475 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::total 0.026475 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12632.003288 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12632.003288 # average ReadReq miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30166.150385 # average WriteReq miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 30166.150385 # average WriteReq miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8311.590930 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8311.590930 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5147.897150 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5147.897150 # average StoreCondReq miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 20837.419240 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 20837.419240 # average overall miss latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.writebacks::writebacks 265120 # number of writebacks
|
|
|
|
|
system.cpu1.dcache.writebacks::total 265120 # number of writebacks
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170295 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 170295 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149789 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 149789 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11069 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11069 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10028 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10028 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 320084 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_misses::total 320084 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 320084 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_misses::total 320084 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1810577000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1810577000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4218979500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4218979500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69863000 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69863000 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31600000 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6029556500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 6029556500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6029556500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 6029556500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168626695000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168626695000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666887000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666887000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186293582000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186293582000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023936 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023936 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030107 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030107 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119237 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119237 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108126 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108126 # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026475 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026475 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10632.003288 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10632.003288 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28166.150385 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28166.150385 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6311.590930 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6311.590930 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3151.176705 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3151.176705 # average StoreCondReq mshr miss latency
|
2012-10-15 14:12:21 +02:00
|
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
2012-10-25 19:15:59 +02:00
|
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2012-10-25 19:15:59 +02:00
|
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446757532781 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 446757532781 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446757532781 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency::total 446757532781 # number of overall MSHR uncacheable cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
