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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
sim_seconds 1.169707 # Number of seconds simulated
sim_ticks 1169707043000 # Number of ticks simulated
final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
host_inst_rate 754175 # Simulator instruction rate (inst/s)
host_op_rate 964493 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 14598169556 # Simulator tick rate (ticks/s)
host_mem_usage 379804 # Number of bytes of host memory used
host_seconds 80.13 # Real time elapsed on the host
sim_insts 60429704 # Number of instructions simulated
sim_ops 77281862 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 61898788 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10078928 # Number of bytes written to this memory
system.physmem.num_reads 6478591 # Number of read requests responded to by this memory
system.physmem.num_writes 867017 # Number of write requests responded to by this memory
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.physmem.num_other 0 # Number of other requests responded to by this memory
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory
system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 125934 # number of replacements
system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use
system.l2c.total_refs 1500548 # Total number of references to valid blocks.
system.l2c.sampled_refs 155551 # Sample count of references to valid blocks.
system.l2c.avg_refs 9.646663 # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.occ_percent::cpu1.inst 0.036719 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.034433 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.420107 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 4097 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1763 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 399350 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 205866 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 5680 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1949 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 446193 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 140780 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1205678 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 577354 # number of Writeback hits
system.l2c.Writeback_hits::total 577354 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 1189 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1738 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 223 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 193 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 416 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 53827 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 49705 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 103532 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 4097 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1763 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 399350 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 259693 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5680 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1949 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 446193 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 190485 # number of demand (read+write) hits
system.l2c.demand_hits::total 1309210 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 4097 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1763 # number of overall hits
system.l2c.overall_hits::cpu0.inst 399350 # number of overall hits
system.l2c.overall_hits::cpu0.data 259693 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5680 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1949 # number of overall hits
system.l2c.overall_hits::cpu1.inst 446193 # number of overall hits
system.l2c.overall_hits::cpu1.data 190485 # number of overall hits
system.l2c.overall_hits::total 1309210 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7942 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 11318 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 7342 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 8301 # number of ReadReq misses
system.l2c.ReadReq_misses::total 34940 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 4674 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 3622 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 452 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1019 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 71101 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 76239 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 147340 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7942 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 82419 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 7342 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 84540 # number of demand (read+write) misses
system.l2c.demand_misses::total 182280 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu0.inst 7942 # number of overall misses
system.l2c.overall_misses::cpu0.data 82419 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu1.inst 7342 # number of overall misses
system.l2c.overall_misses::cpu1.data 84540 # number of overall misses
system.l2c.overall_misses::total 182280 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 520000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 208500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 414166000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 589465000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 940000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 260000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 383790500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 432860500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1822210500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 30607000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 30466000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 61073000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4060000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5045000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 9105000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 3700498000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3973370000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7673868000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 520000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 208500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 414166000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 4289963000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 940000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 260000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 383790500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4406230500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 9496078500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 520000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 208500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 414166000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 4289963000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 940000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 260000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 383790500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4406230500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 9496078500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4107 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1767 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 407292 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 217184 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5698 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 453535 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 149081 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1240618 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 577354 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 577354 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 5863 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4171 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 10034 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 790 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 645 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1435 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 124928 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 125944 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 250872 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 4107 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 1767 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 407292 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 342112 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 5698 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 453535 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 275025 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1491490 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 4107 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 1767 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 407292 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 342112 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 5698 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 453535 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 275025 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1491490 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002264 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.019500 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.052112 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.240912 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.240912 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52082.081640 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average ReadReq miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.writebacks::writebacks 110181 # number of writebacks
system.l2c.writebacks::total 110181 # number of writebacks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 7941 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 11318 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 5 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 7342 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 8301 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 34939 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 4674 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 3622 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 8296 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 567 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 452 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1019 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 71101 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 76239 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 147340 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 7941 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 82419 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 5 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 7342 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 84540 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 182279 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 7941 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 82419 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 5 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 7342 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 84540 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 182279 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 318844000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 453649000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 724000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 200000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 295681000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 333248000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1402906000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 187154000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 145115000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 332269000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22686000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18114000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 40800000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2847286000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3058502000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5905788000 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 318844000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 3300935000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 724000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 295681000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3391750000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 7308694000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 318844000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 3300935000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 724000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 200000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 295681000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3391750000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 7308694000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9316699500 # number of ReadReq MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122238098500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131824279000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 699595000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30626242500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 31325837500 # number of WriteReq MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10016294500 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152864341000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 163150116500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.052112 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40082.081640 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average ReadReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.dtb.read_hits 7070142 # DTB read hits
system.cpu0.dtb.read_misses 3739 # DTB read misses
system.cpu0.dtb.write_hits 5655287 # DTB write hits
system.cpu0.dtb.write_misses 802 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 7073881 # DTB read accesses
system.cpu0.dtb.write_accesses 5656089 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.dtb.hits 12725429 # DTB hits
system.cpu0.dtb.misses 4541 # DTB misses
system.cpu0.dtb.accesses 12729970 # DTB accesses
system.cpu0.itb.inst_hits 29439632 # ITB inst hits
system.cpu0.itb.inst_misses 2205 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses
system.cpu0.itb.hits 29439632 # DTB hits
system.cpu0.itb.misses 2205 # DTB misses
system.cpu0.itb.accesses 29441837 # DTB accesses
system.cpu0.numCycles 2339414086 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.committedInsts 28747266 # Number of instructions committed
system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
system.cpu0.num_func_calls 1116936 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls
system.cpu0.num_int_insts 33031535 # number of integer instructions
system.cpu0.num_fp_insts 3860 # number of float instructions
system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read
system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
system.cpu0.num_mem_refs 13393398 # number of memory refs
system.cpu0.num_load_insts 7407664 # Number of load instructions
system.cpu0.num_store_insts 5985734 # Number of store instructions
system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles
system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles
system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed
system.cpu0.icache.replacements 408172 # number of replacements
system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use
system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits
system.cpu0.icache.overall_hits::total 29030930 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses
system.cpu0.icache.overall_misses::total 408685 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.icache.writebacks::writebacks 16458 # number of writebacks
system.cpu0.icache.writebacks::total 16458 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408685 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 408685 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 408685 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 408685 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 408685 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 408685 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4832163500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4832163500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4832163500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4832163500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.dcache.replacements 335831 # number of replacements
system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use
system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6596660 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5349249 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5349249 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147717 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 147717 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149695 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 149695 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11945909 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 11945909 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11945909 # number of overall hits
system.cpu0.dcache.overall_hits::total 11945909 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 231189 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 231189 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 142616 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 142616 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9505 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9505 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 373805 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 373805 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 373805 # number of overall misses
system.cpu0.dcache.overall_misses::total 373805 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3541904000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 3541904000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5075999000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 5075999000 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104931000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 104931000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68264000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 68264000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 8617903000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 8617903000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 8617903000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 8617903000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827849 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6827849 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491865 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5491865 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157222 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 157222 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157159 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 157159 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12319714 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12319714 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks
system.cpu0.dcache.writebacks::total 287163 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 373805 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 373805 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 373805 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2848236000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2848236000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4648049500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4648049500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 76416000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45881000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45881000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.dtb.read_hits 8313009 # DTB read hits
system.cpu1.dtb.read_misses 3663 # DTB read misses
system.cpu1.dtb.write_hits 5829499 # DTB write hits
system.cpu1.dtb.write_misses 1439 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 8316672 # DTB read accesses
system.cpu1.dtb.write_accesses 5830938 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.dtb.hits 14142508 # DTB hits
system.cpu1.dtb.misses 5102 # DTB misses
system.cpu1.dtb.accesses 14147610 # DTB accesses
system.cpu1.itb.inst_hits 32286240 # ITB inst hits
system.cpu1.itb.inst_misses 2171 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses
system.cpu1.itb.hits 32286240 # DTB hits
system.cpu1.itb.misses 2171 # DTB misses
system.cpu1.itb.accesses 32288411 # DTB accesses
system.cpu1.numCycles 2338003468 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.committedInsts 31682438 # Number of instructions committed
system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
system.cpu1.num_func_calls 909270 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls
system.cpu1.num_int_insts 36868206 # number of integer instructions
system.cpu1.num_fp_insts 6793 # number of float instructions
system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read
system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
system.cpu1.num_mem_refs 14680299 # number of memory refs
system.cpu1.num_load_insts 8634860 # Number of load instructions
system.cpu1.num_store_insts 6045439 # Number of store instructions
system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles
system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles
system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed
system.cpu1.icache.replacements 454317 # number of replacements
system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use
system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits
system.cpu1.icache.overall_hits::total 31831407 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses
system.cpu1.icache.overall_misses::total 454829 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.icache.writebacks::writebacks 19149 # number of writebacks
system.cpu1.icache.writebacks::total 19149 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454829 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 454829 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 454829 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 454829 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 454829 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 454829 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5314262500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5314262500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5314262500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.dcache.replacements 294642 # number of replacements
system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use
system.cpu1.dcache.total_refs 11964721 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 295088 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 40.546281 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 89831748000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 457.752328 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.894048 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.894048 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 6946891 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 6946891 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4828705 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4828705 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81776 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 81776 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 83111 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 83111 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 11775596 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 11775596 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 11775596 # number of overall hits
system.cpu1.dcache.overall_hits::total 11775596 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 172105 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 172105 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 150416 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 150416 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11123 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11123 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9715 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 9715 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 322521 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 322521 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 322521 # number of overall misses
system.cpu1.dcache.overall_misses::total 322521 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2496186500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2496186500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5287724000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 5287724000 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124574500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 124574500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 73632000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 73632000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 7783910500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 7783910500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 7783910500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 7783910500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118996 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 7118996 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979121 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 4979121 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92899 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 92899 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92826 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 92826 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 12098117 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 12098117 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks
system.cpu1.dcache.writebacks::total 254584 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 322521 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91205500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91205500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44502000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44502000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6816193500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 6816193500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6816193500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_refs nan # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
ARM: update stats for clock frequency fix.
2012-05-11 01:04:29 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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