gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.868578                       # Number of seconds simulated
sim_ticks                                2868577613500                       # Number of ticks simulated
final_tick                               2868577613500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 558438                       # Simulator instruction rate (inst/s)
host_op_rate                                   675477                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            12195118142                       # Simulator tick rate (ticks/s)
host_mem_usage                                 590596                       # Number of bytes of host memory used
host_seconds                                   235.22                       # Real time elapsed on the host
sim_insts                                   131357672                       # Number of instructions simulated
sim_ops                                     158887964                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1167908                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1250980                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8365696                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           137236                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           508432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       356544                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11788332                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1167908                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       137236                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1305144                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8293056                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8310620                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26702                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20066                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       130714                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2299                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              7964                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         5571                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                193340                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          129579                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               133970                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           134                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              407138                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              436098                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2916322                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               47841                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              177242                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       124293                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              335                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4109469                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         407138                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          47841                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             454979                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2890999                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6109                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2897122                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2890999                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          134                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             407138                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             442207                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2916322                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              47841                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             177256                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       124293                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             335                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7006592                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        193340                       # Number of read requests accepted
system.physmem.writeReqs                       170194                       # Number of write requests accepted
system.physmem.readBursts                      193340                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     170194                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12365312                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8448                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9398080                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11788332                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10628956                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      132                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   23320                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          12970                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11741                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11572                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11914                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12194                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20279                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11715                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11292                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11716                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11966                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12328                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11336                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10554                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10992                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11462                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10907                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11240                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9545                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9662                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9792                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9578                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8974                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9217                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9112                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9138                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9280                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9864                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9143                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8671                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8940                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8704                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8686                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8539                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          53                       # Number of times write queue was full causing retry
system.physmem.totGap                    2868577154000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9731                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  183581                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 165803                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    135144                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     15528                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      9961                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8501                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6878                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5365                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4499                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3767                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3282                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       82                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       47                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5829                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6545                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7847                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7656                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7408                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10358                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1472                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1047                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2370                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     2465                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1828                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     2038                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      985                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      718                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      373                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       90                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        83936                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      259.284788                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     144.169379                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     318.901486                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          42814     51.01%     51.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16839     20.06%     71.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5671      6.76%     77.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3554      4.23%     82.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2350      2.80%     84.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1452      1.73%     86.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1048      1.25%     87.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          956      1.14%     88.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9252     11.02%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          83936                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6009                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        32.152937                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      562.980980                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6006     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.03%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6009                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6009                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        24.437510                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.815074                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       42.361816                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            5653     94.08%     94.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              88      1.46%     95.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              21      0.35%     95.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              11      0.18%     96.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95              30      0.50%     96.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111             35      0.58%     97.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127            32      0.53%     97.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            15      0.25%     97.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            11      0.18%     98.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175             9      0.15%     98.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            22      0.37%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            19      0.32%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223             8      0.13%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             2      0.03%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             4      0.07%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             3      0.05%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             3      0.05%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             2      0.03%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             5      0.08%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             5      0.08%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             6      0.10%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367             6      0.10%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             1      0.02%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             2      0.03%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431             1      0.02%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::432-447             2      0.03%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             1      0.02%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             4      0.07%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             2      0.03%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             2      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::656-671             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::688-703             2      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::736-751             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6009                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4585121898                       # Total ticks spent queuing
system.physmem.totMemAccLat                8207771898                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    966040000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       23731.53                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  42481.53                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.28                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.11                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.71                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.78                       # Average write queue length when enqueuing
system.physmem.readRowHits                     161661                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94455                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.67                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  64.31                       # Row buffer hit rate for writes
system.physmem.avgGap                      7890808.44                       # Average gap between requests
system.physmem.pageHitRate                      75.31                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  329026320                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  179528250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 798891600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                486116640                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           187361132400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            84057386715                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1647408374250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1920620456175                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.538978                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2740481725360                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95787900000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32307893640                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  305529840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  166707750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 708123000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                465438960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           187361132400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            82818901260                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1648494765000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1920320598210                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.434445                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2742293590423                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95787900000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     30490063327                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     7618                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                7618                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1341                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6277                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         7618                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           7618    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         7618                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6224                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean  9157.575514                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  8041.236075                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  5531.388532                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6077     97.64%     97.64% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          137      2.20%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151            6      0.10%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535            1      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            2      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6224                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1121059000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1121059000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1121059000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         4922     79.08%     79.08% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1302     20.92%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6224                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7618                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7618                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6224                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6224                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        13842                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25125547                       # DTB read hits
system.cpu0.dtb.read_misses                      6527                       # DTB read misses
system.cpu0.dtb.write_hits                   18731781                       # DTB write hits
system.cpu0.dtb.write_misses                     1091                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3404                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1741                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                25132074                       # DTB read accesses
system.cpu0.dtb.write_accesses               18732872                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         43857328                       # DTB hits
system.cpu0.dtb.misses                           7618                       # DTB misses
system.cpu0.dtb.accesses                     43864946                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3348                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3348                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          298                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3050                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3348                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3348    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3348                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2332                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean  9422.169811                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  8126.335555                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5925.919906                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          980     42.02%     42.02% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1299     55.70%     97.73% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575            3      0.13%     97.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           45      1.93%     99.79% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            3      0.13%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::114688-122879            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2332                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1120687000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1120687000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1120687000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2034     87.22%     87.22% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          298     12.78%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2332                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3348                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3348                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2332                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2332                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5680                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   118901491                       # ITB inst hits
system.cpu0.itb.inst_misses                      3348                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2150                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               118904839                       # ITB inst accesses
system.cpu0.itb.hits                        118901491                       # DTB hits
system.cpu0.itb.misses                           3348                       # DTB misses
system.cpu0.itb.accesses                    118904839                       # DTB accesses
system.cpu0.numCycles                      5737155227                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  115236645                       # Number of instructions committed
system.cpu0.committedOps                    139243080                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            123236123                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  9820                       # Number of float alu accesses
system.cpu0.num_func_calls                   12671679                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     15683932                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   123236123                       # number of integer instructions
system.cpu0.num_fp_insts                         9820                       # number of float instructions
system.cpu0.num_int_register_reads          226877119                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          85629478                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                7560                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           504430555                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           52228186                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     44991026                       # number of memory refs
system.cpu0.num_load_insts                   25375377                       # Number of load instructions
system.cpu0.num_store_insts                  19615649                       # Number of store instructions
system.cpu0.num_idle_cycles              5465784255.910094                       # Number of idle cycles
system.cpu0.num_busy_cycles              271370971.089905                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.047301                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.952699                       # Percentage of idle cycles
system.cpu0.Branches                         29094451                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 97895605     68.46%     68.46% # Class of executed instruction
system.cpu0.op_class::IntMult                  108367      0.08%     68.53% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              8067      0.01%     68.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.54% # Class of executed instruction
system.cpu0.op_class::MemRead                25375377     17.74%     86.28% # Class of executed instruction
system.cpu0.op_class::MemWrite               19615649     13.72%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 143005338                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1891                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements           691902                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          493.788529                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42987184                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           692414                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            62.083066                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1147014500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.788529                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.964431                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.964431                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88350780                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88350780                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     23864345                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23864345                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     18002045                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18002045                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       319294                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       319294                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365178                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       365178                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       362317                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       362317                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     41866390                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41866390                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     42185684                       # number of overall hits
system.cpu0.dcache.overall_hits::total       42185684                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       396651                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       396651                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       323350                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       323350                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       127092                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       127092                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21763                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21763                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19681                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19681                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       720001                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        720001                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       847093                       # number of overall misses
system.cpu0.dcache.overall_misses::total       847093                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5048891005                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5048891005                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5105410053                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   5105410053                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    330377500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    330377500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    436252524                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    436252524                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1279500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1279500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  10154301058                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  10154301058                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  10154301058                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  10154301058                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     24260996                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     24260996                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     18325395                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     18325395                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446386                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       446386                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386941                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       386941                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381998                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381998                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     42586391                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     42586391                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     43032777                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     43032777                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016349                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.016349                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017645                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017645                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.284713                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.284713                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056244                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056244                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051521                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051521                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016907                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.016907                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019685                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.019685                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12728.799385                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12728.799385                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15789.114127                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15789.114127                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15180.696595                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15180.696595                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22166.176719                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22166.176719                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14103.176326                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14103.176326                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11987.232875                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 11987.232875                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       505765                       # number of writebacks
system.cpu0.dcache.writebacks::total           505765                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25164                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25164                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15036                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15036                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25164                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25164                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25164                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25164                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       371487                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       371487                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       323350                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       323350                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100065                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       100065                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6727                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6727                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19681                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19681                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       694837                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       694837                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       794902                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       794902                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31775                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31775                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28452                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28452                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60227                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60227                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4098614569                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4098614569                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4609386947                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4609386947                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1545410442                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1545410442                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97646500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97646500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    406311476                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    406311476                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1224000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1224000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8708001516                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   8708001516                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10253411958                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10253411958                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6180823750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6180823750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4817819000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4817819000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10998642750                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10998642750                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015312                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015312                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017645                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017645                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224167                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224167                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017385                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017385                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051521                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051521                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016316                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016316                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018472                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018472                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11032.995957                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11032.995957                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14255.101120                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14255.101120                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15444.065777                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15444.065777                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14515.608741                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14515.608741                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20644.859306                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20644.859306                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12532.437847                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12532.437847                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12898.963593                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12898.963593                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194518.450039                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194518.450039                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169331.470547                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169331.470547                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182619.800920                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182619.800920                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1099684                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.454126                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          117801286                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1100196                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           107.073000                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      13491746250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.454126                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998934                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998934                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        238903187                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       238903187                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    117801286                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      117801286                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    117801286                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       117801286                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    117801286                       # number of overall hits
system.cpu0.icache.overall_hits::total      117801286                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1100205                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1100205                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1100205                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1100205                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1100205                       # number of overall misses
system.cpu0.icache.overall_misses::total      1100205                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10864366523                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10864366523                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10864366523                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10864366523                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10864366523                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10864366523                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    118901491                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    118901491                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    118901491                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    118901491                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    118901491                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    118901491                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009253                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.009253                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009253                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.009253                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009253                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.009253                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9874.856525                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9874.856525                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9874.856525                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9874.856525                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9874.856525                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9874.856525                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1100205                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1100205                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1100205                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1100205                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1100205                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1100205                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9757723477                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   9757723477                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9757723477                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   9757723477                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9757723477                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   9757723477                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    802157500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    802157500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    802157500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    802157500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009253                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009253                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009253                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009253                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009253                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009253                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8869.004846                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8869.004846                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8869.004846                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8869.004846                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8869.004846                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8869.004846                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88911.272445                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88911.272445                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88911.272445                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88911.272445                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1850277                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1850277                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       235795                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          266928                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16114.496747                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           1972101                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          283159                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.964642                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7721.313532                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.317590                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.113534                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4537.329831                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1964.577716                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1889.844545                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.471272                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000080                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000007                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.276937                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.119908                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.115347                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.983551                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1123                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15100                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          269                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          368                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          474                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3254                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7638                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4052                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.068542                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.921631                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        39669375                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       39669375                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7528                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3363                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1053127                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       384165                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       1448183                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       505760                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       505760                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28149                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28149                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1715                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1715                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       225012                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       225012                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7528                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3363                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1053127                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       609177                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1673195                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7528                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3363                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1053127                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       609177                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1673195                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          209                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          123                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        47078                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data        94114                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total       141524                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26175                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        26175                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        17961                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        17961                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44014                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        44014                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          209                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          123                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        47078                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       138128                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       185538                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          209                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          123                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        47078                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       138128                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       185538                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      4805250                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2807500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2358005477                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2765454494                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   5131072721                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    482009840                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    482009840                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    365934287                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    365934287                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1185998                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1185998                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   1958932743                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   1958932743                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      4805250                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2807500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2358005477                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   4724387237                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   7090005464                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      4805250                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2807500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2358005477                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   4724387237                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   7090005464                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         7737                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3486                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1100205                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       478279                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      1589707                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       505760                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       505760                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        54324                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        54324                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19676                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19676                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269026                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269026                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         7737                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3486                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1100205                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       747305                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1858733                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         7737                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3486                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1100205                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       747305                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1858733                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.027013                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.035284                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.042790                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.196776                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.089025                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.481831                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.481831                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.912838                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.912838                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.163605                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.163605                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.027013                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.035284                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042790                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.184835                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.099820                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.027013                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.035284                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042790                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.184835                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.099820                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22991.626794                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22825.203252                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 50087.205850                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29384.092632                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36255.848626                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18414.893601                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18414.893601                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20373.825901                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20373.825901                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 237199.600000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 237199.600000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44507.037374                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 44507.037374                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22991.626794                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22825.203252                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 50087.205850                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34202.965633                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 38213.225668                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22991.626794                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22825.203252                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 50087.205850                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34202.965633                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 38213.225668                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       194963                       # number of writebacks
system.cpu0.l2cache.writebacks::total          194963                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data           34                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total           34                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1200                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1200                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1234                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1234                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1234                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1234                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          209                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          123                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        47078                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        94080                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total       141490                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       245498                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       245498                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26175                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26175                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        17961                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        17961                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42814                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        42814                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          209                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          123                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        47078                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       136894                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       184304                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          209                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          123                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        47078                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       136894                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       245498                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       429802                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31775                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40797                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28452                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28452                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60227                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69249                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3446250                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2008000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2045556523                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   2147080077                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   4198090850                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13523341666                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13523341666                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    511152796                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    511152796                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    258980524                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    258980524                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       945498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       945498                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1561585422                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1561585422                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3446250                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2008000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2045556523                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3708665499                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   5759676272                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3446250                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2008000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2045556523                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3708665499                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13523341666                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  19283017938                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    730253500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5926417500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6656671000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4604429000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4604429000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    730253500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10530846500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11261100000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.027013                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.035284                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.042790                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.196705                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.089004                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.481831                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.481831                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.912838                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.912838                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.159144                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.159144                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.027013                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.035284                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042790                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.183184                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.099156                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.027013                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.035284                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042790                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.183184                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.231234                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43450.370088                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22821.854560                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29670.583433                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55085.343530                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19528.282560                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19528.282560                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14419.048160                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14419.048160                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 189099.600000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 189099.600000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36473.710048                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36473.710048                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43450.370088                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27091.512404                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31250.956420                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43450.370088                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27091.512404                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44864.886478                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186511.959087                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163165.698458                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161831.470547                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161831.470547                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 174852.582729                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 162617.510722                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       1738254                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1687491                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        30889                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28452                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       505760                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       309559                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36266                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        88185                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42256                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       111549                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           50                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       297072                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       284592                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2218454                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2369943                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         9884                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        21632                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          4619913                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     70449208                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     84455860                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13944                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        30948                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         154949960                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     641653                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      3048291                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.181009                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.385025                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           2496524     81.90%     81.90% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2            551767     18.10%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3048291                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    1778395498                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    114075998                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1664668023                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1210905566                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      6398000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     13895250                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     3295                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                3295                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          601                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2694                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         3295                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           3295    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         3295                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2525                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean  9355.742574                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  8433.023249                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5123.717679                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191          905     35.84%     35.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1497     59.29%     95.13% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575           62      2.46%     97.58% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767           54      2.14%     99.72% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959            2      0.08%     99.80% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151            4      0.16%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2525                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1642630968                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1642630968    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1642630968                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1932     76.51%     76.51% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          593     23.49%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2525                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3295                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3295                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2525                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2525                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         5820                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3921520                       # DTB read hits
system.cpu1.dtb.read_misses                      2787                       # DTB read misses
system.cpu1.dtb.write_hits                    3403460                       # DTB write hits
system.cpu1.dtb.write_misses                      508                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2006                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   344                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3924307                       # DTB read accesses
system.cpu1.dtb.write_accesses                3403968                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          7324980                       # DTB hits
system.cpu1.dtb.misses                           3295                       # DTB misses
system.cpu1.dtb.accesses                      7328275                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1740                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1740                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          164                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1576                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1740                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1740    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1740                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1101                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean  9831.970936                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  8728.225186                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5541.612386                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095          184     16.71%     16.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          162     14.71%     31.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          497     45.14%     76.57% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          204     18.53%     95.10% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479            1      0.09%     95.19% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.09%     95.28% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           28      2.54%     97.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           19      1.73%     99.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            3      0.27%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            2      0.18%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1101                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1642083968                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1642083968    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1642083968                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          937     85.10%     85.10% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          164     14.90%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1101                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1740                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1740                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1101                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1101                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2841                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    16475856                       # ITB inst hits
system.cpu1.itb.inst_misses                      1740                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1142                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                16477596                       # ITB inst accesses
system.cpu1.itb.hits                         16475856                       # DTB hits
system.cpu1.itb.misses                           1740                       # DTB misses
system.cpu1.itb.accesses                     16477596                       # DTB accesses
system.cpu1.numCycles                      5736236800                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   16121027                       # Number of instructions committed
system.cpu1.committedOps                     19644884                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             17715670                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1857                       # Number of float alu accesses
system.cpu1.num_func_calls                    1024357                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1805296                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    17715670                       # number of integer instructions
system.cpu1.num_fp_insts                         1857                       # number of float instructions
system.cpu1.num_int_register_reads           32157611                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          12423544                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1341                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            71811842                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            6390929                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      7557236                       # number of memory refs
system.cpu1.num_load_insts                    4032278                       # Number of load instructions
system.cpu1.num_store_insts                   3524958                       # Number of store instructions
system.cpu1.num_idle_cycles              5685648636.968273                       # Number of idle cycles
system.cpu1.num_busy_cycles              50588163.031727                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.008819                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.991181                       # Percentage of idle cycles
system.cpu1.Branches                          2908306                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 12407832     62.06%     62.06% # Class of executed instruction
system.cpu1.op_class::IntMult                   25890      0.13%     62.19% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3309      0.02%     62.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.20% # Class of executed instruction
system.cpu1.op_class::MemRead                 4032278     20.17%     82.37% # Class of executed instruction
system.cpu1.op_class::MemWrite                3524958     17.63%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  19994333                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2782                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements           185399                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          466.419324                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            7065195                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           185751                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            38.035838                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     104846956000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   466.419324                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.910975                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.910975                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          352                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          268                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           84                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         14867676                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        14867676                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3611065                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3611065                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3216741                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3216741                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48524                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        48524                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78212                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        78212                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70143                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        70143                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      6827806                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         6827806                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      6876330                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6876330                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       133141                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       133141                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        90456                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        90456                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30283                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30283                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17238                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17238                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23491                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23491                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       223597                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        223597                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       253880                       # number of overall misses
system.cpu1.dcache.overall_misses::total       253880                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1928381738                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1928381738                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2296114353                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2296114353                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    319996750                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    319996750                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    553086757                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    553086757                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2433500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2433500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4224496091                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4224496091                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4224496091                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4224496091                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3744206                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3744206                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      3307197                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3307197                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        78807                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        78807                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        95450                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        95450                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        93634                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        93634                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      7051403                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      7051403                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      7130210                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      7130210                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035559                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035559                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027351                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.027351                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.384268                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.384268                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.180597                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.180597                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.250881                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.250881                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031710                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031710                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035606                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035606                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14483.755853                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14483.755853                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25383.770596                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25383.770596                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18563.449936                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18563.449936                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23544.623771                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23544.623771                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18893.348708                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18893.348708                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16639.735666                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16639.735666                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       114520                       # number of writebacks
system.cpu1.dcache.writebacks::total           114520                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          275                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          275                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12066                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12066                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          275                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          275                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          275                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          275                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       132866                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       132866                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        90456                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        90456                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29572                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        29572                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5172                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5172                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23491                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23491                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       223322                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       223322                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       252894                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       252894                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3084                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3084                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2437                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2437                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5521                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5521                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1717533750                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1717533750                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2155103647                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2155103647                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    472304765                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    472304765                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     84734500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     84734500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    516677243                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    516677243                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2366000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2366000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3872637397                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   3872637397                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4344942162                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4344942162                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    406850750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    406850750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    279944500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    279944500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    686795250                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    686795250                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035486                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035486                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027351                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027351                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.375246                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.375246                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054185                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054185                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.250881                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.250881                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031671                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031671                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035468                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035468                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12926.811600                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12926.811600                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23824.883336                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23824.883336                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15971.350095                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15971.350095                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.313998                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.313998                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.689158                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.689158                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17341.047443                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17341.047443                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17180.882749                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17180.882749                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131923.070687                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131923.070687                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114872.589249                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114872.589249                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124396.893679                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124396.893679                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           502966                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.575795                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           15972373                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           503478                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            31.724073                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      84694032500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.575795                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973781                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973781                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          388                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          121                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         33455180                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        33455180                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     15972373                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       15972373                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     15972373                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        15972373                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     15972373                       # number of overall hits
system.cpu1.icache.overall_hits::total       15972373                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       503478                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       503478                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       503478                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        503478                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       503478                       # number of overall misses
system.cpu1.icache.overall_misses::total       503478                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4406075262                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4406075262                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4406075262                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4406075262                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4406075262                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4406075262                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     16475851                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     16475851                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     16475851                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     16475851                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     16475851                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     16475851                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030559                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.030559                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030559                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.030559                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030559                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.030559                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8751.276644                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8751.276644                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8751.276644                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8751.276644                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8751.276644                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8751.276644                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       503478                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       503478                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       503478                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       503478                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       503478                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       503478                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3901799738                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3901799738                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3901799738                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3901799738                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3901799738                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3901799738                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15252750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15252750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15252750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     15252750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030559                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030559                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030559                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.030559                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030559                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.030559                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7749.692614                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7749.692614                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7749.692614                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  7749.692614                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7749.692614                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  7749.692614                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86173.728814                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86173.728814                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       195194                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       195194                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        57534                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           39835                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       14698.947760                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            703731                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           54406                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           12.934805                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  8839.546228                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     2.119643                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.076473                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3192.274029                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1936.419828                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   726.511560                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.539523                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000129                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.194841                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.118190                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.044343                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.897153                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1124                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13429                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           25                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1096                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          296                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1612                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        11521                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.068604                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001099                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.819641                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        14679345                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       14679345                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3122                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1719                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       490518                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       100742                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        596101                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       114520                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       114520                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1111                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1111                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          866                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          866                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27369                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27369                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3122                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1719                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       490518                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       128111                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         623470                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3122                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1719                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       490518                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       128111                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        623470                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          318                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          267                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst        12960                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        66868                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        80413                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        27915                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        27915                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22615                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22615                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           10                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total           10                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34061                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34061                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          318                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          267                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        12960                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       100929                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       114474                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          318                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          267                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        12960                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       100929                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       114474                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      6443750                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5338500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    460251238                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1451446014                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1923479502                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    535355877                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    535355877                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    456012560                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    456012560                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2321000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2321000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1258488445                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1258488445                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      6443750                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5338500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    460251238                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2709934459                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3181967947                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      6443750                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5338500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    460251238                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2709934459                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3181967947                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3440                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1986                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       503478                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       167610                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       676514                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       114520                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       114520                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29026                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29026                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23481                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23481                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           10                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           10                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        61430                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        61430                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3440                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1986                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       503478                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       229040                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       737944                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3440                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1986                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       503478                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       229040                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       737944                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.092442                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.134441                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.025741                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.398950                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.118864                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.961724                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.961724                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.963119                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.963119                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.554469                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.554469                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.092442                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.134441                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.025741                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.440661                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.155126                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.092442                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.134441                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.025741                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.440661                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.155126                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20263.364780                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19994.382022                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35513.212809                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21706.137674                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23920.006740                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19178.071897                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19178.071897                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20164.163608                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20164.163608                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       232100                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       232100                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36948.076833                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36948.076833                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20263.364780                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19994.382022                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35513.212809                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26849.908936                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 27796.424926                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20263.364780                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19994.382022                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35513.212809                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26849.908936                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 27796.424926                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        25678                       # number of writebacks
system.cpu1.l2cache.writebacks::total           25678                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           69                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total           69                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data           69                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total           69                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data           69                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total           69                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          318                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          267                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        12960                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        66868                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        80413                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        22290                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        22290                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        27915                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        27915                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22615                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22615                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           10                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33992                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        33992                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          318                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          267                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        12960                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       100860                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       114405                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          318                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          267                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        12960                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       100860                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        22290                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       136695                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3084                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3261                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2437                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2437                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5521                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5698                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4376250                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3603000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    375210762                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1016628986                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1399818998                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    742843274                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    742843274                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    439552298                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    439552298                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    340829757                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    340829757                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2028500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2028500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1027563755                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1027563755                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4376250                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3603000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    375210762                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2044192741                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2427382753                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4376250                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3603000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    375210762                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2044192741                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    742843274                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3170226027                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13847750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    382171500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    396019250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    261667000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    261667000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13847750                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    643838500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    657686250                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.092442                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.134441                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.025741                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.398950                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.118864                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.961724                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.961724                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.963119                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.963119                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.553345                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.553345                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.092442                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.134441                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.025741                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.440360                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.155032                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.092442                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.134441                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.025741                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.440360                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.185238                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28951.447685                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15203.520159                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17407.869349                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33326.302109                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15746.097009                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15746.097009                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15070.959850                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15070.959850                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       202850                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       202850                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30229.576224                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30229.576224                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28951.447685                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20267.625828                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21217.453372                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28951.447685                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20267.625828                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23191.967716                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 123920.719844                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 121441.045692                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107372.589249                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107372.589249                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116616.283282                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 115424.052299                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1060646                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       722071                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        30889                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2437                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       114520                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        27384                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36266                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        75380                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41410                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85537                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           47                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        84086                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        66129                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1007310                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       764894                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5302                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9429                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          1786935                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     32223300                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24770860                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7944                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13760                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          57015864                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     636167                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1470628                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.384445                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.486464                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            905253     61.56%     61.56% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2            565375     38.44%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1470628                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     573017999                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     81259000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    755831512                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    377529095                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3316000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      5989250                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              23198                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180874                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484068                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           199086925                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36785519                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36445                       # number of replacements
system.iocache.tags.tagsinuse               14.391068                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         288263513000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.391068                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.899442                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.899442                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
system.iocache.tags.data_accesses              328311                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          255                       # number of overall misses
system.iocache.overall_misses::total              255                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32671377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32671377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6655899029                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   6655899029                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     32671377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     32671377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     32671377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     32671377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128123.047059                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128123.047059                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183742.795633                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183742.795633                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128123.047059                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128123.047059                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128123.047059                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128123.047059                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         23173                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3543                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.540502                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     19404377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     19404377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4772213067                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4772213067                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     19404377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     19404377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     19404377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     19404377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76095.596078                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 76095.596078                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131741.747653                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131741.747653                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76095.596078                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76095.596078                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76095.596078                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76095.596078                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   122211                       # number of replacements
system.l2c.tags.tagsinuse                63914.238063                       # Cycle average of tags in use
system.l2c.tags.total_refs                     336222                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   186592                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     1.801910                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   11496.547602                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.049900                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.062133                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7182.549375                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2988.985612                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38830.864169                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.955834                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1379.188596                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      342.352201                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1689.682641                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.175423                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000047                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.109597                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.045608                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.592512                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.021045                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.005224                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.025783                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.975254                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        32922                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        31453                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          129                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4653                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        28140                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          241                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1916                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        29284                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.502350                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.479935                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  4784413                       # Number of tag accesses
system.l2c.tags.data_accesses                 4784413                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker           69                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker           62                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              29385                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              44972                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        45934                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker           27                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           29                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              10817                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data               7566                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher         4637                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 143498                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          220641                       # number of Writeback hits
system.l2c.Writeback_hits::total               220641                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            2604                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             702                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                3306                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           145                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           242                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               387                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4135                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1764                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5899                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker            69                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            62                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               29385                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               49107                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        45934                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            27                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            29                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               10817                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                9330                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         4637                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  149397                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker           69                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           62                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              29385                       # number of overall hits
system.l2c.overall_hits::cpu0.data              49107                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        45934                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           27                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           29                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              10817                       # number of overall hits
system.l2c.overall_hits::cpu1.data               9330                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         4637                       # number of overall hits
system.l2c.overall_hits::total                 149397                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            6                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            17693                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             8817                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       130884                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2143                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              691                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher         5571                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               165808                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          8462                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2686                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11148                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          478                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1247                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1725                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          10966                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7268                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              18234                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            6                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17693                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             19783                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       130884                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2143                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              7959                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         5571                       # number of demand (read+write) misses
system.l2c.demand_misses::total                184042                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            6                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17693                       # number of overall misses
system.l2c.overall_misses::cpu0.data            19783                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       130884                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2143                       # number of overall misses
system.l2c.overall_misses::cpu1.data             7959                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         5571                       # number of overall misses
system.l2c.overall_misses::total               184042                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       466750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       165000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   1430972014                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    766150824                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  12775683388                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        96750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    177373250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     73282238                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher    648312983                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    15872503197                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     11409175                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      2717413                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     14126588                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1225466                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       966969                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2192435                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data    964303159                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    590306733                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1554609892                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       466750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       165000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1430972014                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1730453983                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  12775683388                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        96750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    177373250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    663588971                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    648312983                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     17427113089                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       466750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       165000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1430972014                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1730453983                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  12775683388                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        96750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    177373250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    663588971                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    648312983                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    17427113089                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker           75                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker           64                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          47078                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          53789                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       176818                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker           28                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           29                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          12960                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data           8257                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        10208                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             309306                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       220641                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           220641                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        11066                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3388                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           14454                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          623                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1489                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2112                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15101                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9032                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24133                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker           75                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           64                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           47078                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           68890                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       176818                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           28                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           29                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           12960                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           17289                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        10208                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              333439                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker           75                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           64                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          47078                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          68890                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       176818                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           28                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           29                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          12960                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          17289                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        10208                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             333439                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.080000                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.031250                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.375823                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.163918                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.165355                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.083687                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.536065                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.764685                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.792798                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.771274                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.767255                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.837475                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.816761                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.726177                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.804694                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.755563                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.080000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.031250                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.375823                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.287168                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.165355                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.460351                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.551951                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.080000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.031250                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.375823                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.287168                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.165355                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.460351                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.551951                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77791.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        82500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80877.862092                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 86894.728819                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        96750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82768.665422                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 106052.442836                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 95728.210925                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1348.283503                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1011.695086                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1267.185863                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2563.736402                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   775.436247                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1270.976812                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87935.724877                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81219.968767                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 85258.851157                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77791.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80877.862092                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 87471.767831                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        96750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82768.665422                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 83375.922980                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 94690.956896                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77791.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        82500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80877.862092                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 87471.767831                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        96750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82768.665422                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 83375.922980                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 94690.956896                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               93389                       # number of writebacks
system.l2c.writebacks::total                    93389                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                15                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 15                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                15                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            6                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        17687                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         8817                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       130884                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         2134                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          691                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher         5571                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          165793                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8462                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2686                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11148                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          478                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1247                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1725                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        10966                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7268                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         18234                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17687                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        19783                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       130884                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2134                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         7959                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5571                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           184027                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17687                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        19783                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       130884                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2134                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         7959                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         5571                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          184027                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31775                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3080                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        44054                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28452                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2437                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30889                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60227                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5517                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        74943                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       391750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       140000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   1208996486                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    655819176                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11160223644                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        83750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    149987000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     64618762                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher    579886727                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  13820147295                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    151117443                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     47855180                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    198972623                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      8594976                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     22191743                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     30786719                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    828734841                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    499414267                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1328149108                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       391750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       140000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1208996486                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1484554017                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11160223644                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        83750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    149987000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    564033029                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    579886727                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  15148296403                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       391750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       140000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1208996486                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1484554017                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11160223644                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        83750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    149987000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    564033029                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    579886727                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  15148296403                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    549810500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5306043500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10310750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    321686500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6187851250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4077783000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    216378500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4294161500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    549810500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9383826500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10310750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    538065000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10482012750                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.080000                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.031250                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.375696                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.163918                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.164660                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.083687                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.536016                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.764685                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.792798                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.771274                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.767255                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.837475                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.816761                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.726177                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.804694                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.755563                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.080000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.031250                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.375696                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.287168                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.164660                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.460351                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.551906                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.080000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.031250                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.375696                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.287168                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740219                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.164660                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.460351                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.545748                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.551906                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68355.090518                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74381.215379                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        83750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70284.442362                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 93514.850941                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 83357.845597                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17858.360080                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17816.522710                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17848.279781                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17981.121339                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.105052                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17847.373333                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75573.120646                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68714.125894                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72839.152572                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68355.090518                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75041.905525                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        83750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70284.442362                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70867.323659                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 82315.618920                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        70000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68355.090518                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75041.905525                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        83750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70284.442362                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70867.323659                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 82315.618920                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166987.993706                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104443.668831                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 140460.599492                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143321.488823                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88788.879770                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 139019.116838                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155807.636110                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97528.548124                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 139866.468516                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              210102                       # Transaction distribution
system.membus.trans_dist::ReadResp             210102                       # Transaction distribution
system.membus.trans_dist::WriteReq              30889                       # Transaction distribution
system.membus.trans_dist::WriteResp             30889                       # Transaction distribution
system.membus.trans_dist::Writeback            129579                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            77022                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40122                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           12986                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq           33                       # Transaction distribution
system.membus.trans_dist::ReadExReq             38648                       # Transaction distribution
system.membus.trans_dist::ReadExResp            18121                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13636                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       639843                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       761429                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108908                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108908                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 870337                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27272                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17781832                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17971968                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22607424                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           125322                       # Total snoops (count)
system.membus.snoop_fanout::samples            562672                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  562672    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              562672                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88118500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11425000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1114763998                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1110191376                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           37521481                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             475433                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            475418                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30889                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30889                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           220641                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36266                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           80215                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         40509                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         120724                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           82                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50702                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50702                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1061225                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       262179                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1323404                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31467168                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4256160                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               35723328                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          289388                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           934737                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.039071                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.193764                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 898216     96.09%     96.09% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36521      3.91%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             934737                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          749457686                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           360000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         652203239                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         220037759                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------