2006-10-06 10:23:27 +02:00
---------- Begin Simulation Statistics ----------
2015-03-02 11:04:20 +01:00
sim_seconds 0.000025 # Number of seconds simulated
2015-09-15 15:14:09 +02:00
sim_ticks 24832500 # Number of ticks simulated
final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2006-10-06 10:23:27 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-11-16 12:08:57 +01:00
host_inst_rate 44040 # Simulator instruction rate (inst/s)
host_op_rate 44038 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 85804643 # Simulator tick rate (ticks/s)
host_mem_usage 292816 # Number of bytes of host memory used
host_seconds 0.29 # Real time elapsed on the host
2014-09-03 13:42:59 +02:00
sim_insts 12744 # Number of instructions simulated
sim_ops 12744 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-09-15 15:14:09 +02:00
system.physmem.bytes_read::cpu.inst 40448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 22016 # Number of bytes read from this memory
system.physmem.bytes_read::total 62464 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 40448 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 40448 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 632 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 344 # Number of read requests responded to by this memory
system.physmem.num_reads::total 976 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1628833182 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 886580087 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2515413269 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1628833182 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1628833182 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1628833182 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 886580087 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2515413269 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 976 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2015-09-15 15:14:09 +02:00
system.physmem.readBursts 976 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2015-09-15 15:14:09 +02:00
system.physmem.bytesReadDRAM 62464 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2015-09-15 15:14:09 +02:00
system.physmem.bytesReadSys 62464 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::0 84 # Per bank write bursts
system.physmem.perBankRdBursts::1 152 # Per bank write bursts
system.physmem.perBankRdBursts::2 78 # Per bank write bursts
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::3 59 # Per bank write bursts
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::4 88 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::5 48 # Per bank write bursts
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::6 33 # Per bank write bursts
system.physmem.perBankRdBursts::7 50 # Per bank write bursts
system.physmem.perBankRdBursts::8 42 # Per bank write bursts
system.physmem.perBankRdBursts::9 39 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::10 29 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::11 34 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::13 120 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::14 68 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::15 37 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-09-15 15:14:09 +02:00
system.physmem.totGap 24688000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-09-15 15:14:09 +02:00
system.physmem.readPktSize::6 976 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::0 340 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 321 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 209 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 280.184332 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 175.894103 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 284.655938 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 78 35.94% 35.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 61 28.11% 64.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 19 8.76% 72.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 11 5.07% 77.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 14 6.45% 84.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 13 5.99% 90.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4 1.84% 92.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 6 2.76% 94.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 5.07% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation
system.physmem.totQLat 12728500 # Total ticks spent queuing
system.physmem.totMemAccLat 31028500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4880000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13041.50 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-09-15 15:14:09 +02:00
system.physmem.avgMemAccLat 31791.50 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2515.41 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2015-09-15 15:14:09 +02:00
system.physmem.avgRdBWSys 2515.41 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-09-15 15:14:09 +02:00
system.physmem.busUtil 19.65 # Data bus utilization in percentage
system.physmem.busUtilRead 19.65 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-09-15 15:14:09 +02:00
system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2015-09-15 15:14:09 +02:00
system.physmem.readRowHits 749 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2015-09-15 15:14:09 +02:00
system.physmem.readRowHitRate 76.74 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2015-09-15 15:14:09 +02:00
system.physmem.avgGap 25295.08 # Average gap between requests
system.physmem.pageHitRate 76.74 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 892080 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 486750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4516200 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 23568270 # Total energy per rank (pJ)
system.physmem_0.averagePower 997.862715 # Core power per rank (mW)
2015-07-03 16:15:03 +02:00
system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.actEnergy 718200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 391875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2847000 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_1.actBackEnergy 15524235 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 557250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 21564240 # Total energy per rank (pJ)
system.physmem_1.averagePower 912.772063 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 830500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.memoryStateTime::ACT 22027750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.lookups 6978 # Number of BP lookups
system.cpu.branchPred.condPredicted 3979 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1366 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 5343 # Number of BTB lookups
system.cpu.branchPred.BTBHits 988 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.BTBHitPct 18.491484 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
2015-09-15 15:14:09 +02:00
system.cpu.dtb.read_hits 4756 # DTB read hits
system.cpu.dtb.read_misses 94 # DTB read misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
2015-09-15 15:14:09 +02:00
system.cpu.dtb.read_accesses 4850 # DTB read accesses
system.cpu.dtb.write_hits 2093 # DTB write hits
system.cpu.dtb.write_misses 69 # DTB write misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
2015-09-15 15:14:09 +02:00
system.cpu.dtb.write_accesses 2162 # DTB write accesses
system.cpu.dtb.data_hits 6849 # DTB hits
system.cpu.dtb.data_misses 163 # DTB misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
2015-09-15 15:14:09 +02:00
system.cpu.dtb.data_accesses 7012 # DTB accesses
system.cpu.itb.fetch_hits 5404 # ITB hits
system.cpu.itb.fetch_misses 57 # ITB misses
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
2015-09-15 15:14:09 +02:00
system.cpu.itb.fetch_accesses 5461 # ITB accesses
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
2015-09-15 15:14:09 +02:00
system.cpu.numCycles 49666 # number of cpu cycles simulated
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-15 15:14:09 +02:00
system.cpu.fetch.icacheStallCycles 1235 # Number of cycles fetch is stalled on an Icache miss
2015-09-25 13:27:03 +02:00
system.cpu.fetch.Insts 39551 # Number of instructions fetch has processed
2015-09-15 15:14:09 +02:00
system.cpu.fetch.Branches 6978 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2103 # Number of branches that fetch has predicted taken
2015-09-25 13:27:03 +02:00
system.cpu.fetch.Cycles 10833 # Number of cycles fetch has run and was not squashing or blocked
2015-09-15 15:14:09 +02:00
system.cpu.fetch.SquashCycles 1446 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 5404 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 838 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 27534 # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu.fetch.rateDist::mean 1.436442 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.801385 # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu.fetch.rateDist::0 20751 75.37% 75.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 584 2.12% 77.49% # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.rateDist::2 426 1.55% 79.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 584 2.12% 81.15% # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu.fetch.rateDist::4 571 2.07% 83.23% # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.rateDist::5 441 1.60% 84.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 491 1.78% 86.61% # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu.fetch.rateDist::7 560 2.03% 88.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 3126 11.35% 100.00% # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.rateDist::total 27534 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.140499 # Number of branch fetches per cycle
2015-09-25 13:27:03 +02:00
system.cpu.fetch.rate 0.796340 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 37297 # Number of cycles decode is idle
2015-09-15 15:14:09 +02:00
system.cpu.decode.BlockedCycles 10659 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 5112 # Number of cycles decode is running
2015-09-25 13:27:03 +02:00
system.cpu.decode.UnblockCycles 614 # Number of cycles decode is unblocking
2015-09-15 15:14:09 +02:00
system.cpu.decode.SquashCycles 1127 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 528 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 328 # Number of times decode detected a branch misprediction
2015-09-25 13:27:03 +02:00
system.cpu.decode.DecodedInsts 32206 # Number of instructions handled by decode
2015-09-15 15:14:09 +02:00
system.cpu.decode.SquashedInsts 725 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1127 # Number of cycles rename is squashing
2015-09-25 13:27:03 +02:00
system.cpu.rename.IdleCycles 37872 # Number of cycles rename is idle
2015-09-15 15:14:09 +02:00
system.cpu.rename.BlockCycles 4968 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1226 # count of cycles rename stalled for serializing inst
2015-09-25 13:27:03 +02:00
system.cpu.rename.RunCycles 5150 # Number of cycles rename is running
2015-09-15 15:14:09 +02:00
system.cpu.rename.UnblockCycles 4466 # Number of cycles rename is unblocking
2015-09-25 13:27:03 +02:00
system.cpu.rename.RenamedInsts 30281 # Number of instructions processed by rename
2015-09-15 15:14:09 +02:00
system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 324 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 847 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 3132 # Number of times rename has blocked due to SQ full
2015-09-25 13:27:03 +02:00
system.cpu.rename.RenamedOperands 22821 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 37713 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 37695 # Number of integer rename lookups
2013-10-16 16:44:12 +02:00
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
2012-08-15 16:38:05 +02:00
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
2015-09-25 13:27:03 +02:00
system.cpu.rename.UndoneMaps 13681 # Number of HB maps that are undone due to squashing
2015-09-15 15:14:09 +02:00
system.cpu.rename.serializingInsts 60 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2263 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1407 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
system.cpu.memDep1.insertedLoads 2862 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep1.insertedStores 1462 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep1.conflictingLoads 2 # Number of conflicting loads.
2014-09-03 13:42:59 +02:00
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
2015-09-15 15:14:09 +02:00
system.cpu.iq.iqInstsAdded 27015 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 22338 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 14320 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 8141 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 27534 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.811288 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.520707 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::0 19179 69.66% 69.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 2638 9.58% 79.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1919 6.97% 86.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1327 4.82% 91.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1227 4.46% 95.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 711 2.58% 98.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 354 1.29% 99.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 138 0.50% 99.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 41 0.15% 100.00% # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::total 27534 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-09-15 15:14:09 +02:00
system.cpu.iq.fu_full::IntAlu 32 9.64% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 217 65.36% 75.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 83 25.00% 100.00% # attempts to use FU when none available
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::IntAlu 7321 66.01% 66.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2641 23.81% 89.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1123 10.13% 100.00% # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::total 11090 # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_1::IntAlu 7446 66.20% 66.22% # Type of FU issued
system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.23% # Type of FU issued
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.23% # Type of FU issued
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.24% # Type of FU issued
system.cpu.iq.FU_type_1::MemRead 2645 23.52% 89.76% # Type of FU issued
system.cpu.iq.FU_type_1::MemWrite 1152 10.24% 100.00% # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_1::total 11248 # Type of FU issued
system.cpu.iq.FU_type::total 22338 0.00% 0.00% # Type of FU issued
system.cpu.iq.rate 0.449764 # Inst issue rate
system.cpu.iq.fu_busy_cnt::0 166 # FU busy when requested
system.cpu.iq.fu_busy_cnt::1 166 # FU busy when requested
system.cpu.iq.fu_busy_cnt::total 332 # FU busy when requested
system.cpu.iq.fu_busy_rate::0 0.007431 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::1 0.007431 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total 0.014863 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 72630 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 41400 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19613 # Number of integer instruction queue wakeup accesses
2013-05-30 18:54:18 +02:00
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
2015-09-15 15:14:09 +02:00
system.cpu.iq.int_alu_accesses 22644 # Number of integer alu accesses
2013-05-30 18:54:18 +02:00
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1651 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 542 # Number of stores squashed
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2012-10-30 14:35:32 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 309 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread1.forwLoads 73 # Number of loads that had data forwarded from stores
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread1.squashedLoads 1679 # Number of loads squashed
system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations
system.cpu.iew.lsq.thread1.squashedStores 597 # Number of stores squashed
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread1.cacheBlocked 327 # Number of times an access to memory failed due to the cache being blocked
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-09-15 15:14:09 +02:00
system.cpu.iew.iewSquashCycles 1127 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 614 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 27211 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 237 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 5696 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2869 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 589 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 160 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 21052 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0 2447 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::1 2411 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::total 4858 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1286 # Number of squashed instructions skipped in execute
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
2015-07-03 16:15:03 +02:00
system.cpu.iew.exec_nop::0 74 # number of nop insts executed
2015-09-15 15:14:09 +02:00
system.cpu.iew.exec_nop::1 72 # number of nop insts executed
system.cpu.iew.exec_nop::total 146 # number of nop insts executed
system.cpu.iew.exec_refs::0 3514 # number of memory reference insts executed
system.cpu.iew.exec_refs::1 3522 # number of memory reference insts executed
system.cpu.iew.exec_refs::total 7036 # number of memory reference insts executed
system.cpu.iew.exec_branches::0 1644 # Number of branches executed
system.cpu.iew.exec_branches::1 1639 # Number of branches executed
system.cpu.iew.exec_branches::total 3283 # Number of branches executed
system.cpu.iew.exec_stores::0 1067 # Number of stores executed
system.cpu.iew.exec_stores::1 1111 # Number of stores executed
system.cpu.iew.exec_stores::total 2178 # Number of stores executed
system.cpu.iew.exec_rate 0.423871 # Inst execution rate
system.cpu.iew.wb_sent::0 9939 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::1 10068 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::total 20007 # cumulative count of insts sent to commit
system.cpu.iew.wb_count::0 9740 # cumulative count of insts written-back
system.cpu.iew.wb_count::1 9893 # cumulative count of insts written-back
system.cpu.iew.wb_count::total 19633 # cumulative count of insts written-back
system.cpu.iew.wb_producers::0 5189 # num instructions producing a value
system.cpu.iew.wb_producers::1 5256 # num instructions producing a value
system.cpu.iew.wb_producers::total 10445 # num instructions producing a value
system.cpu.iew.wb_consumers::0 6868 # num instructions consuming a value
system.cpu.iew.wb_consumers::1 6926 # num instructions consuming a value
system.cpu.iew.wb_consumers::total 13794 # num instructions consuming a value
system.cpu.iew.wb_rate::0 0.196110 # insts written-back per cycle
system.cpu.iew.wb_rate::1 0.199191 # insts written-back per cycle
system.cpu.iew.wb_rate::total 0.395301 # insts written-back per cycle
system.cpu.iew.wb_fanout::0 0.755533 # average fanout of values written-back
system.cpu.iew.wb_fanout::1 0.758880 # average fanout of values written-back
system.cpu.iew.wb_fanout::total 0.757213 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 14447 # The number of squashed insts skipped by commit
2006-10-06 10:23:27 +02:00
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
2015-09-15 15:14:09 +02:00
system.cpu.commit.branchMispredicts 1048 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 27467 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.465213 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.343088 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-09-15 15:14:09 +02:00
system.cpu.commit.committed_per_cycle::0 22438 81.69% 81.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 2371 8.63% 90.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1089 3.96% 94.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 414 1.51% 95.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 277 1.01% 96.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 199 0.72% 97.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 197 0.72% 98.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 154 0.56% 98.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 328 1.19% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-09-15 15:14:09 +02:00
system.cpu.commit.committed_per_cycle::total 27467 # Number of insts commited each cycle
2014-05-10 00:58:50 +02:00
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedInsts::1 6389 # Number of instructions committed
system.cpu.commit.committedInsts::total 12778 # Number of instructions committed
2014-05-10 00:58:50 +02:00
system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::total 12778 # Number of ops (including micro ops) committed
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
2012-08-15 16:38:05 +02:00
system.cpu.commit.refs::0 2048 # Number of memory references committed
system.cpu.commit.refs::1 2048 # Number of memory references committed
system.cpu.commit.refs::total 4096 # Number of memory references committed
system.cpu.commit.loads::0 1183 # Number of loads committed
system.cpu.commit.loads::1 1183 # Number of loads committed
system.cpu.commit.loads::total 2366 # Number of loads committed
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars::0 0 # Number of memory barriers committed
system.cpu.commit.membars::1 0 # Number of memory barriers committed
system.cpu.commit.membars::total 0 # Number of memory barriers committed
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches::0 1050 # Number of branches committed
system.cpu.commit.branches::1 1050 # Number of branches committed
system.cpu.commit.branches::total 2100 # Number of branches committed
2011-07-10 19:56:09 +02:00
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
2012-08-15 16:38:05 +02:00
system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
2011-07-10 19:56:09 +02:00
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_1::IntAlu 4319 67.60% 67.90% # Class of committed instruction
system.cpu.commit.op_class_1::IntMult 1 0.02% 67.91% # Class of committed instruction
system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.91% # Class of committed instruction
system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::MemRead 1183 18.52% 86.46% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_1::total 6389 # Class of committed instruction
system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction
2015-09-15 15:14:09 +02:00
system.cpu.commit.bw_lim_events 328 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 129836 # The number of ROB reads
system.cpu.rob.rob_writes 57114 # The number of ROB writes
system.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 22132 # Total number of cycles that the CPU has spent unscheduled due to idling
2014-05-10 00:58:50 +02:00
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
2014-09-03 13:42:59 +02:00
system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
system.cpu.committedInsts::total 12744 # Number of Instructions Simulated
2014-05-10 00:58:50 +02:00
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
2014-09-03 13:42:59 +02:00
system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated
2015-09-15 15:14:09 +02:00
system.cpu.cpi::0 7.794413 # CPI: Cycles Per Instruction
system.cpu.cpi::1 7.794413 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.897207 # CPI: Total CPI of All Threads
system.cpu.ipc::0 0.128297 # IPC: Instructions Per Cycle
system.cpu.ipc::1 0.128297 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.256594 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 26491 # number of integer regfile reads
system.cpu.int_regfile_writes 14992 # number of integer regfile writes
2011-02-08 04:23:13 +01:00
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
2011-07-10 19:56:09 +02:00
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.tagsinuse 212.222617 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4769 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 344 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.863372 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 212.222617 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.051812 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.051812 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.083984 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 11936 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 11936 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 3748 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3748 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1021 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1021 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 4769 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4769 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4769 # number of overall hits
system.cpu.dcache.overall_hits::total 4769 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 709 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 709 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses
system.cpu.dcache.overall_misses::total 1027 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24395500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24395500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 50809414 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 50809414 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 75204914 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 75204914 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 75204914 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 75204914 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 4066 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 4066 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_accesses::cpu.data 5796 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 5796 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 5796 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 5796 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078210 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.078210 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409827 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.409827 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.177191 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.177191 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.177191 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.177191 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76715.408805 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 76715.408805 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71663.489422 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 71663.489422 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73227.764362 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73227.764362 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5829 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.blocked::no_mshrs 135 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.177778 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-09-15 15:14:09 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 683 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 683 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 198 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 198 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 344 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17299000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17299000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12670989 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12670989 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29969989 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29969989 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29969989 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29969989 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048697 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048697 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.059351 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.059351 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87368.686869 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87368.686869 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86787.595890 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86787.595890 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.replacements::0 8 # number of replacements
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements::1 0 # number of replacements
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.replacements::total 8 # number of replacements
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.tagsinuse 317.014953 # Cycle average of tags in use
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.total_refs 4463 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 634 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 7.039432 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 317.014953 # Average occupied blocks per requestor
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.154792 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.154792 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.305664 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11430 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11430 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 4463 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4463 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4463 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4463 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4463 # number of overall hits
system.cpu.icache.overall_hits::total 4463 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 935 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 935 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 935 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 935 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 935 # number of overall misses
system.cpu.icache.overall_misses::total 935 # number of overall misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 70147997 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 70147997 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 70147997 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 70147997 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 70147997 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 70147997 # number of overall miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 5398 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5398 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5398 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5398 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5398 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5398 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.173212 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.173212 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.173212 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.173212 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.173212 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.173212 # miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75024.595722 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75024.595722 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75024.595722 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75024.595722 # average overall miss latency
2015-09-15 15:14:09 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 3484 # number of cycles access was blocked
2009-04-22 19:25:17 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.icache.blocked::no_mshrs 77 # number of cycles access was blocked
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 45.246753 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-07-10 19:56:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
2006-10-07 17:32:10 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 8 # number of writebacks
system.cpu.icache.writebacks::total 8 # number of writebacks
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 301 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 301 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 301 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 301 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 634 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 634 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 634 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 634 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 634 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51561499 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 51561499 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51561499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 51561499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51561499 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 51561499 # number of overall MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117451 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.117451 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.117451 # mshr miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81327.285489 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81327.285489 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.tagsinuse 436.545027 # Cycle average of tags in use
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.sampled_refs 830 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.012048 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.712929 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 118.832098 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009696 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003626 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.013322 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 830 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 326 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 504 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 8864 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 8864 # Number of data accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_hits::writebacks 8 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 8 # number of WritebackClean hits
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 632 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 632 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 198 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 632 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 344 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 976 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 632 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 344 # number of overall misses
system.cpu.l2cache.overall_misses::total 976 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12444500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12444500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 50583000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 50583000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16994000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 16994000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 50583000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 29438500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 80021500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 50583000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 29438500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 80021500 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 8 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 8 # number of WritebackClean accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 634 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 634 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 198 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 634 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 344 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 978 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 634 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 344 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 978 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996845 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996845 # miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996845 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996845 # miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85236.301370 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85236.301370 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80036.392405 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80036.392405 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85828.282828 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85828.282828 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81989.241803 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81989.241803 # average overall miss latency
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
2006-10-07 17:32:10 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 632 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 632 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 632 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 976 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 632 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 976 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10984500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10984500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44263000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44263000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15014000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15014000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44263000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25998500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 70261500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44263000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25998500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 70261500 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996845 # mshr miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75236.301370 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75236.301370 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70036.392405 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70036.392405 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75828.282828 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75828.282828 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 986 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 8 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 634 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1964 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size::total 63104 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 978 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.002045 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.045198 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::0 976 99.80% 99.80% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::total 978 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 501000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 951000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 516000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadResp 830 # Transaction distribution
system.membus.trans_dist::ReadExReq 146 # Transaction distribution
system.membus.trans_dist::ReadExResp 146 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 830 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1952 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1952 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62464 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::samples 976 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::0 976 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::total 976 # Request fanout histogram
system.membus.reqLayer0.occupancy 1189000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 4.8 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.membus.respLayer1.occupancy 5195000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 20.9 # Layer utilization (%)
2006-10-06 10:23:27 +02:00
---------- End Simulation Statistics ----------
