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gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt

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ARM: Add regression tests
2010-07-27 07:03:44 +02:00
---------- Begin Simulation Statistics ----------
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
sim_seconds 0.708539 # Number of seconds simulated
sim_ticks 708539449500 # Number of ticks simulated
final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
host_inst_rate 318121 # Simulator instruction rate (inst/s)
host_op_rate 344511 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 446353500 # Simulator tick rate (ticks/s)
host_mem_usage 303968 # Number of bytes of host memory used
host_seconds 1587.40 # Real time elapsed on the host
sim_insts 504984064 # Number of instructions simulated
sim_ops 546875315 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory
system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory
system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
ARM: Update SE stats for TLB stats additions
2010-11-08 20:59:35 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.numCycles 1417078899 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.committedInsts 504984064 # Number of instructions committed
system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
system.cpu.num_int_insts 448447005 # number of integer instructions
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_insts 16 # number of float instructions
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.num_int_register_reads 748339662 # number of times the integer registers were read
system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
system.cpu.num_mem_refs 172743505 # number of memory refs
system.cpu.num_load_insts 115883283 # Number of load instructions
system.cpu.num_store_insts 56860222 # Number of store instructions
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.Branches 121552863 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.op_class::total 548692589 # Class of executed instruction
system.cpu.dcache.tags.replacements 1136276 # number of replacements
system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits
system.cpu.dcache.overall_hits::total 167200190 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses
system.cpu.dcache.overall_misses::total 1140372 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
system.cpu.dcache.writebacks::total 1065708 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 9788 # number of replacements
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits
system.cpu.icache.overall_hits::total 516597066 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
system.cpu.icache.overall_misses::total 11521 # number of overall misses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 516608587 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 516608587 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 516608587 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 9788 # number of writebacks
system.cpu.icache.writebacks::total 9788 # number of writebacks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.replacements 110394 # number of replacements
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks.
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits
system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses
system.cpu.l2cache.overall_misses::total 142364 # number of overall misses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses)
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 356508 # number of ReadExReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses)
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 783864 # number of ReadSharedReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 1140372 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1151893 # number of demand (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks
system.cpu.l2cache.writebacks::total 96330 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes)
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoops 110394 # Total snoops (count)
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadResp 41576 # Transaction distribution
system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::samples 250615 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 250615 # Request fanout histogram
stats: update stats for mmap changes
2016-03-17 18:30:58 +01:00
system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
ARM: Add regression tests
2010-07-27 07:03:44 +02:00
---------- End Simulation Statistics ----------
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