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stats: update stats for mmap changes

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This commit is contained in:
Steve Reinhardt 2016-03-17 10:30:58 -07:00
parent dbad391a9b
commit 4fc69db8f8
46 changed files with 3801 additions and 3699 deletions
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6
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 15 2016 19:39:16
gem5 started Mar 15 2016 19:40:29
gem5 executing on dinar2c11, pid 3692
gem5 compiled Mar 16 2016 15:38:19
gem5 started Mar 16 2016 15:38:47
gem5 executing on dinar2c11, pid 14352
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second

360
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,46 +4,46 @@ sim_seconds 0.061602 # Nu
sim_ticks 61602281500 # Number of ticks simulated
final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 59652 # Simulator instruction rate (inst/s)
host_op_rate 105038 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23259273 # Simulator tick rate (ticks/s)
host_mem_usage 445096 # Number of bytes of host memory used
host_seconds 2648.50 # Real time elapsed on the host
host_inst_rate 60207 # Simulator instruction rate (inst/s)
host_op_rate 106015 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23475786 # Simulator tick rate (ticks/s)
host_mem_usage 445092 # Number of bytes of host memory used
host_seconds 2624.08 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory
system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory
system.physmem.bytes_read::total 1946944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory
system.physmem.bytes_written::total 12160 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory
system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory
system.physmem.num_reads::total 30421 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory
system.physmem.num_writes::total 190 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 30569257 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 31606102 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 30568218 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 31605063 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 30569257 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 31803497 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 30422 # Number of read requests accepted
system.physmem.bw_total::cpu.data 30568218 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 31802458 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 30421 # Number of read requests accepted
system.physmem.writeReqs 190 # Number of write requests accepted
system.physmem.readBursts 30422 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readBursts 30421 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 1941504 # Total number of bytes read from DRAM
system.physmem.bytesReadDRAM 1941440 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue
system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 1947008 # Total read bytes from the system interface side
system.physmem.bytesReadSys 1946944 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
@ -57,7 +57,7 @@ system.physmem.perBankRdBursts::5 1901 # Pe
system.physmem.perBankRdBursts::6 1952 # Per bank write bursts
system.physmem.perBankRdBursts::7 1864 # Per bank write bursts
system.physmem.perBankRdBursts::8 1938 # Per bank write bursts
system.physmem.perBankRdBursts::9 1932 # Per bank write bursts
system.physmem.perBankRdBursts::9 1931 # Per bank write bursts
system.physmem.perBankRdBursts::10 1804 # Per bank write bursts
system.physmem.perBankRdBursts::11 1794 # Per bank write bursts
system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
@ -89,7 +89,7 @@ system.physmem.readPktSize::2 0 # Re
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 30422 # Read request sizes (log2)
system.physmem.readPktSize::6 30421 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@ -98,7 +98,7 @@ system.physmem.writePktSize::4 0 # Wr
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 190 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
@ -194,11 +194,11 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 716.489526 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 515.486965 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 387.954881 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 364 13.38% 13.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 231 8.49% 21.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 716.466005 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 515.355667 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 387.992511 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 365 13.41% 13.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 230 8.45% 21.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation
@ -208,8 +208,8 @@ system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # B
system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 3363.777778 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 10055.709980 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 3363.666667 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 10055.376646 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes
@ -221,11 +221,11 @@ system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Wr
system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads
system.physmem.totQLat 133021500 # Total ticks spent queuing
system.physmem.totMemAccLat 701821500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 151680000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4384.94 # Average queueing delay per DRAM burst
system.physmem.totMemAccLat 701802750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 151675000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4385.08 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23134.94 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 23135.08 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s
@ -236,11 +236,11 @@ system.physmem.busUtilRead 0.25 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing
system.physmem.readRowHits 27659 # Number of row buffer hits during reads
system.physmem.readRowHits 27658 # Number of row buffer hits during reads
system.physmem.writeRowHits 106 # Number of row buffer hits during writes
system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes
system.physmem.avgGap 2012351.25 # Average gap between requests
system.physmem.avgGap 2012416.99 # Average gap between requests
system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ)
@ -258,13 +258,13 @@ system.physmem_0.memoryStateTime::ACT 2211196750 # Ti
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ)
system.physmem_1.readEnergy 114199800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41481574230 # Total energy per rank (pJ)
system.physmem_1.averagePower 673.432024 # Core power per rank (mW)
system.physmem_1.totalEnergy 41481566430 # Total energy per rank (pJ)
system.physmem_1.averagePower 673.431898 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states
system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
@ -350,7 +350,7 @@ system.cpu.iq.iqNonSpecInstsAdded 2340 # Nu
system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 63882730 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedOperandsExamined 63882734 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle
@ -443,7 +443,7 @@ system.cpu.iq.fu_busy_cnt 3969927 # FU
system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 304282659 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_wakeup_accesses 304282658 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses
@ -483,8 +483,8 @@ system.cpu.iew.exec_refs 131430384 # nu
system.cpu.iew.exec_branches 31401849 # Number of branches executed
system.cpu.iew.exec_stores 33679798 # Number of stores executed
system.cpu.iew.exec_rate 2.476830 # Inst execution rate
system.cpu.iew.wb_sent 304565842 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 304282792 # cumulative count of insts written-back
system.cpu.iew.wb_sent 304565843 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 304282791 # cumulative count of insts written-back
system.cpu.iew.wb_producers 230213909 # num instructions producing a value
system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value
system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle
@ -573,22 +573,22 @@ system.cpu.cc_regfile_reads 107533030 # nu
system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes
system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 2072313 # number of replacements
system.cpu.dcache.tags.tagsinuse 4068.012890 # Cycle average of tags in use
system.cpu.dcache.tags.replacements 2072312 # number of replacements
system.cpu.dcache.tags.tagsinuse 4068.008256 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2076409 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 32.783059 # Average number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2076408 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 32.783074 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012890 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993167 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993167 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 4068.008256 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993166 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993166 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 143788645 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 143788645 # Number of data accesses
system.cpu.dcache.tags.tag_accesses 143788642 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 143788642 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits
@ -597,30 +597,30 @@ system.cpu.dcache.demand_hits::cpu.data 68071037 # nu
system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits
system.cpu.dcache.overall_hits::total 68071037 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2691154 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2691154 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::cpu.data 2691153 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2691153 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2785081 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2785081 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2785081 # number of overall misses
system.cpu.dcache.overall_misses::total 2785081 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304267000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 32304267000 # number of ReadReq miss cycles
system.cpu.dcache.demand_misses::cpu.data 2785080 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2785080 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2785080 # number of overall misses
system.cpu.dcache.overall_misses::total 2785080 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304195500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 32304195500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35260881994 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35260881994 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35260881994 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35260881994 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 39416366 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 39416366 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency::cpu.data 35260810494 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35260810494 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35260810494 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35260810494 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 39416365 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 39416365 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 70856118 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 70856118 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 70856118 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 70856118 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 70856117 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 70856117 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 70856117 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 70856117 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses
@ -629,14 +629,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.039306
system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.871573 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.871573 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12660.630694 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12660.630694 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12660.609567 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12660.609567 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked
@ -655,22 +655,22 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 708671
system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 1994366 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195993500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195993500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_misses::total 2076409 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2076409 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2076409 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195923000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195923000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 26995390495 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995390495 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26995390495 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995319995 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26995319995 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995319995 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26995319995 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses
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@ -679,14 +679,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305
system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.173082 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.173082 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.143815 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.143815 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.992335 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.992335 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 53 # number of replacements
system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use
@ -783,27 +783,27 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426
system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 493 # number of replacements
system.cpu.l2cache.tags.tagsinuse 20712.318868 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 30411 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 132.685640 # Average number of references to valid blocks.
system.cpu.l2cache.tags.tagsinuse 20711.322176 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4035102 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 30410 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 132.689970 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917380 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 244.920687 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::total 0.632090 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29918 # Occupied blocks per task id
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system.cpu.l2cache.tags.occ_percent::total 0.632059 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29917 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27623 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913025 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 33310473 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 33310473 # Number of data accesses
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27622 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.912994 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 33310456 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 33310456 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2066601 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2066601 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits
@ -826,26 +826,26 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 28998
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system.cpu.l2cache.overall_miss_latency::total 2226490000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066601 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2066601 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses)
@ -856,38 +856,38 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916 # average ReadExReq miss latency
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system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76769.953052 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76769.953052 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76788.235294 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76788.235294 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -902,117 +902,117 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998
system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses
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system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66769.953052 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66769.953052 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66788.235294 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66788.235294 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_requests 4149788 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072369 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1995353 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6015 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6014 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994339 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225133 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6227214 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225130 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6227211 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 265220928 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152576 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 265220864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 493 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2077917 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 2077916 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2077592 99.98% 99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2077591 99.98% 99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2077917 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4141549000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 2077916 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4141548000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 3114612500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 1424 # Transaction distribution
system.membus.trans_dist::ReadResp 1423 # Transaction distribution
system.membus.trans_dist::WritebackDirty 190 # Transaction distribution
system.membus.trans_dist::CleanEvict 24 # Transaction distribution
system.membus.trans_dist::ReadExReq 28998 # Transaction distribution
system.membus.trans_dist::ReadExResp 28998 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1424 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61058 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61058 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 61058 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959168 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959168 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1959168 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadSharedReq 1423 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61056 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61056 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 61056 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959104 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959104 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1959104 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 30636 # Request fanout histogram
system.membus.snoop_fanout::samples 30635 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 30636 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 30635 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 30636 # Request fanout histogram
system.membus.reqLayer0.occupancy 42770500 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 30635 # Request fanout histogram
system.membus.reqLayer0.occupancy 42769000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 160321750 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 160316500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

28
tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
View file

@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@ -24,6 +25,7 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@ -132,9 +134,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -148,6 +150,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -591,9 +594,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -607,6 +610,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -626,6 +630,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@ -701,9 +706,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -717,6 +722,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -732,12 +738,14 @@ size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=Null
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -745,6 +753,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@ -759,9 +774,9 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
@ -794,6 +809,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr
View file

@ -1,3 +1,2 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]

10
tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
View file

@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 14 2015 23:29:19
gem5 started Sep 15 2015 03:04:52
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
gem5 compiled Mar 16 2016 15:51:04
gem5 started Mar 16 2016 15:55:43
gem5 executing on dinar2c11, pid 15340
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -70,4 +70,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 363605295500 because target called exit()
Exiting @ tick 363608804500 because target called exit()

1133
tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
View file

@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@ -24,6 +25,7 @@ mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@ -130,6 +132,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@ -213,9 +216,9 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
@ -248,6 +251,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
View file

@ -1 +0,0 @@
warn: Sockets disabled, not accepting gdb connections

14
tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:19:30
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
gem5 compiled Mar 16 2016 15:51:04
gem5 started Mar 16 2016 16:37:21
gem5 executing on dinar2c11, pid 16154
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x5d016c0
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@ -68,4 +70,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 290498967000 because target called exit()
Exiting @ tick 279360903000 because target called exit()

134
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.279362 # Number of seconds simulated
sim_ticks 279362298000 # Number of ticks simulated
final_tick 279362298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.279361 # Number of seconds simulated
sim_ticks 279360903000 # Number of ticks simulated
final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1944100 # Simulator instruction rate (inst/s)
host_op_rate 2105717 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1072104103 # Simulator tick rate (ticks/s)
host_mem_usage 306580 # Number of bytes of host memory used
host_seconds 260.57 # Real time elapsed on the host
sim_insts 506581608 # Number of instructions simulated
sim_ops 548694829 # Number of ops (including micro ops) simulated
host_inst_rate 505182 # Simulator instruction rate (inst/s)
host_op_rate 547179 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 278590581 # Simulator tick rate (ticks/s)
host_mem_usage 293956 # Number of bytes of host memory used
host_seconds 1002.77 # Real time elapsed on the host
sim_insts 506578818 # Number of instructions simulated
sim_ops 548692039 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 2066445504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory
system.physmem.bytes_read::total 2489298205 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2066445504 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2066445504 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory
system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 516611376 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory
system.physmem.num_reads::total 632202903 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory
system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7397009256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1513635534 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8910644789 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7397009256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7397009256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 773431582 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 773431582 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7397009256 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2287067115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9684076371 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory
system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory
system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory
system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory
system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,33 +153,33 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 558724597 # number of cpu cycles simulated
system.cpu.numCycles 558721807 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506581608 # Number of instructions committed
system.cpu.committedOps 548694829 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
system.cpu.committedInsts 506578818 # Number of instructions committed
system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls
system.cpu.num_int_insts 448454356 # number of integer instructions
system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
system.cpu.num_int_insts 448447005 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read
system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written
system.cpu.num_int_register_reads 749023756 # number of times the integer registers were read
system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1634230250 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
system.cpu.num_mem_refs 172745235 # number of memory refs
system.cpu.num_load_insts 115884756 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
system.cpu.num_mem_refs 172743505 # number of memory refs
system.cpu.num_load_insts 115883283 # Number of load instructions
system.cpu.num_store_insts 56860222 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 558724596.998000 # Number of busy cycles
system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 121548302 # Number of branches fetched
system.cpu.Branches 121552863 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction
system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
@ -208,36 +208,36 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 548695379 # Class of executed instruction
system.membus.trans_dist::ReadReq 630711791 # Transaction distribution
system.membus.trans_dist::ReadResp 632200332 # Transaction distribution
system.membus.trans_dist::WriteReq 54239306 # Transaction distribution
system.membus.trans_dist::WriteResp 54239306 # Transaction distribution
system.cpu.op_class::total 548692589 # Class of executed instruction
system.membus.trans_dist::ReadReq 630707528 # Transaction distribution
system.membus.trans_dist::ReadResp 632196069 # Transaction distribution
system.membus.trans_dist::WriteReq 54239049 # Transaction distribution
system.membus.trans_dist::WriteResp 54239049 # Transaction distribution
system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222752 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1375861500 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445504 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2705365829 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 687930750 # Request fanout histogram
system.membus.snoop_fanout::mean 0.750964 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
system.membus.snoop_fanout::samples 687926230 # Request fanout histogram
system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 171319374 24.90% 24.90% # Request fanout histogram
system.membus.snoop_fanout::1 516611376 75.10% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram
system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 687930750 # Request fanout histogram
system.membus.snoop_fanout::total 687926230 # Request fanout histogram
---------- End Simulation Statistics ----------

28
tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
View file

@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@ -24,6 +25,7 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@ -85,9 +87,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -101,6 +103,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -161,9 +164,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -177,6 +180,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -196,6 +200,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@ -271,9 +276,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -287,6 +292,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -302,12 +308,14 @@ size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=Null
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -315,6 +323,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@ -329,9 +344,9 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
@ -364,6 +379,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
View file

@ -1 +0,0 @@
warn: Sockets disabled, not accepting gdb connections

14
tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 23 2014 12:08:08
gem5 started Jan 23 2014 17:21:27
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
gem5 compiled Mar 16 2016 15:51:04
gem5 started Mar 16 2016 15:51:37
gem5 executing on dinar2c11, pid 15211
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x6322040
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@ -68,4 +70,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 717366012000 because target called exit()
Exiting @ tick 708539449500 because target called exit()

584
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.708526 # Number of seconds simulated
sim_ticks 708526400500 # Number of ticks simulated
final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.708539 # Number of seconds simulated
sim_ticks 708539449500 # Number of ticks simulated
final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 942956 # Simulator instruction rate (inst/s)
host_op_rate 1021179 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1323022561 # Simulator tick rate (ticks/s)
host_mem_usage 320452 # Number of bytes of host memory used
host_seconds 535.54 # Real time elapsed on the host
sim_insts 504986854 # Number of instructions simulated
sim_ops 546878105 # Number of ops (including micro ops) simulated
host_inst_rate 318121 # Simulator instruction rate (inst/s)
host_op_rate 344511 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 446353500 # Simulator tick rate (ticks/s)
host_mem_usage 303968 # Number of bytes of host memory used
host_seconds 1587.40 # Real time elapsed on the host
sim_insts 504984064 # Number of instructions simulated
sim_ops 546875315 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 140061 # Nu
system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory
system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 208026 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12651475 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12859501 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 208026 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 208026 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8701327 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8701327 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8701327 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 208026 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12651475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21560828 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -154,33 +154,33 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 1417052801 # number of cpu cycles simulated
system.cpu.numCycles 1417078899 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 504986854 # Number of instructions committed
system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
system.cpu.committedInsts 504984064 # Number of instructions committed
system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls
system.cpu.num_int_insts 448454356 # number of integer instructions
system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
system.cpu.num_int_insts 448447005 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read
system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written
system.cpu.num_int_register_reads 748339662 # number of times the integer registers were read
system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
system.cpu.num_mem_refs 172745235 # number of memory refs
system.cpu.num_load_insts 115884756 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
system.cpu.num_mem_refs 172743505 # number of memory refs
system.cpu.num_load_insts 115883283 # Number of load instructions
system.cpu.num_store_insts 56860222 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1417052800.998000 # Number of busy cycles
system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 121548302 # Number of branches fetched
system.cpu.Branches 121552863 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction
system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
@ -209,18 +209,18 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 548695379 # Class of executed instruction
system.cpu.dcache.tags.replacements 1134822 # number of replacements
system.cpu.dcache.tags.tagsinuse 4065.260615 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.
system.cpu.op_class::total 548692589 # Class of executed instruction
system.cpu.dcache.tags.replacements 1136276 # number of replacements
system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.260615 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -230,72 +230,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 343
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits
system.cpu.dcache.overall_hits::total 167203374 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits
system.cpu.dcache.overall_hits::total 167200190 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12104797500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12104797500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9574077500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9574077500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 21678875000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 21678875000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 21678875000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 21678875000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses
system.cpu.dcache.overall_misses::total 1140372 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15466.286636 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15466.286636 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26873.849155 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26873.849155 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19034.639925 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19034.639925 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19034.623213 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19034.623213 # average overall miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -304,58 +304,58 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1064678 # number of writebacks
system.cpu.dcache.writebacks::total 1064678 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
system.cpu.dcache.writebacks::total 1065708 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11322140500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11322140500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9217817500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9217817500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20539958000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 20539958000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20540019000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 20540019000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.286636 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.286636 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25873.849155 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25873.849155 # average WriteReq mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18034.639925 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18034.639925 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18034.677650 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18034.677650 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 9788 # number of replacements
system.cpu.icache.tags.tagsinuse 983.180611 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 983.180611 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.480069 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.480069 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
@ -363,44 +363,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 24
system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1033234275 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1033234275 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 516599856 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 516599856 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 516599856 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 516599856 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 516599856 # number of overall hits
system.cpu.icache.overall_hits::total 516599856 # number of overall hits
system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits
system.cpu.icache.overall_hits::total 516597066 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
system.cpu.icache.overall_misses::total 11521 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 263208000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 263208000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 263208000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 263208000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 263208000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 263208000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 516611377 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 516611377 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 516611377 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.190674 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
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@ -485,58 +485,58 @@ system.cpu.l2cache.demand_misses::total 142364 # nu
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282906 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282906 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050179 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050179 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123748 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123748 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.208160 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.208160 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49587.494572 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49587.494572 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49568.991419 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49568.991419 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 84208 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3412658 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3445488 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 142393920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 110394 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.066862 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1255174 99.55% 99.55% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 5658 0.45% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1260833 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2221990500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 41576 # Transaction distribution
system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
@ -659,7 +659,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 250615 # Request fanout histogram
system.membus.reqLayer0.occupancy 644475328 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)

7
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
View file

@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@ -24,6 +25,7 @@ mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@ -147,9 +149,9 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
@ -182,6 +184,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
View file

@ -1 +0,0 @@
warn: Sockets disabled, not accepting gdb connections

13
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -1,10 +1,13 @@
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:10:34
gem5 started Jan 22 2014 20:48:32
gem5 executing on u200540-lin
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
gem5 compiled Mar 16 2016 15:38:19
gem5 started Mar 16 2016 15:38:59
gem5 executing on dinar2c11, pid 14361
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -69,4 +72,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 885229328000 because target called exit()
Exiting @ tick 885256008500 because target called exit()

146
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,72 +1,72 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.885229 # Number of seconds simulated
sim_ticks 885229328000 # Number of ticks simulated
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.885256 # Number of seconds simulated
sim_ticks 885256008500 # Number of ticks simulated
final_tick 885256008500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1361574 # Simulator instruction rate (inst/s)
host_op_rate 2517703 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1457659146 # Simulator tick rate (ticks/s)
host_mem_usage 313840 # Number of bytes of host memory used
host_seconds 607.30 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
host_inst_rate 362789 # Simulator instruction rate (inst/s)
host_op_rate 670835 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 388389023 # Simulator tick rate (ticks/s)
host_mem_usage 304128 # Number of bytes of host memory used
host_seconds 2279.30 # Real time elapsed on the host
sim_insts 826906380 # Number of instructions simulated
sim_ops 1529035683 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285655658 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832432178 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 991849462 # Number of bytes written to this memory
system.physmem.bytes_written::total 991849462 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384102186 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452449251 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 149160202 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149160202 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9654872754 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12236865449 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9654872754 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9654872754 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1120443517 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1120443517 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 8547061720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285750420 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832812140 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8547061720 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8547061720 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 991875282 # Number of bytes written to this memory
system.physmem.bytes_written::total 991875282 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068382715 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384117854 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452500569 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 149164510 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149164510 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9654903935 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2582021921 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12236925856 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9654903935 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9654903935 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1120438915 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1120438915 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9654903935 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702460837 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357364772 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1770458657 # number of cpu cycles simulated
system.cpu.numCycles 1770512018 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses
system.cpu.committedInsts 826906380 # Number of instructions committed
system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1526605510 # number of integer instructions
system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls
system.cpu.num_int_insts 1526653037 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written
system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written
system.cpu.num_mem_refs 533262343 # number of memory refs
system.cpu.num_load_insts 384102157 # Number of load instructions
system.cpu.num_store_insts 149160186 # Number of store instructions
system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written
system.cpu.num_mem_refs 533282319 # number of memory refs
system.cpu.num_load_insts 384117825 # Number of load instructions
system.cpu.num_store_insts 149164494 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1770458656.998000 # Number of busy cycles
system.cpu.num_busy_cycles 1770512017.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149758583 # Number of branches fetched
system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction
system.cpu.Branches 149762544 # Number of branches fetched
system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction
system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
@ -93,35 +93,35 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction
system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction
system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction
system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1528988702 # Class of executed instruction
system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution
system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution
system.membus.trans_dist::WriteReq 149160202 # Transaction distribution
system.membus.trans_dist::WriteResp 149160202 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.op_class::total 1529035683 # Class of executed instruction
system.membus.trans_dist::ReadReq 1452500569 # Transaction distribution
system.membus.trans_dist::ReadResp 1452500569 # Transaction distribution
system.membus.trans_dist::WriteReq 149164510 # Transaction distribution
system.membus.trans_dist::WriteResp 149164510 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136765430 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 2136765430 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066564728 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 1066564728 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3203330158 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8547061720 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 8547061720 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277625702 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 3277625702 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 11824687422 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram
system.membus.snoop_fanout::mean 0.667046 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
system.membus.snoop_fanout::samples 1601665079 # Request fanout histogram
system.membus.snoop_fanout::mean 0.667045 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.471271 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 533262388 33.30% 33.30% # Request fanout histogram
system.membus.snoop_fanout::1 1068347065 66.70% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 533282364 33.30% 33.30% # Request fanout histogram
system.membus.snoop_fanout::1 1068382715 66.70% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 1601609453 # Request fanout histogram
system.membus.snoop_fanout::total 1601665079 # Request fanout histogram
---------- End Simulation Statistics ----------

27
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@ -24,6 +25,7 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@ -89,9 +91,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -105,6 +107,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -139,9 +142,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -155,6 +158,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -205,9 +209,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -221,6 +225,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -236,12 +241,14 @@ size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=Null
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -249,6 +256,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@ -263,9 +277,9 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
@ -298,6 +312,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
View file

@ -1 +0,0 @@
warn: Sockets disabled, not accepting gdb connections

13
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -1,10 +1,13 @@
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 17:10:34
gem5 started Jan 22 2014 20:57:08
gem5 executing on u200540-lin
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
gem5 compiled Mar 16 2016 15:38:19
gem5 started Mar 16 2016 15:38:49
gem5 executing on dinar2c11, pid 14355
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -69,4 +72,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 1647872849000 because target called exit()
Exiting @ tick 1650600522500 because target called exit()

662
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,73 +1,73 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.650527 # Number of seconds simulated
sim_ticks 1650526667500 # Number of ticks simulated
final_tick 1650526667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 1.650601 # Number of seconds simulated
sim_ticks 1650600522500 # Number of ticks simulated
final_tick 1650600522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 726731 # Simulator instruction rate (inst/s)
host_op_rate 1343807 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1450624585 # Simulator tick rate (ticks/s)
host_mem_usage 327760 # Number of bytes of host memory used
host_seconds 1137.80 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
host_inst_rate 236277 # Simulator instruction rate (inst/s)
host_op_rate 436901 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 471636555 # Simulator tick rate (ticks/s)
host_mem_usage 314152 # Number of bytes of host memory used
host_seconds 3499.73 # Real time elapsed on the host
sim_insts 826906380 # Number of instructions simulated
sim_ops 1529035683 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24258880 # Number of bytes read from this memory
system.physmem.bytes_read::total 24374656 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 18765184 # Number of bytes written to this memory
system.physmem.bytes_written::total 18765184 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 70145 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14697699 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14767844 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 70145 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 70145 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11369249 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11369249 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11369249 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 70145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14697699 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26137092 # Total bandwidth to/from this memory (bytes/s)
system.physmem.num_reads::cpu.data 379045 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380854 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293206 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293206 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 70142 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14697002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14767144 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 70142 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 70142 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11368701 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11368701 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11368701 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 70142 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14697002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26135845 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3301053335 # number of cpu cycles simulated
system.cpu.numCycles 3301201045 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses
system.cpu.committedInsts 826906380 # Number of instructions committed
system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1526605510 # number of integer instructions
system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls
system.cpu.num_int_insts 1526653037 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written
system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written
system.cpu.num_mem_refs 533262343 # number of memory refs
system.cpu.num_load_insts 384102157 # Number of load instructions
system.cpu.num_store_insts 149160186 # Number of store instructions
system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written
system.cpu.num_mem_refs 533282319 # number of memory refs
system.cpu.num_load_insts 384117825 # Number of load instructions
system.cpu.num_store_insts 149164494 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 3301053334.998000 # Number of busy cycles
system.cpu.num_busy_cycles 3301201044.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149758583 # Number of branches fetched
system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction
system.cpu.Branches 149762544 # Number of branches fetched
system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction
system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
@ -94,18 +94,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction
system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction
system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction
system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1528988702 # Class of executed instruction
system.cpu.dcache.tags.replacements 2514362 # number of replacements
system.cpu.dcache.tags.tagsinuse 4086.386622 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
system.cpu.op_class::total 1529035683 # Class of executed instruction
system.cpu.dcache.tags.replacements 2515885 # number of replacements
system.cpu.dcache.tags.tagsinuse 4086.387052 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 530762383 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2519981 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 210.621581 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386622 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.387052 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -115,56 +115,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 29
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits
system.cpu.dcache.overall_hits::total 530743930 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30918235500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30918235500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20395021500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20395021500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 51313257000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51313257000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 51313257000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51313257000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17898.567165 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17898.567165 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25782.410966 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25782.410966 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20374.871052 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20374.871052 # average overall miss latency
system.cpu.dcache.tags.tag_accesses 1069084709 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1069084709 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 382389020 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382389020 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148373363 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148373363 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530762383 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530762383 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530762383 # number of overall hits
system.cpu.dcache.overall_hits::total 530762383 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1728834 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1728834 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791147 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 791147 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2519981 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2519981 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2519981 # number of overall misses
system.cpu.dcache.overall_misses::total 2519981 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30936646500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30936646500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20396358500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20396358500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 51333005000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51333005000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 51333005000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51333005000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384117854 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384117854 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149164510 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149164510 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533282364 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533282364 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533282364 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533282364 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004501 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004501 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005304 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005304 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004725 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004725 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004725 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004725 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17894.515321 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17894.515321 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25780.744286 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25780.744286 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20370.393666 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20370.393666 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -173,50 +173,50 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2323200 # number of writebacks
system.cpu.dcache.writebacks::total 2323200 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29190821500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29190821500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19603977500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19603977500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48794799000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 48794799000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48794799000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 48794799000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16898.567165 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16898.567165 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24782.410966 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24782.410966 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency
system.cpu.dcache.writebacks::writebacks 2324237 # number of writebacks
system.cpu.dcache.writebacks::total 2324237 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1728834 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1728834 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791147 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 791147 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2519981 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2519981 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2519981 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2519981 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29207812500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29207812500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19605211500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19605211500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48813024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 48813024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48813024000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 48813024000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004501 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004501 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005304 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005304 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004725 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004725 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16894.515321 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16894.515321 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24780.744286 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24780.744286 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1253 # number of replacements
system.cpu.icache.tags.tagsinuse 881.361122 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 881.377882 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068379901 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 379665.920753 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 881.361122 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 881.377882 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430360 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430360 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
@ -224,44 +224,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 7
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2136696944 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136696944 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068344251 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068344251 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068344251 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068344251 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits
system.cpu.icache.overall_hits::total 1068344251 # number of overall hits
system.cpu.icache.tags.tag_accesses 2136768244 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136768244 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068379901 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068379901 # number of ReadReq hits
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system.cpu.icache.overall_hits::cpu.inst 1068379901 # number of overall hits
system.cpu.icache.overall_hits::total 1068379901 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 125252000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 125252000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 125252000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 125252000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 125252000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 125256000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 125256000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 125256000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 125256000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 125256000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 125256000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068382715 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068382715 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068382715 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068382715 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068382715 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068382715 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44510.305615 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44510.305615 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44510.305615 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44510.305615 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.727079 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44511.727079 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44511.727079 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44511.727079 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -278,126 +278,126 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122438000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 122438000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122438000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 122438000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122438000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 122438000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122442000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 122442000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122442000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 122442000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
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@ -406,125 +406,125 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099970 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099970 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099888 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099888 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151057 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.150965 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151057 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.026653 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.026653 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49509.397457 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49509.397457 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.150965 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.885019 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.885019 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234526 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234526 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_requests 5039933 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2517138 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2616408 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1731648 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2617444 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 246392 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 246878 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 791147 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 791147 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1728834 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7555847 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7562728 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309866112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 310126400 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2869710 # Request fanout histogram
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310029952 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 310290240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 348437 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2871232 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.024538 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.024532 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2867981 99.94% 99.94% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2869503 99.94% 99.94% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2869710 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4842896500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 2871232 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4845456500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 3779971500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 174499 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
system.membus.trans_dist::ReadResp 174498 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293206 # Transaction distribution
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadSharedReq 174498 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108421 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108421 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1108421 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43139840 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 727569 # Request fanout histogram
system.membus.snoop_fanout::samples 727567 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 727567 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 727569 # Request fanout histogram
system.membus.reqLayer0.occupancy 1900428500 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 727567 # Request fanout histogram
system.membus.reqLayer0.occupancy 1900421500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 1904270000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

26
tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
View file

@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@ -24,6 +25,7 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@ -85,9 +87,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -101,6 +103,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -161,9 +164,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -177,6 +180,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -196,6 +200,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@ -271,9 +276,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -287,6 +292,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -302,12 +308,14 @@ size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=Null
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -315,6 +323,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@ -329,7 +344,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
@ -364,6 +379,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
View file

@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera

10
tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
View file

@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 14 2015 23:29:19
gem5 started Sep 15 2015 03:56:42
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
gem5 compiled Mar 16 2016 15:51:04
gem5 started Mar 16 2016 17:19:39
gem5 executing on dinar2c11, pid 17050
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -16,4 +16,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.510000
Exiting @ tick 517235407500 because target called exit()
Exiting @ tick 517287152500 because target called exit()

702
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.517291 # Number of seconds simulated
sim_ticks 517291025500 # Number of ticks simulated
final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.517287 # Number of seconds simulated
sim_ticks 517287152500 # Number of ticks simulated
final_tick 517287152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 634406 # Simulator instruction rate (inst/s)
host_op_rate 761628 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1203245454 # Simulator tick rate (ticks/s)
host_mem_usage 324572 # Number of bytes of host memory used
host_seconds 429.91 # Real time elapsed on the host
sim_insts 272739286 # Number of instructions simulated
sim_ops 327433744 # Number of ops (including micro ops) simulated
host_inst_rate 131506 # Simulator instruction rate (inst/s)
host_op_rate 157879 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 249419657 # Simulator tick rate (ticks/s)
host_mem_usage 307088 # Number of bytes of host memory used
host_seconds 2073.96 # Real time elapsed on the host
sim_insts 272737951 # Number of instructions simulated
sim_ops 327435116 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 269696 # Number of bytes read from this memory
system.physmem.bytes_read::total 436672 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4214 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6823 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 322792 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 521366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 844158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 322792 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 322792 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 322792 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 521366 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 844158 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -147,33 +147,33 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 1034582051 # number of cpu cycles simulated
system.cpu.numCycles 1034574305 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 272739286 # Number of instructions committed
system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
system.cpu.committedInsts 272737951 # Number of instructions committed
system.cpu.committedOps 327435116 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258332236 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
system.cpu.num_int_insts 258331537 # number of integer instructions
system.cpu.num_func_calls 12449970 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15800021 # number of instructions that are conditional controls
system.cpu.num_int_insts 258332236 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
system.cpu.num_int_register_reads 1215886434 # number of times the integer registers were read
system.cpu.num_int_register_writes 162499715 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
system.cpu.num_mem_refs 168107847 # number of memory refs
system.cpu.num_load_insts 85732248 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_cc_register_reads 1242911540 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76355719 # number of times the CC registers were written
system.cpu.num_mem_refs 168105830 # number of memory refs
system.cpu.num_load_insts 85730232 # Number of load instructions
system.cpu.num_store_insts 82375598 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
system.cpu.num_busy_cycles 1034574304.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 30563503 # Number of branches fetched
system.cpu.Branches 30566209 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntAlu 104315933 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
@ -198,79 +198,79 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Cl
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 19652356 5.99% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.67% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::MemRead 85730232 26.15% 74.87% # Class of executed instruction
system.cpu.op_class::MemWrite 82375598 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 327812214 # Class of executed instruction
system.cpu.dcache.tags.replacements 1332 # number of replacements
system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
system.cpu.op_class::total 327813586 # Class of executed instruction
system.cpu.dcache.tags.replacements 1326 # number of replacements
system.cpu.dcache.tags.tagsinuse 3078.339297 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168357609 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4469 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37672.322443 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.339297 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.751548 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.751548 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3143 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 678 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2434 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.767334 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336728627 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336728627 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86231946 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86231946 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82049814 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82049814 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
system.cpu.dcache.demand_hits::cpu.data 168281760 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168281760 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168335819 # number of overall hits
system.cpu.dcache.overall_hits::total 168335819 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1605 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1605 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2862 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2862 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_misses::cpu.data 4467 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4467 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4470 # number of overall misses
system.cpu.dcache.overall_misses::total 4470 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88066000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88066000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 176802500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 176802500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 264868500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 264868500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 264868500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 264868500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86233551 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86233551 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052676 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052676 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 168286227 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168286227 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168340289 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168340289 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54869.781931 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54869.781931 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61775.856045 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61775.856045 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59294.492948 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59294.492948 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59254.697987 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59254.697987 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -297,34 +297,34 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
system.cpu.dcache.writebacks::total 998 # number of writebacks
system.cpu.dcache.writebacks::writebacks 997 # number of writebacks
system.cpu.dcache.writebacks::total 997 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1604 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1604 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2862 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2862 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_misses::cpu.data 4466 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4466 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4469 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4469 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86415000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86415000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 173940500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 173940500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260355500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 260355500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260538500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 260538500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
@ -335,71 +335,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53874.688279 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53874.688279 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60775.856045 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60775.856045 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58297.245858 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58297.245858 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58299.060192 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58299.060192 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 13796 # number of replacements
system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
system.cpu.icache.tags.replacements 13798 # number of replacements
system.cpu.icache.tags.tagsinuse 1765.947853 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 348643415 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15605 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22341.776033 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.947853 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
system.cpu.icache.overall_hits::total 348644750 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
system.cpu.icache.overall_misses::total 15603 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses
system.cpu.icache.tags.tag_accesses 697333645 # Number of tag accesses
system.cpu.icache.tags.data_accesses 697333645 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 348643415 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348643415 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 348643415 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 348643415 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 348643415 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15605 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15605 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 15605 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 15605 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 338522000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 338522000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 338522000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 338522000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 338522000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 348659020 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 348659020 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 348659020 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21693.175264 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21693.175264 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21693.175264 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21693.175264 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -408,42 +408,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
system.cpu.icache.writebacks::total 13796 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
system.cpu.icache.writebacks::writebacks 13798 # number of writebacks
system.cpu.icache.writebacks::total 13798 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15605 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15605 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15605 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15605 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::total 15605 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322917000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 322917000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322917000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 322917000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322917000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 322917000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.175264 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.175264 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 3487.616981 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::writebacks 341.600605 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.332701 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.683674 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
@ -451,92 +451,92 @@ system.cpu.l2cache.tags.occ_percent::total 0.106434 #
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1233 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
system.cpu.l2cache.tags.tag_accesses 228016 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 228016 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 997 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 997 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6213 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 6213 # number of WritebackClean hits
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system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadCleanReq_hits::total 12996 # number of ReadCleanReq hits
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system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
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system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
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system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses
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system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
system.cpu.l2cache.demand_miss_latency::cpu.inst 155351500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 251066500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 406418000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 155351500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 251066500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 406418000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 997 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 997 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 6213 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 6213 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2862 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2862 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15605 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15605 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1607 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1607 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 15605 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4469 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 20074 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15605 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4469 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 20074 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994410 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994410 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167190 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167190 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851276 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851276 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167190 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.942940 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.339892 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167190 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.942940 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.339892 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.664793 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.664793 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.461479 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.461479 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59565.880111 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59565.880111 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -545,115 +545,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2846 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2846 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2609 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2609 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 4214 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 6823 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4214 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 6823 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141015500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141015500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129261500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129261500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129261500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 208926500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 338188000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129261500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 208926500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 338188000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994410 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994410 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167190 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851276 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851276 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.339892 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.339892 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.664793 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.664793 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.461479 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.461479 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_requests 35198 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15220 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7664 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.trans_dist::ReadResp 17212 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 997 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13798 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 329 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2862 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2862 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15605 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1607 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45008 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10264 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 55272 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 349824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2231616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 20074 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.386570 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.486976 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 12314 61.34% 61.34% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 7760 38.66% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 20074 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 32394000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 23407500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadResp 3977 # Transaction distribution
system.membus.trans_dist::ReadExReq 2846 # Transaction distribution
system.membus.trans_dist::ReadExResp 2846 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3977 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13646 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13646 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 436672 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 436672 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6833 # Request fanout histogram
system.membus.snoop_fanout::samples 6824 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 6824 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 6833 # Request fanout histogram
system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 6824 # Request fanout histogram
system.membus.reqLayer0.occupancy 7272500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 34115000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

26
tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
View file

@ -15,6 +15,7 @@ boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@ -24,6 +25,7 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@ -132,9 +134,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -148,6 +150,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -591,9 +594,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -607,6 +610,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -626,6 +630,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@ -701,9 +706,9 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -717,6 +722,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -732,12 +738,14 @@ size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=Null
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -745,6 +753,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@ -759,7 +774,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
@ -794,6 +809,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr
View file

@ -1,2 +1 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections

10
tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout
View file

@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 14 2015 23:29:19
gem5 started Sep 15 2015 03:05:45
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
gem5 compiled Mar 16 2016 15:51:04
gem5 started Mar 16 2016 16:24:45
gem5 executing on dinar2c11, pid 15928
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 56986224500 because target called exit()
Exiting @ tick 56966152500 because target called exit()

977
tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
View file

@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 15 2016 19:53:43
gem5 started Mar 15 2016 20:46:50
gem5 executing on dinar2c11, pid 11157
gem5 compiled Mar 16 2016 15:51:04
gem5 started Mar 16 2016 17:20:18
gem5 executing on dinar2c11, pid 17075
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 33784139000 because target called exit()
Exiting @ tick 33708718000 because target called exit()

1631
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -3,13 +3,11 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 15 2016 19:39:16
gem5 started Mar 15 2016 19:40:28
gem5 executing on dinar2c11, pid 3690
gem5 compiled Mar 16 2016 15:38:19
gem5 started Mar 16 2016 15:38:50
gem5 executing on dinar2c11, pid 14357
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

74
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.079141 # Nu
sim_ticks 79140979500 # Number of ticks simulated
final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 48534 # Simulator instruction rate (inst/s)
host_op_rate 81347 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29082810 # Simulator tick rate (ticks/s)
host_mem_usage 336912 # Number of bytes of host memory used
host_seconds 2721.23 # Real time elapsed on the host
host_inst_rate 48369 # Simulator instruction rate (inst/s)
host_op_rate 81071 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28984226 # Simulator tick rate (ticks/s)
host_mem_usage 336892 # Number of bytes of host memory used
host_seconds 2730.48 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -266,7 +266,7 @@ system.cpu.numCycles 158281960 # nu
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 227540230 # Number of instructions fetch has processed
system.cpu.fetch.Insts 227540228 # Number of instructions fetch has processed
system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked
@ -280,17 +280,17 @@ system.cpu.fetch.CacheLines 24267792 # Nu
system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.324971 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 95737540 60.56% 60.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 95737539 60.56% 60.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3804663 2.41% 65.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4706874 2.98% 77.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 31950307 20.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
@ -299,8 +299,8 @@ system.cpu.fetch.branchRate 0.130173 # Nu
system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 23286260 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 21616249 # Number of cycles decode is unblocking
system.cpu.decode.RunCycles 23286259 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 21616250 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing
@ -314,22 +314,22 @@ system.cpu.rename.ROBFullEvents 1575 # Nu
system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 380441374 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 910027756 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 600617832 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 380441368 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 910027762 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 600617825 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 121011924 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 121011918 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 82787392 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedLoads 82787391 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 259397690 # Number of instructions issued
system.cpu.iq.iqInstsIssued 259397692 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph
@ -338,8 +338,8 @@ system.cpu.iq.issued_per_cycle::samples 158076676 # Nu
system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 40037946 25.33% 25.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 47502915 30.05% 55.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 40037944 25.33% 25.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 47502917 30.05% 55.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle
@ -386,7 +386,7 @@ system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 161810980 62.38% 62.85% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 161810982 62.38% 62.85% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued
@ -419,21 +419,21 @@ system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Ty
system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 259397690 # Type of FU issued
system.cpu.iq.FU_type_0::total 259397692 # Type of FU issued
system.cpu.iq.rate 1.638833 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 675268343 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 675268347 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_wakeup_accesses 253662320 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 258916834 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 258916836 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 26137805 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedLoads 26137804 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed
@ -447,7 +447,7 @@ system.cpu.iew.iewBlockCycles 12496396 # Nu
system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 82787392 # Number of dispatched load instructions
system.cpu.iew.iewDispLoadInsts 82787391 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall
@ -456,19 +456,19 @@ system.cpu.iew.memOrderViolationEvents 303242 # Nu
system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 257339860 # Number of executed instructions
system.cpu.iew.iewExecutedInsts 257339863 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2057830 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecSquashedInsts 2057829 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 86369701 # number of memory reference insts executed
system.cpu.iew.exec_refs 86369702 # number of memory reference insts executed
system.cpu.iew.exec_branches 14330688 # Number of branches executed
system.cpu.iew.exec_stores 22285011 # Number of stores executed
system.cpu.iew.exec_stores 22285012 # Number of stores executed
system.cpu.iew.exec_rate 1.625832 # Inst execution rate
system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back
system.cpu.iew.wb_sent 256690837 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 256002023 # cumulative count of insts written-back
system.cpu.iew.wb_producers 204396158 # num instructions producing a value
system.cpu.iew.wb_consumers 369708067 # num instructions consuming a value
system.cpu.iew.wb_consumers 369708068 # num instructions consuming a value
system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit
@ -547,13 +547,13 @@ system.cpu.cpi 1.198459 # CP
system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads
system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 448575235 # number of integer regfile reads
system.cpu.int_regfile_reads 448575238 # number of integer regfile reads
system.cpu.int_regfile_writes 232602901 # number of integer regfile writes
system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads
system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes
system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads
system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes
system.cpu.misc_regfile_reads 132474844 # number of misc regfile reads
system.cpu.misc_regfile_reads 132474845 # number of misc regfile reads
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
system.cpu.dcache.tags.replacements 51 # number of replacements
system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use

3
tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
View file

@ -216,7 +216,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
@ -251,6 +251,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

12
tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simout
Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:45:42
gem5 started Jan 21 2016 14:46:23
gem5 executing on zizzer, pid 20742
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic
gem5 compiled Mar 14 2016 17:50:51
gem5 started Mar 14 2016 18:07:36
gem5 executing on phenom, pid 27152
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 48960011500 because target called exit()
Exiting @ tick 48960022500 because target called exit()

96
tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.048960 # Number of seconds simulated
sim_ticks 48960011500 # Number of ticks simulated
final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 48960022500 # Number of ticks simulated
final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 622932 # Simulator instruction rate (inst/s)
host_op_rate 796644 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 430085915 # Simulator tick rate (ticks/s)
host_mem_usage 246536 # Number of bytes of host memory used
host_seconds 113.84 # Real time elapsed on the host
sim_insts 70913182 # Number of instructions simulated
sim_ops 90688137 # Number of ops (including micro ops) simulated
host_inst_rate 991674 # Simulator instruction rate (inst/s)
host_op_rate 1268214 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 684673258 # Simulator tick rate (ticks/s)
host_mem_usage 242788 # Number of bytes of host memory used
host_seconds 71.51 # Real time elapsed on the host
sim_insts 70913204 # Number of instructions simulated
sim_ops 90688159 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 312580276 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory
system.physmem.bytes_read::total 419153621 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 312580276 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 312580276 # Number of instructions bytes read from this memory
system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory
system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 78145069 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory
system.physmem.num_reads::total 101064799 # Number of read requests responded to by this memory
system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory
system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6384399562 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2176742646 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8561142209 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6384399562 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6384399562 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1606621579 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1606621579 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6384399562 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3783364226 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10167763788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,33 +153,33 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 97920024 # number of cpu cycles simulated
system.cpu.numCycles 97920046 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70913182 # Number of instructions committed
system.cpu.committedOps 90688137 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
system.cpu.committedInsts 70913204 # Number of instructions committed
system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3311620 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls
system.cpu.num_int_insts 81528488 # number of integer instructions
system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls
system.cpu.num_int_insts 81528528 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read
system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
system.cpu.num_int_register_reads 141479386 # number of times the integer registers were read
system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_cc_register_reads 266608031 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written
system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 97920023.998000 # Number of busy cycles
system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741486 # Number of branches fetched
system.cpu.Branches 13741468 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690084 # Class of executed instruction
system.membus.trans_dist::ReadReq 100925136 # Transaction distribution
system.membus.trans_dist::ReadResp 100941055 # Transaction distribution
system.cpu.op_class::total 90690106 # Class of executed instruction
system.membus.trans_dist::ReadReq 100925158 # Transaction distribution
system.membus.trans_dist::ReadResp 100941077 # Transaction distribution
system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
system.membus.trans_dist::WriteResp 19849901 # Transaction distribution
system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution
@ -222,22 +222,22 @@ system.membus.trans_dist::SoftPFResp 123744 # Tr
system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution
system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution
system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290138 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 241861238 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580276 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 120930619 # Request fanout histogram
system.membus.snoop_fanout::samples 120930641 # Request fanout histogram
system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram
system.membus.snoop_fanout::1 78145069 64.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 78145091 64.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 120930619 # Request fanout histogram
system.membus.snoop_fanout::total 120930641 # Request fanout histogram
---------- End Simulation Statistics ----------

7
tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
View file

@ -90,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -168,7 +167,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -281,7 +279,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -316,6 +313,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -346,7 +344,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
@ -381,6 +379,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

12
tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:45:42
gem5 started Jan 21 2016 14:46:19
gem5 executing on zizzer, pid 20723
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
gem5 compiled Mar 14 2016 17:50:51
gem5 started Mar 14 2016 18:03:19
gem5 executing on phenom, pid 27037
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 128076812500 because target called exit()
Exiting @ tick 128076834500 because target called exit()

116
tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.128077 # Number of seconds simulated
sim_ticks 128076812500 # Number of ticks simulated
final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 128076834500 # Number of ticks simulated
final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 887065 # Simulator instruction rate (inst/s)
host_op_rate 1132533 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1614418321 # Simulator tick rate (ticks/s)
host_mem_usage 277452 # Number of bytes of host memory used
host_seconds 79.33 # Real time elapsed on the host
sim_insts 70373629 # Number of instructions simulated
sim_ops 89847363 # Number of ops (including micro ops) simulated
host_inst_rate 508798 # Simulator instruction rate (inst/s)
host_op_rate 649592 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 925989388 # Simulator tick rate (ticks/s)
host_mem_usage 253236 # Number of bytes of host memory used
host_seconds 138.31 # Real time elapsed on the host
sim_insts 70373651 # Number of instructions simulated
sim_ops 89847385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory
@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123832 # Nu
system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory
system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1820408 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 61878867 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 63699274 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1820408 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1820408 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 43049166 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 43049166 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 43049166 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1820408 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 61878867 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 106748441 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -154,33 +154,33 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 256153625 # number of cpu cycles simulated
system.cpu.numCycles 256153669 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70373629 # Number of instructions committed
system.cpu.committedOps 89847363 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
system.cpu.committedInsts 70373651 # Number of instructions committed
system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3311620 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls
system.cpu.num_int_insts 81528488 # number of integer instructions
system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls
system.cpu.num_int_insts 81528528 # number of integer instructions
system.cpu.num_fp_insts 56 # number of float instructions
system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read
system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
system.cpu.num_int_register_reads 141328550 # number of times the integer registers were read
system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_cc_register_reads 334802006 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written
system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 256153624.998000 # Number of busy cycles
system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741486 # Number of branches fetched
system.cpu.Branches 13741468 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690084 # Class of executed instruction
system.cpu.op_class::total 90690106 # Class of executed instruction
system.cpu.dcache.tags.replacements 155902 # number of replacements
system.cpu.dcache.tags.tagsinuse 4075.927151 # Cycle average of tags in use
system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927151 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -352,12 +352,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 16890 # number of replacements
system.cpu.icache.tags.tagsinuse 1732.356647 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356647 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id
@ -366,14 +366,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 22
system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 156309048 # Number of tag accesses
system.cpu.icache.tags.data_accesses 156309048 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 78126162 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78126162 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78126162 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 78126162 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 78126162 # number of overall hits
system.cpu.icache.overall_hits::total 78126162 # number of overall hits
system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses
system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits
system.cpu.icache.overall_hits::total 78126184 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses
@ -386,12 +386,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 426200500
system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 78145070 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 78145070 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 78145070 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses
@ -440,14 +440,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947
system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 95333 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30336.891349 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605172 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258764 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027413 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027343 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy

3
tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
View file

@ -115,7 +115,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
kvmInSE=false
@ -150,6 +150,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

12
tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simout
Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:30:54
gem5 started Jan 21 2016 14:31:25
gem5 executing on zizzer, pid 8713
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic
gem5 compiled Mar 14 2016 17:46:51
gem5 started Mar 14 2016 17:54:20
gem5 executing on phenom, pid 26843
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 68148672000 because target called exit()
Exiting @ tick 68148677000 because target called exit()

108
tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,69 +1,69 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.068149 # Number of seconds simulated
sim_ticks 68148672000 # Number of ticks simulated
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 68148677000 # Number of ticks simulated
final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1099944 # Simulator instruction rate (inst/s)
host_op_rate 1114186 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 557740246 # Simulator tick rate (ticks/s)
host_mem_usage 228968 # Number of bytes of host memory used
host_seconds 122.19 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
host_inst_rate 1843276 # Simulator instruction rate (inst/s)
host_op_rate 1867142 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 934655607 # Simulator tick rate (ticks/s)
host_mem_usage 225200 # Number of bytes of host memory used
host_seconds 72.91 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory
system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 538214280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 538214280 # Number of instructions bytes read from this memory
system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory
system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 134553570 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory
system.physmem.num_reads::total 171784870 # Number of read requests responded to by this memory
system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory
system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory
system.physmem.num_other::total 15916 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7897648835 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2165256573 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10062905408 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7897648835 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7897648835 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1318924454 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1318924454 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297345 # number of cpu cycles simulated
system.cpu.numCycles 136297355 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398962 # Number of instructions committed
system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
system.cpu.committedInsts 134398959 # Number of instructions committed
system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187746 # number of integer instructions
system.cpu.num_fp_insts 2326977 # number of float instructions
system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147734 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187757 # number of integer instructions
system.cpu.num_fp_insts 2326976 # number of float instructions
system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160248 # number of memory refs
system.cpu.num_load_insts 37275867 # Number of load instructions
system.cpu.num_store_insts 20884381 # Number of store instructions
system.cpu.num_mem_refs 58160261 # number of memory refs
system.cpu.num_load_insts 37275864 # Number of load instructions
system.cpu.num_store_insts 20884397 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 136297344.998000 # Number of busy cycles
system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12719095 # Number of branches fetched
system.cpu.Branches 12719094 # Number of branches fetched
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction
system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
@ -92,33 +92,33 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction
system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction
system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction
system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293798 # Class of executed instruction
system.membus.trans_dist::ReadReq 171784870 # Transaction distribution
system.membus.trans_dist::ReadResp 171784870 # Transaction distribution
system.cpu.op_class::total 136293808 # Class of executed instruction
system.membus.trans_dist::ReadReq 171784880 # Transaction distribution
system.membus.trans_dist::ReadResp 171784880 # Transaction distribution
system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
system.membus.trans_dist::WriteResp 20864304 # Transaction distribution
system.membus.trans_dist::SwapReq 15916 # Transaction distribution
system.membus.trans_dist::SwapResp 15916 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 192665090 # Request fanout histogram
system.membus.snoop_fanout::samples 192665100 # Request fanout histogram
system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram
system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 192665090 # Request fanout histogram
system.membus.snoop_fanout::total 192665100 # Request fanout histogram
---------- End Simulation Statistics ----------

7
tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -88,7 +88,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -130,7 +129,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -180,7 +178,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -215,6 +212,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -245,7 +243,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
kvmInSE=false
@ -280,6 +278,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

12
tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:30:54
gem5 started Jan 21 2016 14:31:26
gem5 executing on zizzer, pid 8734
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
gem5 compiled Mar 14 2016 17:46:51
gem5 started Mar 14 2016 17:55:53
gem5 executing on phenom, pid 26906
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 203115876500 because target called exit()
Exiting @ tick 203115946500 because target called exit()

446
tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,68 +1,68 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.203116 # Number of seconds simulated
sim_ticks 203115876500 # Number of ticks simulated
final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 203115946500 # Number of ticks simulated
final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1130669 # Simulator instruction rate (inst/s)
host_op_rate 1145309 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1708768878 # Simulator tick rate (ticks/s)
host_mem_usage 305928 # Number of bytes of host memory used
host_seconds 118.87 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
host_inst_rate 864116 # Simulator instruction rate (inst/s)
host_op_rate 875304 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1305930078 # Simulator tick rate (ticks/s)
host_mem_usage 235576 # Number of bytes of host memory used
host_seconds 155.53 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7828288 # Number of bytes read from this memory
system.physmem.bytes_read::total 8353344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory
system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory
system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122317 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130521 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory
system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2585007 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 38540995 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 41126002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2585007 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2585007 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 26867816 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 26867816 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 26867816 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2585007 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38540995 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67993818 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 406231753 # number of cpu cycles simulated
system.cpu.numCycles 406231893 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398962 # Number of instructions committed
system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
system.cpu.committedInsts 134398959 # Number of instructions committed
system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187746 # number of integer instructions
system.cpu.num_fp_insts 2326977 # number of float instructions
system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187757 # number of integer instructions
system.cpu.num_fp_insts 2326976 # number of float instructions
system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160248 # number of memory refs
system.cpu.num_load_insts 37275867 # Number of load instructions
system.cpu.num_store_insts 20884381 # Number of store instructions
system.cpu.num_mem_refs 58160261 # number of memory refs
system.cpu.num_load_insts 37275864 # Number of load instructions
system.cpu.num_store_insts 20884397 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 406231752.998000 # Number of busy cycles
system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12719095 # Number of branches fetched
system.cpu.Branches 12719094 # Number of branches fetched
system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction
system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
@ -91,18 +91,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction
system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction
system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction
system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293798 # Class of executed instruction
system.cpu.dcache.tags.replacements 146582 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.268920 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
system.cpu.op_class::total 136293808 # Class of executed instruction
system.cpu.dcache.tags.replacements 146583 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268920 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -110,38 +110,38 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 36
system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits
system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits
system.cpu.dcache.overall_hits::total 57944940 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
system.cpu.dcache.overall_misses::total 150663 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623254000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1623254000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 6329554500 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses
system.cpu.dcache.overall_misses::total 150664 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7952808500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7952808500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7952808500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7952808500 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593
system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35676.696191 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35676.696191 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.464341 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.464341 # average WriteReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52785.411813 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52785.411813 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -182,26 +182,26 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks
system.cpu.dcache.writebacks::total 123865 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577755000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577755000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802145500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7802145500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802145500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7802145500 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
@ -212,24 +212,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593
system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34676.696191 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34676.696191 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.464341 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.464341 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 184976 # number of replacements
system.cpu.icache.tags.tagsinuse 2004.181257 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 144582729500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181257 # Average occupied blocks per requestor
system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
@ -239,14 +239,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2
system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits
system.cpu.icache.overall_hits::total 134366547 # number of overall hits
system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses
system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits
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system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses
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@ -259,12 +259,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 2835239000
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system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses
@ -312,19 +312,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 99021 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30843.659201 # Cycle average of tags in use
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system.cpu.l2cache.tags.sampled_refs 130064 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.335519 # Average number of references to valid blocks.
system.cpu.l2cache.tags.replacements 99022 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use
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system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26289.730201 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863843 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id
@ -332,8 +332,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id
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system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses)
@ -382,38 +382,38 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179
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system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses)
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@ -430,115 +430,115 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264
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system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747399 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747399 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 669260 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 331558 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 36468 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447938 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1006962 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 41378752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 99021 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 436723 # Request fanout histogram
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 99022 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 433110 99.17% 99.17% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 436723 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 643471000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 29257 # Transaction distribution
system.membus.trans_dist::ReadResp 29258 # Transaction distribution
system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution
system.membus.trans_dist::CleanEvict 10300 # Transaction distribution
system.membus.trans_dist::CleanEvict 10301 # Transaction distribution
system.membus.trans_dist::ReadExReq 101264 # Transaction distribution
system.membus.trans_dist::ReadExResp 101264 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 29257 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356612 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 356612 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13810624 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 226091 # Request fanout histogram
system.membus.snoop_fanout::samples 226093 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 226091 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 226091 # Request fanout histogram
system.membus.reqLayer0.occupancy 568572500 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 226093 # Request fanout histogram
system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 652605000 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------