2011-02-08 04:23:11 +01:00
---------- Begin Simulation Statistics ----------
2015-09-25 13:27:03 +02:00
sim_seconds 2.909343 # Number of seconds simulated
sim_ticks 2909343316500 # Number of ticks simulated
final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-02-08 04:23:11 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-09-25 13:27:03 +02:00
host_inst_rate 666869 # Simulator instruction rate (inst/s)
host_op_rate 804035 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17251437084 # Simulator tick rate (ticks/s)
host_mem_usage 624248 # Number of bytes of host memory used
host_seconds 168.64 # Real time elapsed on the host
sim_insts 112463069 # Number of instructions simulated
sim_ops 135595282 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2014-10-30 05:18:29 +01:00
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
2015-09-25 13:27:03 +02:00
system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 166592 # Number of read requests accepted
system.physmem.writeReqs 121840 # Number of write requests accepted
system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
2015-09-25 13:27:03 +02:00
system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10226 # Per bank write bursts
system.physmem.perBankRdBursts::1 9700 # Per bank write bursts
system.physmem.perBankRdBursts::2 10356 # Per bank write bursts
system.physmem.perBankRdBursts::3 10496 # Per bank write bursts
system.physmem.perBankRdBursts::4 18505 # Per bank write bursts
system.physmem.perBankRdBursts::5 10022 # Per bank write bursts
system.physmem.perBankRdBursts::6 10179 # Per bank write bursts
system.physmem.perBankRdBursts::7 10614 # Per bank write bursts
system.physmem.perBankRdBursts::8 9478 # Per bank write bursts
system.physmem.perBankRdBursts::9 10041 # Per bank write bursts
system.physmem.perBankRdBursts::10 9320 # Per bank write bursts
system.physmem.perBankRdBursts::11 9342 # Per bank write bursts
system.physmem.perBankRdBursts::12 9424 # Per bank write bursts
system.physmem.perBankRdBursts::13 10229 # Per bank write bursts
system.physmem.perBankRdBursts::14 9340 # Per bank write bursts
system.physmem.perBankRdBursts::15 9201 # Per bank write bursts
system.physmem.perBankWrBursts::0 7577 # Per bank write bursts
system.physmem.perBankWrBursts::1 7036 # Per bank write bursts
system.physmem.perBankWrBursts::2 7887 # Per bank write bursts
system.physmem.perBankWrBursts::3 8049 # Per bank write bursts
system.physmem.perBankWrBursts::4 7151 # Per bank write bursts
system.physmem.perBankWrBursts::5 7579 # Per bank write bursts
system.physmem.perBankWrBursts::6 7566 # Per bank write bursts
system.physmem.perBankWrBursts::7 7770 # Per bank write bursts
system.physmem.perBankWrBursts::8 7275 # Per bank write bursts
system.physmem.perBankWrBursts::9 7619 # Per bank write bursts
system.physmem.perBankWrBursts::10 6810 # Per bank write bursts
system.physmem.perBankWrBursts::11 7097 # Per bank write bursts
system.physmem.perBankWrBursts::12 7200 # Per bank write bursts
system.physmem.perBankWrBursts::13 7753 # Per bank write bursts
system.physmem.perBankWrBursts::14 6925 # Per bank write bursts
system.physmem.perBankWrBursts::15 6640 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-09-25 13:27:03 +02:00
system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
system.physmem.totGap 2909342872000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::6 157020 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.writePktSize::6 117459 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::15 2057 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2393 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6014 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5882 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6380 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7267 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6822 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7809 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7803 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9329 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6661 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6301 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6059 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5924 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::39 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
2015-09-25 13:27:03 +02:00
system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads
system.physmem.totQLat 1636363750 # Total ticks spent queuing
system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-03-02 11:04:20 +01:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2014-10-30 05:18:29 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2015-09-25 13:27:03 +02:00
system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing
system.physmem.readRowHits 136200 # Number of row buffer hits during reads
system.physmem.writeRowHits 89619 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes
system.physmem.avgGap 10086754.84 # Average gap between requests
system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.621597 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states
system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.478544 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states
system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-11-03 17:14:42 +01:00
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu.dtb.walker.walks 9555 # Table walker walks requested
system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2015-09-25 13:27:03 +02:00
system.cpu.dtb.read_hits 24521784 # DTB read hits
system.cpu.dtb.read_misses 8135 # DTB read misses
system.cpu.dtb.write_hits 19607400 # DTB write hits
system.cpu.dtb.write_misses 1420 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-09-25 13:27:03 +02:00
system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2014-10-30 05:18:29 +01:00
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
2015-09-25 13:27:03 +02:00
system.cpu.dtb.read_accesses 24529919 # DTB read accesses
system.cpu.dtb.write_accesses 19608820 # DTB write accesses
2011-02-08 04:23:11 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2015-09-25 13:27:03 +02:00
system.cpu.dtb.hits 44129184 # DTB hits
system.cpu.dtb.misses 9555 # DTB misses
system.cpu.dtb.accesses 44138739 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walks 4763 # Table walker walks requested
system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 115560644 # ITB inst hits
system.cpu.itb.inst_misses 4763 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2015-09-25 13:27:03 +02:00
system.cpu.itb.inst_accesses 115565407 # ITB inst accesses
system.cpu.itb.hits 115560644 # DTB hits
system.cpu.itb.misses 4763 # DTB misses
system.cpu.itb.accesses 115565407 # DTB accesses
system.cpu.numCycles 5818686633 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-25 13:27:03 +02:00
system.cpu.committedInsts 112463069 # Number of instructions committed
system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses
2015-03-02 11:04:20 +01:00
system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
2015-09-25 13:27:03 +02:00
system.cpu.num_func_calls 9893453 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls
system.cpu.num_int_insts 119900050 # number of integer instructions
2015-03-02 11:04:20 +01:00
system.cpu.num_fp_insts 11161 # number of float instructions
2015-09-25 13:27:03 +02:00
system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read
system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written
2015-03-02 11:04:20 +01:00
system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
2014-10-30 05:18:29 +01:00
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
2015-09-25 13:27:03 +02:00
system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read
system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written
system.cpu.num_mem_refs 45409486 # number of memory refs
system.cpu.num_load_insts 24844046 # Number of load instructions
system.cpu.num_store_insts 20565440 # Number of store instructions
system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles
system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles
system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.924573 # Percentage of idle cycles
system.cpu.Branches 25918657 # Number of branches fetched
2014-10-30 05:18:29 +01:00
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
2015-09-25 13:27:03 +02:00
system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction
system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction
2014-10-30 05:18:29 +01:00
system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
2015-07-03 16:15:03 +02:00
system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Class of executed instruction
2014-10-30 05:18:29 +01:00
system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
2015-09-25 13:27:03 +02:00
system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction
system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2015-09-25 13:27:03 +02:00
system.cpu.op_class::total 138715716 # Class of executed instruction
2011-08-19 22:08:09 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2015-09-25 13:27:03 +02:00
system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
system.cpu.dcache.tags.replacements 821347 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.tag_accesses 177121649 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 177121649 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23112263 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23112263 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18824569 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18824569 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 392807 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 392807 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443229 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460200 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460200 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 41936832 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41936832 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42329639 # number of overall hits
system.cpu.dcache.overall_hits::total 42329639 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 401818 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 401818 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 298972 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 298972 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 118323 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_misses::cpu.data 700790 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 700790 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 819113 # number of overall misses
system.cpu.dcache.overall_misses::total 819113 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6512815000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6512815000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19103648000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 19103648000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294606000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 294606000 # number of LoadLockedReq miss cycles
2015-03-02 11:04:20 +01:00
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 25616463000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 25616463000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 25616463000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 25616463000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23514081 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23514081 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19123541 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19123541 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511130 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511130 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465986 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 465986 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460202 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460202 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42637622 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42637622 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43148752 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43148752 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017088 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.017088 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015634 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015634 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231493 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.231493 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048836 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.016436 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016436 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.018983 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.018983 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16208.370456 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16208.370456 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63897.783070 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63897.783070 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12945.730984 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12945.730984 # average LoadLockedReq miss latency
2015-03-02 11:04:20 +01:00
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36553.693689 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36553.693689 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31273.417709 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31273.417709 # average overall miss latency
2015-07-03 16:15:03 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu.dcache.writebacks::writebacks 685107 # number of writebacks
system.cpu.dcache.writebacks::total 685107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 939 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 939 # number of ReadReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14240 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14240 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 939 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 939 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 939 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 939 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400879 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 400879 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298972 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 298972 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116280 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 116280 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8517 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8517 # number of LoadLockedReq MSHR misses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 699851 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 699851 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 816131 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 816131 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080968000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080968000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18804676000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 18804676000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1617499500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1617499500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115437000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115437000 # number of LoadLockedReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24885644000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 24885644000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26503143500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26503143500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5936758500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5936758500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4791465500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4791465500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10728224000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10728224000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017048 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017048 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015634 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015634 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227496 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227496 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018277 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018277 # mshr miss rate for LoadLockedReq accesses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016414 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016414 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018914 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.018914 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15169.085934 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15169.085934 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62897.783070 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62897.783070 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13910.384417 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13910.384417 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13553.716097 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13553.716097 # average LoadLockedReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35558.488878 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35558.488878 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32474.129153 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32474.129153 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190659.595992 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.595992 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173673.039980 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173673.039980 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.585199 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.585199 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.replacements 1696276 # number of replacements
system.cpu.icache.tags.tagsinuse 510.440576 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 113863850 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1696788 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 67.105525 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 28967481500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.440576 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996954 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.tag_accesses 117257438 # Number of tag accesses
system.cpu.icache.tags.data_accesses 117257438 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 113863850 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 113863850 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 113863850 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 113863850 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 113863850 # number of overall hits
system.cpu.icache.overall_hits::total 113863850 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1696794 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1696794 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1696794 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1696794 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1696794 # number of overall misses
system.cpu.icache.overall_misses::total 1696794 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24262817500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 24262817500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 24262817500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 24262817500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 24262817500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 24262817500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 115560644 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 115560644 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 115560644 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 115560644 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 115560644 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 115560644 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014683 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014683 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014683 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014683 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014683 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014683 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14299.212220 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14299.212220 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14299.212220 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14299.212220 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696794 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1696794 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1696794 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1696794 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1696794 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1696794 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22566023500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 22566023500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22566023500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 22566023500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22566023500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22566023500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13299.212220 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13299.212220 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.replacements 87598 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64865.821065 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4548879 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 152768 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 29.776386 # Average number of references to valid blocks.
2014-11-12 15:05:25 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 50190.412542 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.801705 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012642 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9659.374197 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5012.219980 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.765845 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147390 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.076480 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.989774 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6804 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 40555786 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40555786 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7774 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4032 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 11806 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 685107 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 685107 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 167410 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 167410 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678817 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1678817 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513395 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 513395 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7774 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 4032 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1678817 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 680805 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2371428 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7774 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 4032 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1678817 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 680805 # number of overall hits
system.cpu.l2cache.overall_hits::total 2371428 # number of overall hits
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2735 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2735 # number of UpgradeReq misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 128803 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 128803 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17954 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 17954 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12281 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 12281 # number of ReadSharedReq misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 17954 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 141084 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 159047 # number of demand (read+write) misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 17954 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 141084 # number of overall misses
system.cpu.l2cache.overall_misses::total 159047 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 929000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1195000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1856500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1856500 # number of UpgradeReq miss cycles
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16377126500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16377126500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2358568000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2358568000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1624402500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1624402500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 929000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2358568000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 18001529000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20361292000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 929000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2358568000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 18001529000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20361292000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7781 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4034 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 11815 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 685107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 685107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2759 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2759 # number of UpgradeReq accesses(hits+misses)
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 296213 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 296213 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696771 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1696771 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525676 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 525676 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7781 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 4034 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1696771 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 821889 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2530475 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7781 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 4034 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1696771 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 821889 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2530475 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000900 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000496 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000762 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991301 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991301 # miss rate for UpgradeReq accesses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.434832 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.434832 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010581 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010581 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023362 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023362 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000900 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000496 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010581 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.171658 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.062853 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000900 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000496 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010581 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.171658 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.062853 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 132714.285714 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 132777.777778 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 678.793419 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 678.793419 # average UpgradeReq miss latency
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127148.641724 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127148.641724 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131367.271917 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131367.271917 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132269.562739 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132269.562739 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 132714.285714 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131367.271917 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127594.404752 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 128020.597685 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 132714.285714 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131367.271917 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127594.404752 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 128020.597685 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.writebacks::writebacks 81269 # number of writebacks
system.cpu.l2cache.writebacks::total 81269 # number of writebacks
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2735 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2735 # number of UpgradeReq MSHR misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128803 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 128803 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17954 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17954 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12281 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12281 # number of ReadSharedReq MSHR misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 17954 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 141084 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 159047 # number of demand (read+write) MSHR misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 17954 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141084 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 159047 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 859000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1105000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 193639500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 193639500 # number of UpgradeReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15089096500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15089096500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2179028000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2179028000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1501592500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1501592500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 859000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2179028000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16590689000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18770822000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 859000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2179028000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16590689000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18770822000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5547532500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6577298500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4474192000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4474192000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10021724500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11051490500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000762 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991301 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991301 # mshr miss rate for UpgradeReq accesses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.434832 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.434832 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010581 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023362 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023362 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.062853 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.062853 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 175948 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.trans_dist::ReadReq 30177 # Transaction distribution
system.iobus.trans_dist::ReadResp 30177 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iocache.tags.replacements 36418 # number of replacements
system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.iocache.tags.tag_accesses 328068 # Number of tag accesses
system.iocache.tags.data_accesses 328068 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses
system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2015-09-25 13:27:03 +02:00
system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
system.iocache.demand_misses::total 228 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 228 # number of overall misses
system.iocache.overall_misses::total 228 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency
2015-07-03 16:15:03 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2011-08-19 22:08:09 +02:00
system.iocache.cache_copies 0 # number of cache copies performed
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2015-09-25 13:27:03 +02:00
system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
system.membus.trans_dist::ReadResp 70632 # Transaction distribution
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
system.membus.trans_dist::WriteResp 27589 # Transaction distribution
system.membus.trans_dist::Writeback 117459 # Transaction distribution
system.membus.trans_dist::CleanEvict 6342 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution
2014-11-12 15:05:25 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution
system.membus.trans_dist::ReadExReq 127038 # Transaction distribution
system.membus.trans_dist::ReadExResp 127038 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 492 # Total snoops (count)
system.membus.snoop_fanout::samples 390004 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::total 390004 # Request fanout histogram
system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-09-25 13:27:03 +02:00
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
2015-08-07 16:39:17 +02:00
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
2011-02-08 04:23:11 +01:00
---------- End Simulation Statistics ----------
