2011-02-05 09:16:09 +01:00
---------- Begin Simulation Statistics ----------
2015-09-15 15:14:09 +02:00
sim_seconds 0.061602 # Number of seconds simulated
2015-11-06 09:26:50 +01:00
sim_ticks 61602281500 # Number of ticks simulated
final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-02-05 09:16:09 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-03-17 18:30:58 +01:00
host_inst_rate 60207 # Simulator instruction rate (inst/s)
host_op_rate 106015 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23475786 # Simulator tick rate (ticks/s)
host_mem_usage 445092 # Number of bytes of host memory used
host_seconds 2624.08 # Real time elapsed on the host
2012-08-15 16:38:05 +02:00
sim_insts 157988547 # Number of instructions simulated
2013-03-11 23:45:09 +01:00
sim_ops 278192464 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-09-15 15:14:09 +02:00
system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory
2016-03-17 18:30:58 +01:00
system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory
system.physmem.bytes_read::total 1946944 # Number of bytes read from this memory
2015-09-15 15:14:09 +02:00
system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory
system.physmem.bytes_written::total 12160 # Number of bytes written to this memory
2015-09-15 15:14:09 +02:00
system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory
2016-03-17 18:30:58 +01:00
system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory
system.physmem.num_reads::total 30421 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory
system.physmem.num_writes::total 190 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s)
2016-03-17 18:30:58 +01:00
system.physmem.bw_read::cpu.data 30568218 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 31605063 # Total read bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s)
2016-03-17 18:30:58 +01:00
system.physmem.bw_total::cpu.data 30568218 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 31802458 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 30421 # Number of read requests accepted
2015-11-06 09:26:50 +01:00
system.physmem.writeReqs 190 # Number of write requests accepted
2016-03-17 18:30:58 +01:00
system.physmem.readBursts 30421 # Number of DRAM read bursts, including those serviced by the write queue
2015-11-06 09:26:50 +01:00
system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue
2016-03-17 18:30:58 +01:00
system.physmem.bytesReadDRAM 1941440 # Total number of bytes read from DRAM
2015-11-06 09:26:50 +01:00
system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue
system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM
2016-03-17 18:30:58 +01:00
system.physmem.bytesReadSys 1946944 # Total read bytes from the system interface side
2015-11-06 09:26:50 +01:00
system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue
2015-09-15 15:14:09 +02:00
system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::0 1928 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::1 2059 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::2 2023 # Per bank write bursts
system.physmem.perBankRdBursts::3 1928 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::4 2025 # Per bank write bursts
2015-07-03 16:15:03 +02:00
system.physmem.perBankRdBursts::5 1901 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::6 1952 # Per bank write bursts
system.physmem.perBankRdBursts::7 1864 # Per bank write bursts
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::8 1938 # Per bank write bursts
2016-03-17 18:30:58 +01:00
system.physmem.perBankRdBursts::9 1931 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::10 1804 # Per bank write bursts
system.physmem.perBankRdBursts::11 1794 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::14 1818 # Per bank write bursts
2015-07-03 16:15:03 +02:00
system.physmem.perBankRdBursts::15 1778 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankWrBursts::0 10 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankWrBursts::1 78 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankWrBursts::2 7 # Per bank write bursts
system.physmem.perBankWrBursts::3 28 # Per bank write bursts
system.physmem.perBankWrBursts::4 6 # Per bank write bursts
system.physmem.perBankWrBursts::5 7 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankWrBursts::6 16 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
2015-07-03 16:15:03 +02:00
system.physmem.perBankWrBursts::9 5 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::10 3 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-11-06 09:26:50 +01:00
system.physmem.totGap 61602096500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-03-17 18:30:58 +01:00
system.physmem.readPktSize::6 30421 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.writePktSize::6 190 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see
2016-03-17 18:30:58 +01:00
system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation
2016-03-17 18:30:58 +01:00
system.physmem.bytesPerActivate::mean 716.466005 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 515.355667 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 387.992511 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 365 13.41% 13.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 230 8.45% 21.87% # Bytes accessed per row activation
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 132 4.85% 39.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 112 4.12% 43.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes
2016-03-17 18:30:58 +01:00
system.physmem.rdPerTurnAround::mean 3363.666667 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 10055.376646 # Reads before turning the bus around for writes
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::mean 17.777778 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.765969 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.666667 # Writes before turning the bus around for reads
2015-09-15 15:14:09 +02:00
system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads
2015-07-03 16:15:03 +02:00
system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.totQLat 133021500 # Total ticks spent queuing
2016-03-17 18:30:58 +01:00
system.physmem.totMemAccLat 701802750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 151675000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4385.08 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-03-17 18:30:58 +01:00
system.physmem.avgMemAccLat 23135.08 # Average memory access latency per DRAM burst
2015-09-15 15:14:09 +02:00
system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s
2015-09-15 15:14:09 +02:00
system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2014-09-03 13:42:59 +02:00
system.physmem.busUtil 0.25 # Data bus utilization in percentage
2015-09-15 15:14:09 +02:00
system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-09-15 15:14:09 +02:00
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
2015-11-06 09:26:50 +01:00
system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing
2016-03-17 18:30:58 +01:00
system.physmem.readRowHits 27658 # Number of row buffer hits during reads
2015-11-06 09:26:50 +01:00
system.physmem.writeRowHits 106 # Number of row buffer hits during writes
2015-09-15 15:14:09 +02:00
system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads
2015-11-06 09:26:50 +01:00
system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes
2016-03-17 18:30:58 +01:00
system.physmem.avgGap 2012416.99 # Average gap between requests
2015-11-06 09:26:50 +01:00
system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined
2015-09-15 15:14:09 +02:00
system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.readEnergy 121984200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 984960 # Energy for write commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.actBackEnergy 2835924705 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34470717000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41469713850 # Total energy per rank (pJ)
system.physmem_0.averagePower 673.239327 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57330547250 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::ACT 2211196750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ)
2016-03-17 18:30:58 +01:00
system.physmem_1.readEnergy 114199800 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ)
2016-03-17 18:30:58 +01:00
system.physmem_1.totalEnergy 41481566430 # Total energy per rank (pJ)
system.physmem_1.averagePower 673.431898 # Core power per rank (mW)
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::ACT 2480893250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.lookups 36908905 # Number of BP lookups
system.cpu.branchPred.condPredicted 36908905 # Number of conditional branches predicted
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.BTBLookups 21094596 # Number of BTB lookups
system.cpu.branchPred.BTBHits 21013333 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.usedRAS 5443330 # Number of times the RAS was used to get a target.
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.RASInCorrect 4414 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 444 # Number of system calls
2015-11-06 09:26:50 +01:00
system.cpu.numCycles 123204564 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu.fetch.icacheStallCycles 27815555 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 199030250 # Number of instructions fetch has processed
system.cpu.fetch.Branches 36908905 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 26456663 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 94541896 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1553195 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 5275 # Number of stall cycles due to pending traps
2015-07-03 16:15:03 +02:00
system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
2015-11-06 09:26:50 +01:00
system.cpu.fetch.CacheLines 27443897 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 182895 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 123139703 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.847279 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.366421 # Number of instructions fetched each cycle (Total)
2011-02-05 09:16:09 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::0 62945303 51.12% 51.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3649645 2.96% 54.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3480674 2.83% 56.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 5913881 4.80% 61.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 7544216 6.13% 67.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5413971 4.40% 72.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3251108 2.64% 74.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2020095 1.64% 76.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 28920810 23.49% 100.00% # Number of instructions fetched each cycle (Total)
2011-02-05 09:16:09 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::total 123139703 # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.branchRate 0.299574 # Number of branch fetches per cycle
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rate 1.615445 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12941515 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 63708297 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 35887575 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9825719 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 776597 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 331225446 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 776597 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 18253426 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 8529207 # Number of cycles rename is blocking
2015-09-15 15:14:09 +02:00
system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst
2015-11-06 09:26:50 +01:00
system.cpu.rename.RunCycles 40202725 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 55360957 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 325142954 # Number of instructions processed by rename
2015-09-15 15:14:09 +02:00
system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full
2015-11-06 09:26:50 +01:00
system.cpu.rename.IQFullEvents 778303 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 48626694 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 4947433 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 327068188 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 863737810 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 532004029 # Number of integer rename lookups
2015-09-15 15:14:09 +02:00
system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups
2013-03-11 23:45:09 +01:00
system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
2015-11-06 09:26:50 +01:00
system.cpu.rename.UndoneMaps 47855441 # Number of HB maps that are undone due to squashing
2015-09-15 15:14:09 +02:00
system.cpu.rename.serializingInsts 492 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed
2015-11-06 09:26:50 +01:00
system.cpu.rename.skidInsts 66412323 # count of insts added to the skid buffer
2015-09-15 15:14:09 +02:00
system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit.
2015-11-06 09:26:50 +01:00
system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit.
2016-02-10 10:08:27 +01:00
system.cpu.memDep0.conflictingLoads 49401722 # Number of conflicting loads.
2015-11-06 09:26:50 +01:00
system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores.
2016-02-10 10:08:27 +01:00
system.cpu.iq.iqInstsAdded 322301392 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2340 # Number of non-speculative instructions added to the IQ
2015-11-06 09:26:50 +01:00
system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling
2016-03-17 18:30:58 +01:00
system.cpu.iq.iqSquashedOperandsExamined 63882734 # Number of squashed operands that are examined and possibly removed from graph
2016-02-10 10:08:27 +01:00
system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::0 30259811 24.57% 24.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 19566759 15.89% 40.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 16687041 13.55% 54.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 17331203 14.07% 68.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 14759381 11.99% 80.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 12567446 10.21% 90.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 6273248 5.09% 95.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3904177 3.17% 98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1790637 1.45% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::total 123139703 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::IntAlu 338800 8.53% 8.53% # attempts to use FU when none available
2015-09-15 15:14:09 +02:00
system.cpu.iq.fu_full::IntMult 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 197610 4.98% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::IntAlu 174121950 56.88% 56.89% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::total 306103027 # Type of FU issued
system.cpu.iq.rate 2.484510 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3969927 # FU busy when requested
2015-09-15 15:14:09 +02:00
system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst)
2015-11-06 09:26:50 +01:00
system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes
2016-03-17 18:30:58 +01:00
system.cpu.iq.int_inst_queue_wakeup_accesses 304282658 # Number of integer instruction queue wakeup accesses
2015-09-15 15:14:09 +02:00
system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses
2015-11-06 09:26:50 +01:00
system.cpu.iq.int_alu_accesses 310039433 # Number of integer alu accesses
2015-09-15 15:14:09 +02:00
system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.forwLoads 58196288 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.squashedStores 4729640 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.cacheBlocked 141544 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewSquashCycles 776597 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 5329160 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 3100599 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 322303732 # Number of instructions dispatched to IQ
2015-09-15 15:14:09 +02:00
system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewDispStoreInsts 36169392 # Number of dispatched store instructions
2016-02-10 10:08:27 +01:00
system.cpu.iew.iewDispNonSpecInsts 1101 # Number of dispatched non-speculative instructions
2015-09-15 15:14:09 +02:00
system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewLSQFullEvents 3102623 # Number of times the LSQ has become full, causing a stall
2015-09-15 15:14:09 +02:00
system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly
2015-11-06 09:26:50 +01:00
system.cpu.iew.predictedNotTakenIncorrect 414776 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 786455 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 305156727 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 97750586 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 946300 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
2015-11-06 09:26:50 +01:00
system.cpu.iew.exec_refs 131430384 # number of memory reference insts executed
system.cpu.iew.exec_branches 31401849 # Number of branches executed
2015-09-15 15:14:09 +02:00
system.cpu.iew.exec_stores 33679798 # Number of stores executed
2015-11-06 09:26:50 +01:00
system.cpu.iew.exec_rate 2.476830 # Inst execution rate
2016-03-17 18:30:58 +01:00
system.cpu.iew.wb_sent 304565843 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 304282791 # cumulative count of insts written-back
2015-11-06 09:26:50 +01:00
system.cpu.iew.wb_producers 230213909 # num instructions producing a value
2016-02-10 10:08:27 +01:00
system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value
2015-11-06 09:26:50 +01:00
system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle
2016-02-10 10:08:27 +01:00
system.cpu.iew.wb_fanout 0.689551 # average fanout of values written-back
2015-11-06 09:26:50 +01:00
system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
2015-11-06 09:26:50 +01:00
system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 117118936 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.375299 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 3.092759 # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::0 52925822 45.19% 45.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 15815600 13.50% 58.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 10978628 9.37% 68.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8749337 7.47% 75.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1860126 1.59% 77.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1720772 1.47% 78.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 865935 0.74% 79.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 690105 0.59% 79.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 23512611 20.08% 100.00% # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::total 117118936 # Number of insts commited each cycle
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
2013-03-11 23:45:09 +01:00
system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 122219137 # Number of memory references committed
system.cpu.commit.loads 90779385 # Number of loads committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 29309705 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 278169481 # Number of committed integer instructions.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 4237596 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.bw_lim_events 23512611 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 416008479 # The number of ROB reads
system.cpu.rob.rob_writes 650833820 # The number of ROB writes
2015-09-15 15:14:09 +02:00
system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself
2015-11-06 09:26:50 +01:00
system.cpu.idleCycles 64861 # Total number of cycles that the CPU has spent unscheduled due to idling
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
2013-03-11 23:45:09 +01:00
system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
2015-11-06 09:26:50 +01:00
system.cpu.cpi 0.779832 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.779832 # CPI: Total CPI of All Threads
system.cpu.ipc 1.282327 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.282327 # IPC: Total IPC of All Threads
2016-03-17 18:25:11 +01:00
system.cpu.int_regfile_reads 491477136 # number of integer regfile reads
2015-11-06 09:26:50 +01:00
system.cpu.int_regfile_writes 239432261 # number of integer regfile writes
2015-09-15 15:14:09 +02:00
system.cpu.fp_regfile_reads 110 # number of floating regfile reads
system.cpu.fp_regfile_writes 84 # number of floating regfile writes
2015-11-06 09:26:50 +01:00
system.cpu.cc_regfile_reads 107533030 # number of cc regfile reads
2015-09-15 15:14:09 +02:00
system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes
2015-11-06 09:26:50 +01:00
system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads
2013-03-11 23:45:09 +01:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.replacements 2072312 # number of replacements
system.cpu.dcache.tags.tagsinuse 4068.008256 # Cycle average of tags in use
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks.
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.sampled_refs 2076408 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 32.783074 # Average number of references to valid blocks.
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit.
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4068.008256 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993166 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993166 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-03-17 18:30:58 +01:00
system.cpu.dcache.tags.tag_accesses 143788642 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 143788642 # Number of data accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31345825 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 68071037 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits
system.cpu.dcache.overall_hits::total 68071037 # number of overall hits
2016-03-17 18:30:58 +01:00
system.cpu.dcache.ReadReq_misses::cpu.data 2691153 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2691153 # number of ReadReq misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_misses::cpu.data 2785080 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2785080 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2785080 # number of overall misses
system.cpu.dcache.overall_misses::total 2785080 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304195500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 32304195500 # number of ReadReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 35260810494 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35260810494 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35260810494 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35260810494 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 39416365 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 39416365 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_accesses::cpu.data 70856117 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 70856117 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 70856117 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 70856117 # number of overall (read+write) accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465 # average ReadReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 12660.609567 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12660.609567 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124387 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-09-15 15:14:09 +02:00
system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks
system.cpu.dcache.writebacks::total 2066601 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 708671 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits
2016-03-17 18:30:58 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994365 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1994365 # number of ReadReq MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 2076409 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2076409 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2076409 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2076409 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195923000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195923000 # number of ReadReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995319995 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26995319995 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995319995 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26995319995 # number of overall MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.143815 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.143815 # average ReadReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency
2016-03-17 18:30:58 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.replacements 53 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27442574 # Total number of references to valid blocks.
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.avg_refs 27090.398815 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 825.039758 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.402851 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.402851 # Average percentage of cache occupancy
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tag_accesses 54888808 # Number of tag accesses
system.cpu.icache.tags.data_accesses 54888808 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27442574 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27442574 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27442574 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27442574 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27442574 # number of overall hits
system.cpu.icache.overall_hits::total 27442574 # number of overall hits
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_misses::cpu.inst 1323 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1323 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1323 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses
system.cpu.icache.overall_misses::total 1323 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 97204000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 97204000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 97204000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 97204000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 97204000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 97204000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27443897 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27443897 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27443897 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27443897 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27443897 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27443897 # number of overall (read+write) accesses
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73472.411187 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 73472.411187 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 73472.411187 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 73472.411187 # average overall miss latency
2015-09-15 15:14:09 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 53 # number of writebacks
system.cpu.icache.writebacks::total 53 # number of writebacks
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1014 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77418000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 77418000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77418000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 77418000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77418000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 77418000 # number of overall MSHR miss cycles
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.replacements 493 # number of replacements
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.tagsinuse 20711.322176 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4035102 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 30410 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 132.689970 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.data 244.920687 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.603990 # Average percentage of cache occupancy
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007474 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.632059 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29917 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27622 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.912994 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 33310456 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 33310456 # Number of data accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackDirty_hits::writebacks 2066601 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2066601 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 53 # number of WritebackClean hits
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 53071 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 53071 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1993914 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1993914 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2046985 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2047001 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2046985 # number of overall hits
system.cpu.l2cache.overall_hits::total 2047001 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 998 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 998 # number of ReadCleanReq misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 425 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 425 # number of ReadSharedReq misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_misses::cpu.data 29423 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 30421 # number of demand (read+write) misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_misses::cpu.data 29423 # number of overall misses
system.cpu.l2cache.overall_misses::total 30421 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118138000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2118138000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75717000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 75717000 # number of ReadCleanReq miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32635000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 32635000 # number of ReadSharedReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 75717000 # number of demand (read+write) miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.data 2150773000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 2226490000 # number of demand (read+write) miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 75717000 # number of overall miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.data 2150773000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 2226490000 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066601 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2066601 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 53 # number of WritebackClean accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 82069 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1014 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1014 # number of ReadCleanReq accesses(hits+misses)
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994339 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1994339 # number of ReadSharedReq accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 2076408 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2077422 # number of demand (read+write) accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 2076408 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2077422 # number of overall (read+write) accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353337 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.353337 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.984221 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.984221 # miss rate for ReadCleanReq accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000213 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000213 # miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984221 # miss rate for demand accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475 # average ReadCleanReq miss latency
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76788.235294 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76788.235294 # average ReadSharedReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73189.244272 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73189.244272 # average overall miss latency
2012-01-29 02:09:17 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-02-05 09:16:09 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2012-01-29 02:09:17 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
2011-02-05 09:16:09 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.writebacks::writebacks 190 # number of writebacks
system.cpu.l2cache.writebacks::total 190 # number of writebacks
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 998 # number of ReadCleanReq MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 425 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 425 # number of ReadSharedReq MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 998 # number of demand (read+write) MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 29423 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 30421 # number of demand (read+write) MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 29423 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 30421 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828158000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828158000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65737000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65737000 # number of ReadCleanReq MSHR miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28385000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28385000 # number of ReadSharedReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65737000 # number of demand (read+write) MSHR miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856543000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1922280000 # number of demand (read+write) MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856543000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1922280000 # number of overall MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000213 # mshr miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66788.235294 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66788.235294 # average ReadSharedReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency
2016-03-17 18:30:58 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 4149788 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072369 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 1995353 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::CleanEvict 6014 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994339 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225130 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 6227211 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152576 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 265220864 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoops 493 # Total snoops (count)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 2077916 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2077591 99.98% 99.98% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.snoop_fanout::total 2077916 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4141548000 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3114612500 # Layer occupancy (ticks)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.membus.trans_dist::ReadResp 1423 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::WritebackDirty 190 # Transaction distribution
system.membus.trans_dist::CleanEvict 24 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadExReq 28998 # Transaction distribution
system.membus.trans_dist::ReadExResp 28998 # Transaction distribution
2016-03-17 18:30:58 +01:00
system.membus.trans_dist::ReadSharedReq 1423 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61056 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61056 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 61056 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959104 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959104 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1959104 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-03-17 18:30:58 +01:00
system.membus.snoop_fanout::samples 30635 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.membus.snoop_fanout::0 30635 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-03-17 18:30:58 +01:00
system.membus.snoop_fanout::total 30635 # Request fanout histogram
system.membus.reqLayer0.occupancy 42769000 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-03-17 18:30:58 +01:00
system.membus.respLayer1.occupancy 160316500 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
2011-02-05 09:16:09 +01:00
---------- End Simulation Statistics ----------
