2011-02-05 09:16:09 +01:00
---------- Begin Simulation Statistics ----------
2016-02-10 10:08:27 +01:00
sim_seconds 0.079141 # Number of seconds simulated
sim_ticks 79140979500 # Number of ticks simulated
final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-02-05 09:16:09 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-02-10 10:08:27 +01:00
host_inst_rate 91812 # Simulator instruction rate (inst/s)
host_op_rate 153885 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 55016334 # Simulator tick rate (ticks/s)
host_mem_usage 351180 # Number of bytes of host memory used
host_seconds 1438.50 # Real time elapsed on the host
2012-08-15 16:38:05 +02:00
sim_insts 132071192 # Number of instructions simulated
2013-10-02 11:03:38 +02:00
sim_ops 221363384 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-02-10 10:08:27 +01:00
system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory
system.physmem.bytes_read::total 346432 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5413 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 2797236 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1580167 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4377403 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2797236 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2797236 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2797236 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1580167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4377403 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5413 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2016-02-10 10:08:27 +01:00
system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2016-02-10 10:08:27 +01:00
system.physmem.bytesReadDRAM 346432 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2016-02-10 10:08:27 +01:00
system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 298 # Per bank write bursts
system.physmem.perBankRdBursts::1 346 # Per bank write bursts
system.physmem.perBankRdBursts::2 461 # Per bank write bursts
system.physmem.perBankRdBursts::3 349 # Per bank write bursts
system.physmem.perBankRdBursts::4 340 # Per bank write bursts
system.physmem.perBankRdBursts::5 326 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::6 402 # Per bank write bursts
2016-02-10 10:08:27 +01:00
system.physmem.perBankRdBursts::7 384 # Per bank write bursts
system.physmem.perBankRdBursts::8 341 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::9 281 # Per bank write bursts
2016-02-10 10:08:27 +01:00
system.physmem.perBankRdBursts::10 239 # Per bank write bursts
system.physmem.perBankRdBursts::11 285 # Per bank write bursts
system.physmem.perBankRdBursts::12 220 # Per bank write bursts
system.physmem.perBankRdBursts::13 466 # Per bank write bursts
system.physmem.perBankRdBursts::14 389 # Per bank write bursts
system.physmem.perBankRdBursts::15 286 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-02-10 10:08:27 +01:00
system.physmem.totGap 79140890500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-02-10 10:08:27 +01:00
system.physmem.readPktSize::6 5413 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2016-02-10 10:08:27 +01:00
system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 904 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.bytesPerActivate::samples 1107 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 311.790425 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.924163 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.273428 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 441 39.84% 39.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 229 20.69% 60.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 106 9.58% 70.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 59 5.33% 75.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 51 4.61% 80.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 54 4.88% 84.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 23 2.08% 86.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 18 1.63% 88.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 126 11.38% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1107 # Bytes accessed per row activation
system.physmem.totQLat 40702000 # Total ticks spent queuing
system.physmem.totMemAccLat 142195750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 27065000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7519.31 # Average queueing delay per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-02-10 10:08:27 +01:00
system.physmem.avgMemAccLat 26269.31 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2016-02-10 10:08:27 +01:00
system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-04-30 05:35:23 +02:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2016-02-10 10:08:27 +01:00
system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2016-02-10 10:08:27 +01:00
system.physmem.readRowHits 4302 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2016-02-10 10:08:27 +01:00
system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2016-02-10 10:08:27 +01:00
system.physmem.avgGap 14620522.91 # Average gap between requests
system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 4898880 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2673000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 22659000 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-02-10 10:08:27 +01:00
system.physmem_0.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2477527515 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 45310553250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 52987315485 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.541483 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 75375284500 # Time in different power states
system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-10 10:08:27 +01:00
system.physmem_0.memoryStateTime::ACT 1122707500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-02-10 10:08:27 +01:00
system.physmem_1.actEnergy 3470040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1893375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 19406400 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-02-10 10:08:27 +01:00
system.physmem_1.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2315256210 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 45452899500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 52961929365 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.220665 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 75612477000 # Time in different power states
system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-10 10:08:27 +01:00
system.physmem_1.memoryStateTime::ACT 884606250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-02-10 10:08:27 +01:00
system.cpu.branchPred.lookups 20604097 # Number of BP lookups
system.cpu.branchPred.condPredicted 20604097 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1328804 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 12707128 # Number of BTB lookups
system.cpu.branchPred.BTBHits 12016947 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-02-10 10:08:27 +01:00
system.cpu.branchPred.BTBHitPct 94.568552 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1442846 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16873 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 400 # Number of system calls
2016-02-10 10:08:27 +01:00
system.cpu.numCycles 158281960 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-02-10 10:08:27 +01:00
system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 227540230 # Number of instructions fetch has processed
system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3196201 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 1974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 21216 # Number of stall cycles due to pending traps
2014-09-03 13:42:59 +02:00
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
2015-09-15 15:14:09 +02:00
system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR
2016-02-10 10:08:27 +01:00
system.cpu.fetch.CacheLines 24267792 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-02-10 10:08:27 +01:00
system.cpu.fetch.rateDist::0 95737540 60.56% 60.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-02-10 10:08:27 +01:00
system.cpu.fetch.rateDist::total 158076676 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.130173 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 23286260 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 21616249 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 23294905 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 31785654 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 30420 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 36005072 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 65362525 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 328266719 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1575 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 380441374 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 910027756 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 600617832 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups
2013-06-24 20:17:22 +02:00
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
2016-02-10 10:08:27 +01:00
system.cpu.rename.UndoneMaps 121011924 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 82787392 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 259397690 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3884 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 158076676 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-02-10 10:08:27 +01:00
system.cpu.iq.issued_per_cycle::0 40037946 25.33% 25.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 47502915 30.05% 55.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4766946 3.02% 97.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2459939 1.56% 99.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 882458 0.56% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 391404 0.25% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-02-10 10:08:27 +01:00
system.cpu.iq.issued_per_cycle::total 158076676 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-02-10 10:08:27 +01:00
system.cpu.iq.fu_full::IntAlu 232299 7.31% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2560752 80.62% 87.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-02-10 10:08:27 +01:00
system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 161810980 62.38% 62.85% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-02-10 10:08:27 +01:00
system.cpu.iq.FU_type_0::total 259397690 # Type of FU issued
system.cpu.iq.rate 1.638833 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 675268343 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 258916834 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-02-10 10:08:27 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 26137805 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-02-10 10:08:27 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 49888 # Number of loads that were rescheduled
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-02-10 10:08:27 +01:00
system.cpu.iew.iewSquashCycles 1598100 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 12496396 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 82787392 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 63074 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 303242 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 257339860 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2057830 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
2016-02-10 10:08:27 +01:00
system.cpu.iew.exec_refs 86369701 # number of memory reference insts executed
system.cpu.iew.exec_branches 14330688 # Number of branches executed
system.cpu.iew.exec_stores 22285011 # Number of stores executed
system.cpu.iew.exec_rate 1.625832 # Inst execution rate
system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back
system.cpu.iew.wb_producers 204396158 # num instructions producing a value
system.cpu.iew.wb_consumers 369708067 # num instructions consuming a value
system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
2016-02-10 10:08:27 +01:00
system.cpu.commit.branchMispredicts 1330625 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 144920748 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.527479 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.956907 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-02-10 10:08:27 +01:00
system.cpu.commit.committed_per_cycle::0 45508636 31.40% 31.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 57312376 39.55% 70.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14158342 9.77% 80.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 11991162 8.27% 88.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4086517 2.82% 91.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2858053 1.97% 93.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 923800 0.64% 94.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1073191 0.74% 95.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 7008671 4.84% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-02-10 10:08:27 +01:00
system.cpu.commit.committed_per_cycle::total 144920748 # Number of insts commited each cycle
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
2013-10-02 11:03:38 +02:00
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 77165304 # Number of memory references committed
system.cpu.commit.loads 56649587 # Number of loads committed
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 12326938 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 797818 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction
2014-09-01 23:55:52 +02:00
system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
2016-02-10 10:08:27 +01:00
system.cpu.commit.bw_lim_events 7008671 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 455771992 # The number of ROB reads
system.cpu.rob.rob_writes 648913303 # The number of ROB writes
system.cpu.timesIdled 2665 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 205284 # Total number of cycles that the CPU has spent unscheduled due to idling
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
2013-10-02 11:03:38 +02:00
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
2016-02-10 10:08:27 +01:00
system.cpu.cpi 1.198459 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads
system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 448575218 # number of integer regfile reads
system.cpu.int_regfile_writes 232602901 # number of integer regfile writes
system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads
system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes
system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads
system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes
system.cpu.misc_regfile_reads 132474844 # number of misc regfile reads
2013-06-24 20:17:22 +02:00
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.replacements 51 # number of replacements
2016-02-10 10:08:27 +01:00
system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 65747317 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 32956.048622 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-02-10 10:08:27 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 1429.115986 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.348905 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.348905 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1394 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 131501473 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 131501473 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 45233028 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 45233028 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20513911 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20513911 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 65746939 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 65746939 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 65746939 # number of overall hits
system.cpu.dcache.overall_hits::total 65746939 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 980 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 980 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1820 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1820 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2800 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2800 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2800 # number of overall misses
system.cpu.dcache.overall_misses::total 2800 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65148000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 65148000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 128547000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 128547000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 193695000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 193695000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 193695000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 193695000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 45234008 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 45234008 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
2016-02-10 10:08:27 +01:00
system.cpu.dcache.demand_accesses::cpu.data 65749739 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 65749739 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 65749739 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 65749739 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66477.551020 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66477.551020 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70630.219780 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 70630.219780 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 69176.785714 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 69176.785714 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu.dcache.writebacks::writebacks 10 # number of writebacks
system.cpu.dcache.writebacks::total 10 # number of writebacks
2016-02-10 10:08:27 +01:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 526 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 526 # number of ReadReq MSHR hits
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
2016-02-10 10:08:27 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 528 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 528 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 528 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 528 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 454 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 454 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1818 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1818 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2272 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2272 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2272 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2272 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126583000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 126583000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162646000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 162646000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162646000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 162646000 # number of overall MSHR miss cycles
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
2016-02-10 10:08:27 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79433.920705 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79433.920705 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69627.612761 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69627.612761 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.cpu.icache.tags.replacements 5017 # number of replacements
system.cpu.icache.tags.tagsinuse 1636.801929 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 24258361 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6993 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3468.949092 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-02-10 10:08:27 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1636.801929 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.799220 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.799220 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1976 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.964844 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 48542851 # Number of tag accesses
system.cpu.icache.tags.data_accesses 48542851 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 24258362 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 24258362 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 24258362 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 24258362 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 24258362 # number of overall hits
system.cpu.icache.overall_hits::total 24258362 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 9429 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 9429 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 9429 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 9429 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 9429 # number of overall misses
system.cpu.icache.overall_misses::total 9429 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 409019999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 409019999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 409019999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 409019999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 409019999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 409019999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24267791 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24267791 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 24267791 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 24267791 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 24267791 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 24267791 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000389 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000389 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000389 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000389 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000389 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000389 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43378.937215 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 43378.937215 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 43378.937215 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 43378.937215 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 793 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2016-02-10 10:08:27 +01:00
system.cpu.icache.writebacks::writebacks 5017 # number of writebacks
system.cpu.icache.writebacks::total 5017 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2159 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2159 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2159 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2159 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2159 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2159 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7270 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 7270 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 7270 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 7270 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 7270 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 7270 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311109999 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 311109999 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311109999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 311109999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311109999 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 311109999 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000300 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000300 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000300 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42793.672490 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42793.672490 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.tags.tagsinuse 2581.252539 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8528 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3879 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.198505 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 1.770890 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2276.984589 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 302.497060 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069488 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.009231 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.078774 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3879 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 999 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 41 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2611 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118378 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 119261 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 119261 # Number of data accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackDirty_hits::writebacks 10 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 10 # number of WritebackDirty hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.WritebackClean_hits::writebacks 4917 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 4917 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3531 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 3531 # number of ReadCleanReq hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 35 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 3531 # number of demand (read+write) hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_hits::cpu.data 41 # number of demand (read+write) hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.demand_hits::total 3572 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3531 # number of overall hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.overall_hits::total 3572 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 276 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 276 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1535 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1535 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3460 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3460 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 419 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 419 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3460 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1954 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5414 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3460 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1954 # number of overall misses
system.cpu.l2cache.overall_misses::total 5414 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115784500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 115784500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262406500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 262406500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34977000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 34977000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 262406500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 150761500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 413168000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 262406500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 150761500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 413168000 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackDirty_accesses::writebacks 10 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 10 # number of WritebackDirty accesses(hits+misses)
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 4917 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 4917 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 277 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 277 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6991 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 6991 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 454 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 454 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 6991 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1995 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 8986 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6991 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1995 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8986 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996390 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996390 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996106 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.996106 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.494922 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.494922 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.922907 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.922907 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.494922 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.979449 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.602493 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.494922 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.979449 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.602493 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75429.641694 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75429.641694 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75840.028902 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75840.028902 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83477.326969 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83477.326969 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76314.739564 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76314.739564 # average overall miss latency
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 276 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 276 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1535 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1535 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3460 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3460 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 419 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 419 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1954 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5414 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1954 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5237000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5237000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100434500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100434500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131221500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 359038000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131221500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 359038000 # number of overall MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996390 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996390 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996106 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996106 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.494922 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.922907 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.922907 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.602493 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.602493 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18974.637681 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18974.637681 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.919075 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.919075 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73477.326969 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73477.326969 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 14610 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 5368 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 377 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 7723 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 5017 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 41 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 7270 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 454 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19277 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4595 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 23872 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 768448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128320 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 896768 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 279 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 9542 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.070845 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.256579 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.snoop_fanout::0 8866 92.92% 92.92% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 676 7.08% 100.00% # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.snoop_fanout::total 9542 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12332000 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 10903500 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3131998 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::ReadResp 3878 # Transaction distribution
system.membus.trans_dist::UpgradeReq 276 # Transaction distribution
system.membus.trans_dist::ReadExReq 1535 # Transaction distribution
system.membus.trans_dist::ReadExResp 1535 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3878 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11102 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11102 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11102 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 346432 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-02-10 10:08:27 +01:00
system.membus.snoop_fanout::samples 5689 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.membus.snoop_fanout::0 5689 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-02-10 10:08:27 +01:00
system.membus.snoop_fanout::total 5689 # Request fanout histogram
system.membus.reqLayer0.occupancy 6955500 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-02-10 10:08:27 +01:00
system.membus.respLayer1.occupancy 28681250 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
2011-02-05 09:16:09 +01:00
---------- End Simulation Statistics ----------
