2011-02-05 09:16:09 +01:00
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---------- Begin Simulation Statistics ----------
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2011-05-05 03:38:27 +02:00
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host_inst_rate 88999 # Simulator instruction rate (inst/s)
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host_mem_usage 265284 # Number of bytes of host memory used
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host_seconds 2487.25 # Real time elapsed on the host
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host_tick_rate 42882469 # Simulator tick rate (ticks/s)
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2011-02-05 09:16:09 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 221363017 # Number of instructions simulated
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2011-05-05 03:38:27 +02:00
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sim_seconds 0.106659 # Number of seconds simulated
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sim_ticks 106659390000 # Number of ticks simulated
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-05-05 03:38:27 +02:00
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system.cpu.BPredUnit.BTBHits 19559071 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 22388883 # Number of BTB lookups
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2011-05-05 03:38:27 +02:00
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system.cpu.BPredUnit.condIncorrect 3071862 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 25034838 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 25034838 # Number of BP lookups
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2011-02-05 09:16:09 +01:00
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-05-05 03:38:27 +02:00
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system.cpu.commit.branchMispredicts 3071894 # The number of times a branch was mispredicted
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.branches 12326943 # Number of branches committed
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2011-05-05 03:38:27 +02:00
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system.cpu.commit.bw_lim_events 2350531 # number cycles where commit BW limit reached
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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2011-02-05 09:16:09 +01:00
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system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
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2011-05-05 03:38:27 +02:00
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system.cpu.commit.commitSquashedInsts 173965235 # The number of squashed insts skipped by commit
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system.cpu.commit.committed_per_cycle::samples 190108496 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::mean 1.164404 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::stdev 1.519902 # Number of insts commited each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2011-05-05 03:38:27 +02:00
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system.cpu.commit.committed_per_cycle::0 74006380 38.93% 38.93% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::1 71095556 37.40% 76.33% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::2 18250817 9.60% 85.93% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::3 12666090 6.66% 92.59% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::4 5885570 3.10% 95.68% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::5 2802504 1.47% 97.16% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::6 1948827 1.03% 98.18% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::7 1102221 0.58% 98.76% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::8 2350531 1.24% 100.00% # Number of insts commited each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2011-05-05 03:38:27 +02:00
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system.cpu.commit.committed_per_cycle::total 190108496 # Number of insts commited each cycle
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2011-04-20 03:45:23 +02:00
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system.cpu.commit.count 221363017 # Number of instructions committed
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system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 0 # Number of function calls committed.
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system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
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system.cpu.commit.loads 56649590 # Number of loads committed
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system.cpu.commit.membars 0 # Number of memory barriers committed
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system.cpu.commit.refs 77165306 # Number of memory references committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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2011-02-05 09:16:09 +01:00
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system.cpu.committedInsts 221363017 # Number of Instructions Simulated
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system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
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2011-05-05 03:38:27 +02:00
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system.cpu.cpi 0.963660 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.963660 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 50560876 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 33172.166428 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34228.682171 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 50560179 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 23121000 # number of ReadReq miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.ReadReq_misses 697 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 310 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 13246500 # number of ReadReq MSHR miss cycles
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2011-02-14 02:46:04 +01:00
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.ReadReq_mshr_misses 387 # number of ReadReq MSHR misses
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 26488.657179 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35473.248408 # average WriteReq mshr miss latency
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_hits 20508633 # number of WriteReq hits
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.WriteReq_miss_latency 187990000 # number of WriteReq miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 7097 # number of WriteReq misses
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.WriteReq_mshr_hits 5527 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 55693000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1570 # number of WriteReq MSHR misses
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.avg_refs 36352.334527 # Average number of references to valid blocks.
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.demand_accesses 71076606 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 27086.348473 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 71068812 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 211111000 # number of demand (read+write) miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.demand_misses 7794 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 5837 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 68939500 # number of demand (read+write) MSHR miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.occ_blocks::0 1400.398145 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.341894 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 71076606 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 27086.348473 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.overall_hits 71068812 # number of overall hits
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system.cpu.dcache.overall_miss_latency 211111000 # number of overall miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.overall_misses 7794 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 5837 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 68939500 # number of overall MSHR miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2011-02-14 02:46:04 +01:00
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system.cpu.dcache.replacements 48 # number of replacements
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks.
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2011-05-05 03:38:27 +02:00
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system.cpu.dcache.tagsinuse 1400.398145 # Cycle average of tags in use
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system.cpu.dcache.total_refs 71068814 # Total number of references to valid blocks.
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2011-02-05 09:16:09 +01:00
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2011-02-14 02:44:32 +01:00
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system.cpu.dcache.writebacks 10 # number of writebacks
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2011-05-05 03:38:27 +02:00
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system.cpu.decode.BlockedCycles 57002752 # Number of cycles decode is blocked
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system.cpu.decode.DecodedInsts 419872535 # Number of instructions handled by decode
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system.cpu.decode.IdleCycles 66995296 # Number of cycles decode is idle
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system.cpu.decode.RunCycles 60323444 # Number of cycles decode is running
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system.cpu.decode.SquashCycles 23120513 # Number of cycles decode is squashing
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system.cpu.decode.UnblockCycles 5787004 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 25034838 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 27511716 # Number of cache lines fetched
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system.cpu.fetch.Cycles 69512577 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 449654 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 261443886 # Number of instructions fetch has processed
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2011-04-04 18:42:25 +02:00
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system.cpu.fetch.MiscStallCycles 62 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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2011-05-05 03:38:27 +02:00
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system.cpu.fetch.SquashCycles 3099669 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.117359 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 27511716 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 19559071 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.225602 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 213229009 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.015146 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.226933 # Number of instructions fetched each cycle (Total)
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2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-05-05 03:38:27 +02:00
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system.cpu.fetch.rateDist::0 145563800 68.27% 68.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 3763912 1.77% 70.03% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 3143749 1.47% 71.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 4274487 2.00% 73.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 4655568 2.18% 75.69% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 4407393 2.07% 77.76% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 4998818 2.34% 80.11% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3209647 1.51% 81.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 39211635 18.39% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-02-05 09:16:09 +01:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-05-05 03:38:27 +02:00
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system.cpu.fetch.rateDist::total 213229009 # Number of instructions fetched each cycle (Total)
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system.cpu.fp_regfile_reads 3514377 # number of floating regfile reads
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system.cpu.fp_regfile_writes 2187528 # number of floating regfile writes
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system.cpu.icache.ReadReq_accesses 27511716 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 25569.940006 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.790041 # average ReadReq mshr miss latency
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|
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system.cpu.icache.ReadReq_hits 27505382 # number of ReadReq hits
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|
|
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system.cpu.icache.ReadReq_miss_latency 161960000 # number of ReadReq miss cycles
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2011-04-04 18:42:25 +02:00
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system.cpu.icache.ReadReq_miss_rate 0.000230 # miss rate for ReadReq accesses
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2011-05-05 03:38:27 +02:00
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system.cpu.icache.ReadReq_misses 6334 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 952 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 120905500 # number of ReadReq MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses
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2011-05-05 03:38:27 +02:00
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|
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system.cpu.icache.ReadReq_mshr_misses 5382 # number of ReadReq MSHR misses
|
2011-02-05 09:16:09 +01:00
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-05-05 03:38:27 +02:00
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system.cpu.icache.avg_refs 5112.524535 # Average number of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
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|
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
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|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.demand_accesses 27511716 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 25569.940006 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 27505382 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 161960000 # number of demand (read+write) miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.000230 # miss rate for demand accesses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.demand_misses 6334 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 952 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 120905500 # number of demand (read+write) MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 5382 # number of demand (read+write) MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1605.599338 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.783984 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.overall_accesses 27511716 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 25569.940006 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.overall_hits 27505382 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 161960000 # number of overall miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_miss_rate 0.000230 # miss rate for overall accesses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.overall_misses 6334 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 952 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 120905500 # number of overall MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 5382 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.replacements 3421 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 5380 # Sample count of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.icache.tagsinuse 1605.599338 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 27505382 # Total number of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.idleCycles 89772 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.branchMispredicts 3285583 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.exec_branches 15876599 # Number of branches executed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iew.exec_rate 1.304758 # Inst execution rate
|
|
|
|
|
system.cpu.iew.exec_refs 90277406 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_stores 23169669 # Number of stores executed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 535171 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 104943598 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 227523 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 37082263 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 395310289 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 67107737 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 3518032 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 278329468 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 451527 # Number of times the IQ has become full, causing a stall
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 13065 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 23120513 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 520097 # Number of cycles IEW is unblocking
|
2011-04-22 19:18:51 +02:00
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 16336525 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 15761 # Number of memory responses ignored because the instruction is squashed
|
2011-04-22 19:18:51 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 34193 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 46033 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 48294008 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 16566547 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 34193 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 745041 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 2540542 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.wb_consumers 371832293 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_count 275994943 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_fanout 0.599268 # average fanout of values written-back
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iew.wb_producers 222827233 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_rate 1.293815 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_sent 277038754 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.int_regfile_reads 516581259 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 284038520 # number of integer regfile writes
|
|
|
|
|
system.cpu.ipc 1.037710 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.037710 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 1197054 0.42% 0.42% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntAlu 187021337 66.36% 66.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 1590291 0.56% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 68531630 24.32% 91.66% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 23507188 8.34% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 281847500 # Type of FU issued
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 2638444 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 5236518 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2534154 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 5693561 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 2791850 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.009906 # FU busy rate (busy events/executed inst)
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.fu_full::IntAlu 67290 2.41% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.41% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 2359047 84.50% 86.91% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 365513 13.09% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 280803852 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 774570053 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 273460789 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 563268520 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.iqInstsAdded 395308865 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 281847500 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 173620640 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 90712 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 357064626 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 213229009 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 1.321807 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.374231 # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::0 72462076 33.98% 33.98% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 65441995 30.69% 64.67% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 36667606 17.20% 81.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 20567003 9.65% 91.52% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 11965683 5.61% 97.13% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 3990809 1.87% 99.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 1502036 0.70% 99.70% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 514117 0.24% 99.94% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 117684 0.06% 100.00% # Number of insts issued each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::total 213229009 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.rate 1.321250 # Inst issue rate
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.695262 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.472471 # average ReadExReq mshr miss latency
|
2011-02-14 02:44:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 53963500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48971000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 5767 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34290.551611 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.326597 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 2105 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 125572000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.634992 # miss rate for ReadReq accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses 3662 # number of ReadReq misses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 113677000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634992 # mshr miss rate for ReadReq accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 3662 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses
|
2011-02-14 02:44:32 +01:00
|
|
|
system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.574195 # Average number of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 7335 # number of demand (read+write) accesses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34367.438744 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 2111 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 179535500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.712202 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 5224 # number of demand (read+write) misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 162648000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.712202 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 5224 # number of demand (read+write) MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 2429.722700 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 1.014710 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.074149 # Average percentage of cache occupancy
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 7335 # number of overall (read+write) accesses
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34367.438744 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.overall_hits 2111 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 179535500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.712202 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 5224 # number of overall misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 162648000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.712202 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 5224 # number of overall MSHR misses
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 3666 # Sample count of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 2430.737411 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 2105 # Total number of references to valid blocks.
|
2011-02-05 09:16:09 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 90595235 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 30370608 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 104943598 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 37082263 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.misc_regfile_reads 145181965 # number of misc regfile reads
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.numCycles 213318781 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.rename.BlockCycles 18031749 # Number of cycles rename is blocking
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
|
2011-05-05 03:38:27 +02:00
|
|
|
system.cpu.rename.IQFullEvents 21548402 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.IdleCycles 74813235 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.LSQFullEvents 16345466 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RenameLookups 1053910938 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RenamedInsts 409668647 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RenamedOperands 430592677 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RunCycles 57355298 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.SquashCycles 23120513 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.UnblockCycles 39885814 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.UndoneMaps 196229268 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 11151271 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.int_rename_lookups 1042759667 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.serializeStallCycles 22400 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 83004304 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 1309 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rob.rob_reads 583086217 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 813789002 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 1930 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.workload.num_syscalls 400 # Number of system calls
|
2011-02-05 09:16:09 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
