Commit graph

614 commits

Author SHA1 Message Date
Nilay Vaish
af58313fd6 regressions: update a couple of configs
The configs for pc-simple-timing-ruby, t1000-simple-atomic had not been
updated correctly in the patch 6e6cefc1db1f.
2013-07-02 10:10:58 -05:00
Andreas Hansson
5a15909bac stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
2013-06-27 05:49:51 -04:00
Akash Bagdia
7d7ab73862 sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 05:49:49 -04:00
Andreas Hansson
4de3205afa config: Add a BaseSESystem builder for re-use in regressions
This patch extends the existing system builders to also include a
syscall-emulation builder. This builder is deployed in all
syscall-emulation regressions that do not involve Ruby,
i.e. o3-timing, simple-timing and simple-atomic, as well as the
multi-processor regressions o3-timing-mp, simple-timing-mp and
simple-atomic-mp (the latter are only used by SPARC at this point).

The values chosen for the cache sizes match those that were used in
the existing config scripts (despite being on the large
side). Similarly, a mem_class parameter is added to the builder base
class to enable simple-atomic to use SimpleMemory and o3-timing to use
the default DDR3 configuration.

Due to the different order the ports are connected, the bus stats get
shuffled around for the multi-processor regressions. A separate patch
bumps the port indices. Besides this, all behaviour is exactly the
same.
2013-06-27 05:49:49 -04:00
Akash Bagdia
076d04a653 config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.

As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.

The configs and tests are updated accordingly.
2013-06-27 05:49:49 -04:00
Akash Bagdia
7eccb1b779 config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
2013-06-27 05:49:49 -04:00
Andreas Hansson
f821c5472b tests: Prune 00.gzip from the regressions
This patch prunes the 00.gzip regressions with the main motivation
being that it adds little (or no) coverage and requires a substantial
amount of run time.

A complete regression run, including compilation from a clean repo, is
almost 20% faster(!).
2013-06-27 05:49:49 -04:00
Andreas Hansson
718fb40709 scons: Identify runs that fail and runs with stats differences
This patch changes the regression script such that it is possible to
identify the runs that fail with an exit code, and those that finish
with stats differences. The ones that truly fail are reported as
FAILED, and those that finish with changed stats as CHANGED.

The yellow colour has been reclaimed from the skipped regressions and
is now used for the changed ones. With no obvious good option left the
skipped ones are now in cyan.

While I was editing the script I also bumped any occurence of M5 to
gem5.
2013-06-27 05:49:49 -04:00
Nilay Vaish
a1e18270a1 stats: updates due to changes to stat collection in ruby 2013-06-25 00:32:04 -05:00
Andreas Hansson
beee57070a stats: Bump x86 stats
This patch bumps the x86 stats to reflect the recent fixes.
2013-06-24 14:17:22 -04:00
Nilay Vaish
247e4e9ab4 stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
2013-06-10 06:46:20 -05:00
Steve Reinhardt
bd39adfa98 Updating EIO regression reference outputs for new stats. 2013-06-08 10:28:33 -04:00
Andreas Hansson
74553c7d3f stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00
Andreas Hansson
3bc4ecdcb4 mem: More descriptive DRAM config names
This patch changes the class names of the variuos DRAM configurations
to better reflect what memory they are based on. The speed and
interface width is now part of the name, and also the alias that is
used to select them on the command line.

Some minor changes are done to the actual parameters, to better
reflect the named configurations. As a result of these changes the
regressions change slightly and the stats will be bumped in a separate
patch.
2013-05-30 12:54:14 -04:00
Nilay Vaish
af2e83c7f1 x86, regressions: updates stats
This is due to op class, function call, walker patches.
2013-05-21 11:41:27 -05:00
Nilay Vaish
5b49c3d255 stats: updates statistics for ruby regressions 2013-05-21 11:32:57 -05:00
Andreas Hansson
9f8b1aec49 config: Added memory type to t1000 regression
This patch adds the memory type parameter to the t1000 regression.
2013-04-28 17:14:39 -04:00
Nilay Vaish
c2d799c6b0 x86: regressions: add switcher full test 2013-04-23 00:03:09 -05:00
Nilay Vaish
3295e6de69 x86, stats: updates due to lret bugfix 2013-04-23 00:03:05 -05:00
Andreas Hansson
3477d60d5c config: Add a mem-type config option to se/fs scripts
This patch enables selection of the memory controller class through a
mem-type command-line option. Behind the scenes, this option is
treated much like the cpu-type, and a similar framework is used to
resolve the valid options, and translate the short-hand description to
a valid class.

The regression scripts are updated with a hardcoded memory class for
the moment. The best solution going forward is probably to get the
memory out of the makeSystem functions, but Ruby complicates things as
it does not connect the memory controller to the membus.

--HG--
rename : configs/common/CpuConfig.py => configs/common/MemConfig.py
2013-04-22 13:20:33 -04:00
Ali Saidi
d69f904a18 stats: Update stats for O3 switching fix. 2013-04-22 13:20:33 -04:00
Andreas Sandberg
dc83d23425 tests: Add support for testing KVM-based CPUs
This changeset adds support for initializing a KVM VM in the
BaseSystem test class and adds the following methods in run.py:

require_file -- Test if a file exists and abort/skip if not.
require_kvm -- Test if KVM support has been compiled into gem5 (i.e.,
	       BaseKvmCPU exists) and the KVM device exists on the
	       host.
2013-04-22 13:20:32 -04:00
Andreas Sandberg
5f2361f3af arm: Enable support for triggering a sim panic on kernel panics
Add the options 'panic_on_panic' and 'panic_on_oops' to the
LinuxArmSystem SimObject. When these option are enabled, the simulator
panics when the guest kernel panics or oopses. Enable panic on panic
and panic on oops in ARM-based test cases.
2013-04-22 13:20:31 -04:00
Andreas Hansson
5dd23833fd stats: Update stats for ldr_ret_uop (changeset 35198406dd72)
This patch merely bumps the stats to match the changes introduced in
changeset 35198406dd72.
2013-04-19 09:04:42 -04:00
Andreas Hansson
c704b7be16 stats: Bump the vortex stats to match latest behaviour
This patch bumps the stats for the failing vortex o3 regression.
2013-04-16 06:26:49 -04:00
Joel Hestness
53b713fb4b stats: Bump Ruby stats for new changesets
The new changeset that can reorder Ruby profilers will cause the ruby.stats
files to reordered statistics (the point of the patch). Update the references
to ensure that these changes are reflected in regressions.
2013-04-09 16:41:12 -05:00
Nilay Vaish
26e96b90e1 regressions: updates due to changes to o3 cpu, x86 memory map 2013-03-29 14:05:36 -05:00
Nilay Vaish
1af9369779 regressions: update eio stats due to cache latency fix 2013-03-28 09:32:01 -05:00
Nilay Vaish
4646369afd regressions: update due to cache latency fix 2013-03-27 18:36:21 -05:00
Andreas Hansson
a84d026538 stats: Update stats for cache retry event check
This patch updates the stats for the affected stats. All the changes
are minimal (in the <0.01% range).
2013-03-26 14:47:03 -04:00
Andreas Hansson
08f7a8bc00 stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
2013-03-26 14:46:49 -04:00
Nilay Vaish
04fe6b486a regressions: updates to config.ini for ruby tests 2013-03-22 17:21:25 -05:00
Nilay Vaish
53a0597805 regressions: x86: stats updates due to new x87 insts 2013-03-11 17:45:09 -05:00
Nilay Vaish
d24d5446c5 regressions: stats updates due to no physmem in ruby 2013-03-06 21:57:10 -06:00
Nilay Vaish
c061819890 ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.
2013-03-06 21:53:57 -06:00
Ali Saidi
09b2430e95 stats: update patches for branch predictor and fetch updates. 2013-03-04 23:33:47 -05:00
Andreas Hansson
cb9e208a4c stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
2013-03-01 13:20:30 -05:00
Ali Saidi
a86f67e706 stats: more zizzer stats fun 2013-02-19 09:53:07 -05:00
Ali Saidi
bd31a5dc18 stats: update regressions for o3 changes in renaming and translation. 2013-02-15 17:40:14 -05:00
Andreas Sandberg
e5dca84c3f config: Move CPU handover logic to m5.switchCpus()
CPU switching consists of the following steps:
 1. Drain the system
 2. Switch out old CPUs (cpu.switchOut())
 3. Change the system timing mode to the mode the new CPUs require
 4. Flush caches if switching to hardware virtualization
 5. Inform new CPUs of the handover (cpu.takeOverFrom())
 6. Resume the system

m5.switchCpus() previously only did step 2 & 5. Since information
about the new processors' memory system requirements is now exposed,
do all of the steps above.

This patch adds automatic memory system switching and flush (if
needed) to switchCpus(). Additionally, it adds optional draining to
switchCpus(). This has the following implications:

* changeToTiming and changeToAtomic are no longer needed, so they have
  been removed.

* changeMemoryMode is only used internally, so it is has been renamed
  to be private.

* switchCpus requires a reference to the system containing the CPUs as
  its first parameter.

WARNING: This changeset breaks compatibility with existing
configuration scripts since it changes the signature of
m5.switchCpus().
2013-02-15 17:40:08 -05:00
Nilay Vaish
1962e9262d regressions: update stats due to changes to ruby 2013-02-10 21:43:23 -06:00
Andreas Hansson
fce3433b2e stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
2013-01-31 07:49:16 -05:00
Andreas Hansson
c4898b15bc mem: Add DDR3 and LPDDR2 DRAM controller configurations
This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.

The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
2013-01-31 07:49:14 -05:00
Andreas Hansson
093fc6707f stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3
This patch bumps the stats for 20.parser for ARM o3-timing to reflect
a namechange of the branch predictor.
2013-01-28 07:44:26 -05:00
Nilay Vaish
9bc132e473 regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
2013-01-24 12:29:00 -06:00
Nilay Vaish
4526f33062 x86 regressions: updates due to new instructions and cpuid 2013-01-15 07:43:23 -06:00
Nilay Vaish
7fdcfdf08b regressions: update stats due to changes in ruby obj hierarchy 2013-01-14 10:20:16 -06:00
Andreas Hansson
5b90902437 stats: Bump failing x86 regression stats
This patch bumps the stats of mcf and twolf for the o3 CPU such that
the regressions pass.
2013-01-14 10:23:54 -05:00
Ali Saidi
fbeced6135 stats: update stats for previous six changes 2013-01-08 08:54:16 -05:00
Ali Saidi
9f15510c2c stats: update stats for previous changes. 2013-01-07 13:05:54 -05:00