config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour. The main motivation for these simplifications is to ease the introduction of clock domains.
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9 changed files with 11 additions and 16 deletions
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@ -134,8 +134,8 @@ if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
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test_sys.vm = KvmVM()
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if options.caches or options.l2cache:
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test_sys.iocache = IOCache(clock = '1GHz',
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addr_ranges = test_sys.mem_ranges)
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# By default the IOCache runs at the system clock
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test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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else:
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@ -281,10 +281,10 @@ class BaseCPU(MemObject):
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
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self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
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# Override the default bus clock of 1 GHz and uses the CPU
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# clock for the L1-to-L2 bus, and also set a width of 32 bytes
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# (256-bits), which is four times that of the default bus.
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self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
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# Set a width of 32 bytes (256-bits), which is four times that
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# of the default bus. The clock of the CPU is inherited by
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# default.
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self.toL2Bus = CoherentBus(width = 32)
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self.connectCachedPorts(self.toL2Bus)
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self.l2cache = l2c
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self.toL2Bus.master = self.l2cache.cpu_side
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@ -53,8 +53,6 @@ class CopyEngine(PciDevice):
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ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
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XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
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# Override the default clock
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clock = '500MHz'
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latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
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latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
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@ -118,8 +118,6 @@ class CpuLocalTimer(BasicPioDevice):
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
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int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
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# Override the default clock
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clock = '1GHz'
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class PL031(AmbaIntDevice):
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type = 'PL031'
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@ -36,7 +36,6 @@ class RubySystem(ClockedObject):
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random_seed = Param.Int(1234, "random seed used by the simulation");
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randomization = Param.Bool(False,
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"insert random delays on message enqueue times");
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clock = '1GHz'
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block_size_bytes = Param.UInt32(64,
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"default cache block size; must be a power of two");
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mem_size = Param.MemorySize("total memory size of the system");
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@ -161,8 +161,8 @@ class BaseFSSystem(BaseSystem):
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def init_system(self, system):
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BaseSystem.init_system(self, system)
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#create the iocache
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system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges)
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# create the iocache, which by default runs at the system clock
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system.iocache = IOCache(addr_ranges=system.mem_ranges)
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system.iocache.cpu_side = system.iobus.master
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system.iocache.mem_side = system.membus.slave
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@ -39,7 +39,7 @@ cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
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system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
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funcbus = NoncoherentBus(),
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physmem = SimpleMemory(),
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membus = CoherentBus(clock="1GHz", width=16))
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membus = CoherentBus(width=16))
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# l2cache & bus
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system.toL2Bus = CoherentBus(clock="2GHz", width=16)
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@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
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# system simulated
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system = System(cpu = cpu, physmem = DDR3_1600_x64(),
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membus = NoncoherentBus(clock="1GHz", width = 16))
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membus = NoncoherentBus(width = 16))
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# add a communication monitor
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system.monitor = CommMonitor()
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@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
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# system simulated
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system = System(cpu = cpu, physmem = SimpleMemory(),
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membus = NoncoherentBus(clock="1GHz", width = 16))
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membus = NoncoherentBus(width = 16))
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# add a communication monitor, and also trace all the packets
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system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
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