Updating EIO regression reference outputs for new stats.
This commit is contained in:
Steve Reinhardt
parent
2b582ad9bb
commit
bd39adfa98
14 changed files with 773 additions and 660 deletions
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@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
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type=System
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children=cpu membus physmem
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boot_osflags=a
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clock=1000
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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mem_mode=atomic
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mem_ranges=
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memories=system.physmem
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num_work_ids=16
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readfile=
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@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
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[system.cpu]
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type=AtomicSimpleCPU
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children=dtb interrupts itb tracer workload
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children=dtb interrupts isa itb tracer workload
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branchPred=Null
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checker=Null
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clock=500
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cpu_id=0
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defer_registration=false
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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@ -42,17 +44,22 @@ fastmem=false
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function_trace=false
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function_trace_start=0
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=500000
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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phase=0
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profile=0
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progress_interval=0
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simpoint_interval=100000000
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simpoint_profile=false
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simpoint_profile_file=simpoint.bb.gz
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simpoint_start_insts=
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simulate_data_stalls=false
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simulate_inst_stalls=false
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switched_out=false
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system=system
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tracer=system.cpu.tracer
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width=1
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@ -67,6 +74,9 @@ size=64
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[system.cpu.interrupts]
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type=AlphaInterrupts
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[system.cpu.isa]
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type=AlphaISA
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[system.cpu.itb]
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type=AlphaTLB
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size=48
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@ -89,6 +99,7 @@ type=CoherentBus
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block_size=64
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clock=1000
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header_cycles=1
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system=system
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use_default_range=false
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width=8
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master=system.physmem.port
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@ -96,13 +107,13 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
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[system.physmem]
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type=SimpleMemory
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bandwidth=73.000000
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clock=1000
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conf_table_reported=false
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file=
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in_addr_map=true
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.master[0]
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@ -1,10 +1,8 @@
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Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simout
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Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jul 22 2012 20:21:46
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gem5 started Jul 23 2012 00:28:55
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gem5 compiled Jun 8 2013 10:00:13
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gem5 started Jun 8 2013 10:00:28
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu
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sim_ticks 250015500 # Number of ticks simulated
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final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1870393 # Simulator instruction rate (inst/s)
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host_op_rate 1870272 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 935134836 # Simulator tick rate (ticks/s)
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host_mem_usage 212756 # Number of bytes of host memory used
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host_seconds 0.27 # Real time elapsed on the host
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host_inst_rate 2804892 # Simulator instruction rate (inst/s)
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host_op_rate 2804630 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1402273759 # Simulator tick rate (ticks/s)
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host_mem_usage 217844 # Number of bytes of host memory used
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host_seconds 0.18 # Real time elapsed on the host
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sim_insts 500001 # Number of instructions simulated
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sim_ops 500001 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory
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@ -33,6 +33,9 @@ system.physmem.bw_write::total 1670144451 # Wr
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system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 13160136072 # Throughput (bytes/s)
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system.membus.data_through_bus 3290238 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
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type=System
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children=cpu membus physmem
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boot_osflags=a
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clock=1000
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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mem_mode=atomic
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mem_mode=timing
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mem_ranges=
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memories=system.physmem
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num_work_ids=16
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readfile=
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@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
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[system.cpu]
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type=TimingSimpleCPU
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children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
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children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
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branchPred=Null
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checker=Null
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clock=500
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cpu_id=0
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defer_registration=false
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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@ -41,15 +43,17 @@ dtb=system.cpu.dtb
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function_trace=false
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function_trace_start=0
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=500000
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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phase=0
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profile=0
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progress_interval=0
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simpoint_start_insts=
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switched_out=false
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system=system
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tracer=system.cpu.tracer
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workload=system.cpu.workload
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@ -61,21 +65,18 @@ type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=2
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block_size=64
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=2
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=10
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=2
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size=262144
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subblock_size=0
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system=system
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tgts_per_mshr=5
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trace_addr=0
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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@ -90,21 +91,18 @@ type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=2
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block_size=64
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=2
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is_top_level=true
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latency=1000
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max_miss_count=0
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mshrs=10
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=2
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size=131072
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subblock_size=0
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system=system
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tgts_per_mshr=5
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trace_addr=0
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.icache_port
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@ -113,6 +111,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
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[system.cpu.interrupts]
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type=AlphaInterrupts
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[system.cpu.isa]
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type=AlphaISA
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[system.cpu.itb]
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type=AlphaTLB
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size=48
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@ -120,23 +121,20 @@ size=48
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[system.cpu.l2cache]
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type=BaseCache
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addr_ranges=0:18446744073709551615
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assoc=2
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assoc=8
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block_size=64
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clock=500
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forward_snoops=true
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hash_delay=1
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hit_latency=20
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is_top_level=false
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latency=10000
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max_miss_count=0
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mshrs=10
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mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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prioritizeRequests=false
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repl=Null
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response_latency=20
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size=2097152
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subblock_size=0
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system=system
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tgts_per_mshr=5
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trace_addr=0
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tgts_per_mshr=12
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.toL2Bus.master[0]
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@ -145,10 +143,11 @@ mem_side=system.membus.slave[1]
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[system.cpu.toL2Bus]
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type=CoherentBus
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block_size=64
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clock=1000
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clock=500
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header_cycles=1
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system=system
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use_default_range=false
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width=8
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width=32
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master=system.cpu.l2cache.cpu_side
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slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
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@ -170,6 +169,7 @@ type=CoherentBus
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block_size=64
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clock=1000
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header_cycles=1
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system=system
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use_default_range=false
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width=8
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master=system.physmem.port
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@ -177,13 +177,13 @@ slave=system.system_port system.cpu.l2cache.mem_side
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[system.physmem]
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type=SimpleMemory
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bandwidth=73.000000
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clock=1000
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conf_table_reported=false
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file=
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in_addr_map=true
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.master[0]
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@ -1,14 +1,12 @@
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Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simout
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Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jul 22 2012 20:21:46
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gem5 started Jul 23 2012 00:28:55
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gem5 compiled Jun 8 2013 10:00:13
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gem5 started Jun 8 2013 10:00:28
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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main dictionary has 1245 entries
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49508 bytes wasted
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>Exiting @ tick 729729000 because a thread reached the max instruction count
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>Exiting @ tick 727072000 because a thread reached the max instruction count
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@ -4,11 +4,11 @@ sim_seconds 0.000727 # Nu
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sim_ticks 727072000 # Number of ticks simulated
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final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1240024 # Simulator instruction rate (inst/s)
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host_op_rate 1239964 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1802997891 # Simulator tick rate (ticks/s)
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host_mem_usage 256648 # Number of bytes of host memory used
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host_seconds 0.40 # Real time elapsed on the host
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host_inst_rate 1476552 # Simulator instruction rate (inst/s)
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host_op_rate 1476467 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2146892777 # Simulator tick rate (ticks/s)
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host_mem_usage 226332 # Number of bytes of host memory used
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host_seconds 0.34 # Real time elapsed on the host
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sim_insts 500001 # Number of instructions simulated
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sim_ops 500001 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
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@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 35473791 # In
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system.physmem.bw_total::cpu.inst 35473791 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 39963030 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 75436821 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 75436821 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 718 # Transaction distribution
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system.membus.trans_dist::ReadResp 718 # Transaction distribution
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system.membus.trans_dist::ReadExReq 139 # Transaction distribution
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system.membus.trans_dist::ReadExResp 139 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 1714 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 54848 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 54848 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 857000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.membus.respLayer1.occupancy 7713000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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@ -160,104 +175,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use
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system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
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system.cpu.dcache.overall_hits::total 180321 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
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system.cpu.dcache.overall_misses::total 454 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 481.542013 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
@ -377,5 +294,122 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 180321 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 454 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 75436821 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 718 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 806 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 908 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count 1714 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 25792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 29056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size 54848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 54848 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 604500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
|
||||
boot_osflags=a
|
||||
clock=1000
|
||||
init_param=0
|
||||
kernel=
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
|
|
@ -29,11 +31,11 @@ system_port=system.membus.slave[1]
|
|||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
children=dcache dtb icache interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -42,17 +44,22 @@ fastmem=false
|
|||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu0.interrupts
|
||||
isa=system.cpu0.isa
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
width=1
|
||||
|
|
@ -65,21 +72,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.dcache_port
|
||||
|
|
@ -94,21 +98,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu0.icache_port
|
||||
|
|
@ -117,6 +118,9 @@ mem_side=system.toL2Bus.slave[0]
|
|||
[system.cpu0.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu0.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -136,11 +140,11 @@ system=system
|
|||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
children=dcache dtb icache interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -149,17 +153,22 @@ fastmem=false
|
|||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu1.interrupts
|
||||
isa=system.cpu1.isa
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
width=1
|
||||
|
|
@ -172,21 +181,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
|
|
@ -201,21 +207,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu1.icache_port
|
||||
|
|
@ -224,6 +227,9 @@ mem_side=system.toL2Bus.slave[2]
|
|||
[system.cpu1.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -243,11 +249,11 @@ system=system
|
|||
|
||||
[system.cpu2]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
children=dcache dtb icache interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=2
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -256,17 +262,22 @@ fastmem=false
|
|||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu2.interrupts
|
||||
isa=system.cpu2.isa
|
||||
itb=system.cpu2.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu2.tracer
|
||||
width=1
|
||||
|
|
@ -279,21 +290,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu2.dcache_port
|
||||
|
|
@ -308,21 +316,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu2.icache_port
|
||||
|
|
@ -331,6 +336,9 @@ mem_side=system.toL2Bus.slave[4]
|
|||
[system.cpu2.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu2.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu2.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -350,11 +358,11 @@ system=system
|
|||
|
||||
[system.cpu3]
|
||||
type=AtomicSimpleCPU
|
||||
children=dcache dtb icache interrupts itb tracer workload
|
||||
children=dcache dtb icache interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=3
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -363,17 +371,22 @@ fastmem=false
|
|||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu3.interrupts
|
||||
isa=system.cpu3.isa
|
||||
itb=system.cpu3.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=500000
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_interval=100000000
|
||||
simpoint_profile=false
|
||||
simpoint_profile_file=simpoint.bb.gz
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu3.tracer
|
||||
width=1
|
||||
|
|
@ -386,21 +399,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu3.dcache_port
|
||||
|
|
@ -415,21 +425,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=2
|
||||
is_top_level=true
|
||||
latency=1000
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=2
|
||||
size=32768
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=8
|
||||
trace_addr=0
|
||||
tgts_per_mshr=20
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu3.icache_port
|
||||
|
|
@ -438,6 +445,9 @@ mem_side=system.toL2Bus.slave[6]
|
|||
[system.cpu3.interrupts]
|
||||
type=AlphaInterrupts
|
||||
|
||||
[system.cpu3.isa]
|
||||
type=AlphaISA
|
||||
|
||||
[system.cpu3.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
|
@ -460,21 +470,18 @@ type=BaseCache
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
block_size=64
|
||||
clock=500
|
||||
forward_snoops=true
|
||||
hash_delay=1
|
||||
hit_latency=20
|
||||
is_top_level=false
|
||||
latency=10000
|
||||
max_miss_count=0
|
||||
mshrs=92
|
||||
mshrs=20
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
prioritizeRequests=false
|
||||
repl=Null
|
||||
response_latency=20
|
||||
size=4194304
|
||||
subblock_size=0
|
||||
system=system
|
||||
tgts_per_mshr=16
|
||||
trace_addr=0
|
||||
tgts_per_mshr=12
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.master[0]
|
||||
|
|
@ -485,6 +492,7 @@ type=CoherentBus
|
|||
block_size=64
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.physmem.port
|
||||
|
|
@ -492,21 +500,22 @@ slave=system.l2c.mem_side system.system_port
|
|||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clock=1000
|
||||
conf_table_reported=false
|
||||
file=
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:1073741823
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.toL2Bus]
|
||||
type=CoherentBus
|
||||
block_size=64
|
||||
clock=1000
|
||||
clock=500
|
||||
header_cycles=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
master=system.l2c.cpu_side
|
||||
|
|
|
|||
|
|
@ -6,5 +6,3 @@ hack: be nice to actually delete the event here
|
|||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
|
|||
|
|
@ -1,10 +1,8 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 22 2012 20:21:46
|
||||
gem5 started Jul 23 2012 00:28:55
|
||||
gem5 compiled Jun 8 2013 10:00:13
|
||||
gem5 started Jun 8 2013 10:00:28
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu
|
|||
sim_ticks 250015500 # Number of ticks simulated
|
||||
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2922206 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2922133 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 365280152 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 1149344 # Number of bytes of host memory used
|
||||
host_seconds 0.68 # Real time elapsed on the host
|
||||
host_inst_rate 3032804 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3032728 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 379104441 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 1154504 # Number of bytes of host memory used
|
||||
host_seconds 0.66 # Real time elapsed on the host
|
||||
sim_insts 2000004 # Number of instructions simulated
|
||||
sim_ops 2000004 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
|
||||
|
|
@ -57,6 +57,12 @@ system.physmem.bw_total::cpu2.data 116216795 # To
|
|||
system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 877513594 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 219392 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.toL2Bus.throughput 977859373 # Throughput (bytes/s)
|
||||
system.toL2Bus.data_through_bus 244480 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
|
|
@ -124,7 +125,7 @@ type=ExeTracer
|
|||
type=EioProcess
|
||||
chkpt=
|
||||
errout=cerr
|
||||
file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||||
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||||
input=None
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
|
|
@ -153,6 +154,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
|
|
@ -225,7 +227,7 @@ type=ExeTracer
|
|||
type=EioProcess
|
||||
chkpt=
|
||||
errout=cerr
|
||||
file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||||
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||||
input=None
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
|
|
@ -254,6 +256,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu2.tracer
|
||||
|
|
@ -326,7 +329,7 @@ type=ExeTracer
|
|||
type=EioProcess
|
||||
chkpt=
|
||||
errout=cerr
|
||||
file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||||
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||||
input=None
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
|
|
@ -355,6 +358,7 @@ max_loads_any_thread=0
|
|||
numThreads=1
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
switched_out=false
|
||||
system=system
|
||||
tracer=system.cpu3.tracer
|
||||
|
|
@ -427,7 +431,7 @@ type=ExeTracer
|
|||
type=EioProcess
|
||||
chkpt=
|
||||
errout=cerr
|
||||
file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||||
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||||
input=None
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
|
|
@ -476,7 +480,6 @@ latency=30000
|
|||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.toL2Bus]
|
||||
|
|
|
|||
|
|
@ -8,5 +8,3 @@ gzip: stdout: Broken pipe
|
|||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
Redirecting stdout to build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout
|
||||
Redirecting stderr to build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 28 2013 09:19:43
|
||||
gem5 started Mar 28 2013 09:22:33
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/fast/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
|
||||
gem5 compiled Jun 8 2013 10:00:13
|
||||
gem5 started Jun 8 2013 10:00:28
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
main dictionary has 1245 entries
|
||||
|
|
@ -17,4 +15,4 @@ main dictionary has 1245 entries
|
|||
49508 bytes wasted
|
||||
49508 bytes wasted
|
||||
49508 bytes wasted
|
||||
>>>>Exiting @ tick 729071000 because a thread reached the max instruction count
|
||||
>>>>Exiting @ tick 729024000 because a thread reached the max instruction count
|
||||
|
|
|
|||
File diff suppressed because it is too large
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Reference in a new issue