ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in the se mode. Now ruby itself will provide the data.
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e8802fa127
commit
c061819890
7 changed files with 15 additions and 17 deletions
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@ -114,5 +114,7 @@ for (i, cpu) in enumerate(system.cpu):
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cpu.interrupts.int_master = system.piobus.slave
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cpu.interrupts.int_slave = system.piobus.master
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system.ruby._cpu_ruby_ports[i].access_phys_mem = True
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root = Root(full_system = True, system = system)
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Simulation.run(options, root, system, FutureClass)
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@ -187,6 +187,9 @@ if options.ruby:
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print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
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sys.exit(1)
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# Set the option for physmem so that it is not allocated any space
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system.physmem.null = True
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options.use_map = True
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Ruby.create_system(options, system)
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assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
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@ -41,7 +41,7 @@ class RubyPort(MemObject):
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pio_port = MasterPort("Ruby_pio_port")
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using_ruby_tester = Param.Bool(False, "")
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using_network_tester = Param.Bool(False, "")
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access_phys_mem = Param.Bool(True,
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access_phys_mem = Param.Bool(False,
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"should the rubyport atomically update phys_mem")
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ruby_system = Param.RubySystem("")
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system = Param.System(Parent.any, "system object")
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@ -52,6 +52,7 @@ class RubyPort(MemObject):
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class RubyPortProxy(RubyPort):
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type = 'RubyPortProxy'
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cxx_header = "mem/ruby/system/RubyPortProxy.hh"
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access_phys_mem = True
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class RubySequencer(RubyPort):
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type = 'RubySequencer'
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@ -67,3 +68,4 @@ class RubySequencer(RubyPort):
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class DMASequencer(RubyPort):
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type = 'DMASequencer'
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cxx_header = "mem/ruby/system/DMASequencer.hh"
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access_phys_mem = True
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@ -79,8 +79,8 @@ options.num_cpus = nb_cores
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# system simulated
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system = System(cpu = cpus,
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funcmem = SimpleMemory(in_addr_map = False),
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funcbus = NoncoherentBus(),
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physmem = SimpleMemory())
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physmem = SimpleMemory(null = True),
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funcbus = NoncoherentBus())
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Ruby.create_system(options, system)
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@ -100,12 +100,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
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#
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ruby_port.deadlock_threshold = 1000000
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#
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# Ruby doesn't need the backing image of memory when running with
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# the tester.
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#
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ruby_port.access_phys_mem = False
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# connect reference memory to funcbus
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system.funcmem.port = system.funcbus.master
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@ -74,5 +74,8 @@ for (i, cpu) in enumerate(system.cpu):
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cpu.interrupts.int_slave = system.piobus.master
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cpu.clock = '2GHz'
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# Set access_phys_mem to True for ruby port
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system.ruby._cpu_ruby_ports[i].access_phys_mem = True
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root = Root(full_system = True, system = system)
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m5.ticks.setGlobalFrequency('1THz')
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@ -77,7 +77,7 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer':
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tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
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wakeup_frequency = 10, num_cpus = options.num_cpus)
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system = System(tester = tester, physmem = SimpleMemory())
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system = System(tester = tester, physmem = SimpleMemory(null = True))
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Ruby.create_system(options, system)
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@ -104,12 +104,6 @@ for ruby_port in system.ruby._cpu_ruby_ports:
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#
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ruby_port.using_ruby_tester = True
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#
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# Ruby doesn't need the backing image of memory when running with
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# the tester.
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#
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ruby_port.access_phys_mem = False
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# -----------------------
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# run simulation
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# -----------------------
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@ -67,7 +67,7 @@ options.l3_assoc=2
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options.num_cpus = 1
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cpu = TimingSimpleCPU(cpu_id=0)
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system = System(cpu = cpu, physmem = SimpleMemory())
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system = System(cpu = cpu, physmem = SimpleMemory(null = True))
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Ruby.create_system(options, system)
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