From c0618198908b592ff0c165b671cb5d8d785d83ca Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Wed, 6 Mar 2013 21:53:57 -0600 Subject: [PATCH] ruby: remove the functional copy of memory in se mode This patch removes the functional copy of the memory that was maintained in the se mode. Now ruby itself will provide the data. --- configs/example/ruby_fs.py | 2 ++ configs/example/se.py | 3 +++ src/mem/ruby/system/Sequencer.py | 4 +++- tests/configs/memtest-ruby.py | 10 ++-------- tests/configs/pc-simple-timing-ruby.py | 3 +++ tests/configs/rubytest-ruby.py | 8 +------- tests/configs/simple-timing-ruby.py | 2 +- 7 files changed, 15 insertions(+), 17 deletions(-) diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py index 8d21cfb32..32ddb90bf 100644 --- a/configs/example/ruby_fs.py +++ b/configs/example/ruby_fs.py @@ -114,5 +114,7 @@ for (i, cpu) in enumerate(system.cpu): cpu.interrupts.int_master = system.piobus.slave cpu.interrupts.int_slave = system.piobus.master + system.ruby._cpu_ruby_ports[i].access_phys_mem = True + root = Root(full_system = True, system = system) Simulation.run(options, root, system, FutureClass) diff --git a/configs/example/se.py b/configs/example/se.py index fe5524ef5..20149cccd 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -187,6 +187,9 @@ if options.ruby: print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) + # Set the option for physmem so that it is not allocated any space + system.physmem.null = True + options.use_map = True Ruby.create_system(options, system) assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 9b243a8b9..68d02f53c 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -41,7 +41,7 @@ class RubyPort(MemObject): pio_port = MasterPort("Ruby_pio_port") using_ruby_tester = Param.Bool(False, "") using_network_tester = Param.Bool(False, "") - access_phys_mem = Param.Bool(True, + access_phys_mem = Param.Bool(False, "should the rubyport atomically update phys_mem") ruby_system = Param.RubySystem("") system = Param.System(Parent.any, "system object") @@ -52,6 +52,7 @@ class RubyPort(MemObject): class RubyPortProxy(RubyPort): type = 'RubyPortProxy' cxx_header = "mem/ruby/system/RubyPortProxy.hh" + access_phys_mem = True class RubySequencer(RubyPort): type = 'RubySequencer' @@ -67,3 +68,4 @@ class RubySequencer(RubyPort): class DMASequencer(RubyPort): type = 'DMASequencer' cxx_header = "mem/ruby/system/DMASequencer.hh" + access_phys_mem = True diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index 397e9f0c7..a252bc881 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -79,8 +79,8 @@ options.num_cpus = nb_cores # system simulated system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentBus(), - physmem = SimpleMemory()) + physmem = SimpleMemory(null = True), + funcbus = NoncoherentBus()) Ruby.create_system(options, system) @@ -100,12 +100,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): # ruby_port.deadlock_threshold = 1000000 - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # connect reference memory to funcbus system.funcmem.port = system.funcbus.master diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 0753472bc..23a0bb3d0 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -74,5 +74,8 @@ for (i, cpu) in enumerate(system.cpu): cpu.interrupts.int_slave = system.piobus.master cpu.clock = '2GHz' + # Set access_phys_mem to True for ruby port + system.ruby._cpu_ruby_ports[i].access_phys_mem = True + root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz') diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index 4b5b3a19c..861205acc 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -77,7 +77,7 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer': tester = RubyTester(check_flush = check_flush, checks_to_complete = 100, wakeup_frequency = 10, num_cpus = options.num_cpus) -system = System(tester = tester, physmem = SimpleMemory()) +system = System(tester = tester, physmem = SimpleMemory(null = True)) Ruby.create_system(options, system) @@ -104,12 +104,6 @@ for ruby_port in system.ruby._cpu_ruby_ports: # ruby_port.using_ruby_tester = True - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index 86869452a..41b4fdb1f 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -67,7 +67,7 @@ options.l3_assoc=2 options.num_cpus = 1 cpu = TimingSimpleCPU(cpu_id=0) -system = System(cpu = cpu, physmem = SimpleMemory()) +system = System(cpu = cpu, physmem = SimpleMemory(null = True)) Ruby.create_system(options, system)