Andreas Hansson c4898b15bc mem: Add DDR3 and LPDDR2 DRAM controller configurations ... This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward. The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration.		2013-01-31 07:49:14 -05:00
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configs	mem: Add DDR3 and LPDDR2 DRAM controller configurations	2013-01-31 07:49:14 -05:00
long	stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3	2013-01-28 07:44:26 -05:00
quick	regressions: update stats due to branch predictor changes	2013-01-24 12:29:00 -06:00
test-progs/hello	X86: Add a 32 bit hello world test binary.	2012-05-27 19:01:09 -07:00
diff-out	tests: fix diff-out script for op/inst stat changes.	2012-02-12 18:35:59 -06:00
halt.sh	Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.	2006-07-21 15:56:35 -04:00
run.py	tests: Add CPU switching tests	2013-01-07 13:05:52 -05:00
SConscript	tests: Add CPU switching tests	2013-01-07 13:05:52 -05:00