Commit graph

435 commits

Author SHA1 Message Date
Gabe Black
d21e037fb8 Made sparc copies of some architecture specific files.
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
    Formatting & doxygen.
arch/sparc/linux_process.cc:
    Added some more ioctl commands to ignore.
    Set unlink and rename to the new functions.
    Ignore setrlimit, times and rt_sigaction.
    Should eventually provide a function for times.
arch/sparc/linux_process.cc:
    Fixes for Linux emulation:
    - stat struct alignment
    - osf_{get,set}sysinfo return values
    - additional syscall numbers
    - initialize $r0 to 0
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
    Updated Copyright
arch/sparc/linux_process.cc:
    Alphabetize includes.
arch/sparc/linux_process.cc:
    Changed all syscalls to use syscall return object
arch/sparc/linux_process.cc:
    Removed unecessary constructor call at each return.
arch/sparc/linux_process.cc:
    Rename sim/universe.{cc,hh} to root.{cc,hh}.
arch/sparc/linux_process.cc:
    shuffle files around for new directory structure
arch/sparc/linux_process.cc:
    Remove RCS Id string
arch/sparc/linux_process.cc:
arch/sparc/linux_process.hh:
    Update copyright dates and author list
arch/sparc/linux_process.hh:
    remove $Id$ string
arch/sparc/linux_process.cc:
    Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).
arch/sparc/linux_process.cc:
    Added the endianness namespace. This may change.
arch/sparc/linux_process.cc:
    Replaced the namespace declaration with including arch/alpha/isa_traits.hh
arch/sparc/linux_process.cc:
    fixup for bsd hosts. Some headers are included by default which means that
    more variables need TGT_ prefixes and there isn't a stat call (everything
    is a stat64 call) so we have to work around that a bit
arch/sparc/linux_process.cc:
    Add endian conversions to fstat
arch/sparc/linux_process.cc:
    fix #if. I wonder why my compiler had no issues
arch/sparc/linux_process.cc:
    add endian conversions for fstat functions
arch/sparc/linux_process.cc:
    move architecture independent code into kern/linux/linux.(hh|cc)
arch/sparc/linux_process.hh:
    Add getDesc function
arch/sparc/linux_process.cc:
    Added using directive for AlphaISA namespace
arch/sparc/linux_process.cc:
    Add pipeFunc.
arch/alpha/linux_process.cc:
    Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc
arch/sparc/linux_process.cc:
    bk cp ../alpha/linux_process.cc linux_process.cc
arch/sparc/linux_process.hh:
    bk cp ../alpha/linux_process.hh linux_process.hh

--HG--
extra : convert_revision : a8eca1c5f848383263a2326b0e3cde4bcd85f14b
2006-03-01 05:20:47 -05:00
Gabe Black
e08cf8fee0 Changed the name of the fault's invocation method from ev5_trap to invoke.
--HG--
extra : convert_revision : b7ab14ac644f6a38c69aaa5372b3002b21f34af0
2006-03-01 01:23:10 -05:00
Gabe Black
69e91d7617 moved ev5_trap fully into the fault class.
--HG--
extra : convert_revision : 182cdec9a4e05f55edff0c6a114844b9ad2ca8db
2006-03-01 00:09:08 -05:00
Ali Saidi
26d7b5a4d1 Add quiesceNs, quiesceTime, quiesceCycles, and m5panic pseudo ops.
This changeset removes a check that prevents quiescing when an
interrupt is pending. *** You should only call quiesce if that
isn't a problem. ***

arch/alpha/isa/decoder.isa:
sim/pseudo_inst.cc:
sim/pseudo_inst.hh:
    Add quiesceNs, quiesceCycles, quisceTime and m5panic pseudo ops.
    These quiesce for a number of ns, cycles, report how long
    we were quiesced for, and panic the simulator respectively.
    The latter is added to the panic() function in the console and linux
    kernel instead of executing an infinite loop until someone notices.
cpu/exec_context.cc:
cpu/exec_context.hh:
    Add a quiesce end event to the execution contexted which upon
    executing wakes up a CPU for quiesceCycles/quiesceNs.
util/m5/Makefile:
    Make the makefile more reasonable
util/m5/m5.c:
    update the m5op executable to use the files from the linux tree
util/m5/m5op.S:
    update m5op.S from linux tree
util/m5/m5op.h:
    update m5op.h from linux tree

--HG--
rename : util/m5/m5op.s => util/m5/m5op.S
extra : convert_revision : 3be18525e811405b112e33f24a8c4e772d15462d
2006-02-28 18:41:04 -05:00
Kevin Lim
34da58a698 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean

arch/alpha/ev5.cc:
cpu/o3/regfile.hh:
    Hand merge.

--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
extra : convert_revision : c941dd2198851398820b38a66471372ed8454891
2006-02-28 15:16:24 -05:00
Gabe Black
f7360d5bca Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 0b3ffc0605c9043d7f5bf6c15f4a3c68846a732a
2006-02-28 06:13:35 -05:00
Gabe Black
d207168eda Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 3a3ff8fcf472db385219a00ae434d1f3fea43b18
2006-02-28 06:03:57 -05:00
Gabe Black
299efffaf5 Cleaned up and slightly reorganized the Fault class heirarchy.
arch/alpha/ev5.cc:
    Changed c style casts of Faults to dynamic_casts
arch/alpha/faults.cc:
    AlphaFault is now an abstract class.
arch/alpha/faults.hh:
    AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes.
cpu/o3/alpha_cpu_impl.hh:
    Changed a c style cast to a dynamic_cast for a Fault
sim/faults.hh:
    All generic Fault classes are now abstract. Also, MachineCheckFault and AlignmentFault inherit FaultBase as a virtual base class to help resolve ambiguities when they are multiply inherited in ISA specific classes. The override the isMachineCheckFault and isAlignmentFault functions appropriately, and provide a standard name for these faults.

--HG--
extra : convert_revision : 2cb906708e3eaec4a12587484c09e50ed6ef88fc
2006-02-28 06:02:18 -05:00
Gabe Black
6165419d35 Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context.
--HG--
extra : convert_revision : 56e33536cdd9079ace03896b85ea3c84b6eb4e57
2006-02-27 23:26:13 -05:00
Gabe Black
36b2d9815e Moved the _stat for MachineCheckFault and AlignmentFault into the isa specific classes to prevent instantiation of the generic classes.
--HG--
extra : convert_revision : 0378261342df008c2bf6d260295ef21b15f119a8
2006-02-27 16:46:00 -05:00
Gabe Black
2f7b8ab1ec Got rid of the fault_addr function.
--HG--
extra : convert_revision : deb54cd82db47abb6d9bac76e072f2a4b1c883b2
2006-02-27 16:27:01 -05:00
Kevin Lim
96fd6b5c40 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean

--HG--
extra : convert_revision : 97c345f0715a347ce34f9cabd994485f30f2e171
2006-02-27 12:09:08 -05:00
Kevin Lim
70b35bab57 Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
2006-02-27 11:44:35 -05:00
Gabe Black
f1ef4a8f06 Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc
--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/tlb.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision : 9fe6863cc37347d2a6bd716c529b0a4a50b36ea7
2006-02-27 06:05:10 -05:00
Gabe Black
c5dcd152f2 Changed targetarch to just arch.
SConscript:
    Changed all of the "targetarch" files to be "arch" files
arch/SConscript:
    Added all of the remaining targetarch files to isa_switch_hdrs

--HG--
extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480
2006-02-27 05:35:43 -05:00
Gabe Black
07cd7e966e Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class, and replaced the isA templated function with them where appropriate.
arch/alpha/ev5.cc:
cpu/simple/cpu.cc:
    Changed from the isA templated function to isMachineCheckFault and isAlignmentFault
sim/faults.hh:
    Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class.

--HG--
extra : convert_revision : 3bf3a4369bc24a039648ee4f2a9c1663362ff2e2
2006-02-27 04:02:45 -05:00
Gabe Black
f9c2b9e74f Put the Alpha faults into the AlphaISA namespace
--HG--
extra : convert_revision : d9586bb8ffaab74673aa0b3d17bb676b949ff212
2006-02-27 04:00:24 -05:00
Gabe Black
444f520f7e MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly.
arch/alpha/alpha_memory.cc:
cpu/base_dyn_inst.cc:
dev/alpha_console.cc:
dev/pcidev.hh:
dev/sinic.cc:
    MachineCheckFaults are now generated by the ISA, rather than being created directly.

--HG--
extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19
2006-02-27 03:57:15 -05:00
Steve Reinhardt
63db9860cf Make sure cpu/static_inst_exec_sigs.hh get rebuilt when
CPU_MODELS parameter changes.

arch/SConscript:
    Fix typo in comment.
cpu/SConscript:
    Convert exec signature generator to Action so we can add dependency
    on CPU_MODELS environment var.
    Print nicer string while we're at it.
    Also add some comments.

--HG--
extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
2006-02-25 22:57:46 -05:00
Gabe Black
e66f521d5b Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

SConscript:
arch/alpha/ev5.cc:
dev/alpha_console.cc:
    Hand merged

--HG--
extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
2006-02-24 18:45:28 -05:00
Steve Reinhardt
7a37037358 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/stever/bk/multiarch

arch/isa_parser.py:
    SCCS merged

--HG--
extra : convert_revision : 080cca7616b37db3bf18976b63b3dbcb47d8b918
2006-02-24 08:52:38 -05:00
Gabe Black
08637efadc Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type.
arch/alpha/alpha_memory.cc:
arch/alpha/isa/decoder.isa:
    Added news where faults are created.
arch/alpha/ev5.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Changed Fault to be a RefCountingPtr
arch/alpha/isa/fp.isa:
    Added a new where a FloatEnableFault was created.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
    Added a new where an UnimplementedFault is created.
base/refcnt.hh:
    Added include of stddef.h for the NULL macro
cpu/base_dyn_inst.cc:
    Added a new where an UnimplementedOpcodeFault is created.
cpu/o3/alpha_cpu_impl.hh:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name()
cpu/o3/regfile.hh:
    Added new where UnimplementedOpcodeFaults are created.
cpu/simple/cpu.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created.
dev/alpha_console.cc:
    Added news where MachineCheckFaults are created.
dev/pcidev.hh:
    Added news where MachineCheckFaults are generated.
dev/sinic.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables.
kern/kernel_stats.cc:
    Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future.
kern/kernel_stats.hh:
    Commented out the declaration of _fault. when fault() is called, the fault increments its own stat.
sim/faults.cc:
sim/faults.hh:
    Changed Fault from a FaultBase * to a RefCountingPtr.

--HG--
extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d
2006-02-24 01:51:45 -05:00
Korey Sewell
f6cac25dcf name changes ...
SConscript:
    change to alpha_memory.hh

--HG--
rename : arch/alpha/memory.cc => arch/alpha/alpha_memory.cc
rename : arch/alpha/memory.hh => arch/alpha/alpha_memory.hh
extra : convert_revision : 62b1a41de22701160f04cb7a78242746cfcde819
2006-02-23 18:46:12 -05:00
Steve Reinhardt
51647e7bec Enable building only selected CPU models via new scons
CPU_MODELS parameter.  For example:
scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug
Unfortunately the option is not sticky due to a scons
bug with saving & restoring ListOption parameters.

SConscript:
    Separate out cpu-model-specific files so they can be conditionally
    included based on value of new CPU_MODELS parameter.
    Most of these are now handled in cpu/SConscript, except for FullCPU
    which is still in this file.
arch/SConscript:
    The set of CPU-model-specific execute files must now be
    determined from the CPU_MODELS parameter, via the new
    cpu_models.py file.
    Also pass the list of configured CPU models to isa_parser.py.
arch/isa_parser.py:
    Move CpuModel definition and objects out to a
    separate file so they can be shared with scons.
    Global list of CPU models to generate code for is now
    controlled by command-line parameters (so we can do
    only a subset of the available ones).
build/SConstruct:
    Define new CPU_MODELS ListOption.
cpu/static_inst.hh:
    Rename static_inst_impl.hh to static_inst_exec_sigs.hh.

--HG--
extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
2006-02-23 17:00:29 -05:00
Ali Saidi
4f831bc561 ev5.cc:
SCCS merged

arch/alpha/ev5.cc:
    SCCS merged

--HG--
extra : convert_revision : 9d70c1d461dab0ec016fd0616d74a49942aac659
2006-02-23 15:08:08 -05:00
Ali Saidi
e1c3acd91c Merge zizzer:/bk/m5
into  zeep.eecs.umich.edu:/z/saidi/work/m5.head

cpu/simple/cpu.cc:
    remove initCPU from constructor
dev/alpha_console.cc:
    we are panicing, so no need to return a fault

--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
2006-02-23 15:06:06 -05:00
Ali Saidi
1166d4f0bf Get rid of the xc from the alphaAccess/alphaConsole backdoor device.
Now allocate an array of stacks indexed by cpu number which specify
cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for
their stacks before continuing. This change *REQUIRES* a the new
console code to operate correctly.

arch/alpha/ev5.cc:
    Add cpuId to initCPU/initIPR functions
cpu/o3/cpu.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move the cpu initilization into an init() function since it now needs
    the CPU id which isn't known at construction
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
    instead of the bootstrap variables, add space for 64 cpu stacks in the
    alpha access structure.
sim/system.cc:
    start all cpus immediately rather than just the first one

--HG--
extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
2006-02-23 14:50:16 -05:00
Steve Reinhardt
99484cfae8 Create a Builder object for .isa files in arch/SConscript.
Start using SCons File objects to avoid fixed paths in
subordinate SConscripts.

SConscript:
    Push isa_parser stuff (including .isa scanner) down into
    arch/SConscript.
arch/SConscript:
    Create a Builder object for .isa files, including existing scanner.
    Return file objects generated by isa-specific SConscript
    back up to parent.
arch/alpha/SConscript:
arch/mips/SConscript:
arch/sparc/SConscript:
    Convert sources to scons File objects, so file names can be specified
    relative to the current directory.
    Invoke new builder for isa description, and get generated sources from
    there (instead of listing them explicitly).
arch/isa_parser.py:
    Get rid of third argument ("include_path").
    It was a pain to generate this from scons, and it turned out
    it's not needed anyway, since the only included file
    (decoder.hh) will be in the same directory as the sources.

--HG--
extra : convert_revision : 36861bcef36763f229704d8cb7a642b4486a3581
2006-02-23 14:31:15 -05:00
Steve Reinhardt
c13ea339dc Add pipe() syscall to Alpha Linux emulation.
arch/alpha/alpha_linux_process.cc:
    Add pipeFunc.

--HG--
extra : convert_revision : c094d2dff993d5e60bc43b7cd4b9586c15c634a3
2006-02-23 08:16:59 -05:00
Gabe Black
5ecaaa0fb0 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 850077a56aead260aa4bbd3df60b672a931d57ed
2006-02-23 04:08:55 -05:00
Steve Reinhardt
f67a99d1c9 Auto-generate arch/foo.hh "switch headers" in scons.
SConscript:
    Include new arch/SConscript file.
arch/isa_specific.hh:
    Get rid of unnecessary ISA_INCLUDE() macro and other
    things that were used only for that purpose.
build/SConstruct:
    Move list of ISAs to env var ALL_ISA_LIST.

--HG--
extra : convert_revision : 612c7ee4279d57209662be88dc577d80fdbd692c
2006-02-22 22:22:06 -05:00
Steve Reinhardt
9a4c0f12ef Clean excess comments out of SConscripts.
SConscript:
arch/alpha/SConscript:
    Clean out excess comments.

--HG--
extra : convert_revision : 7aae68d36f9fce5f236d117d803b5e3cd4a3769d
2006-02-22 21:11:45 -05:00
Korey Sewell
9bc7f13eeb make sure alpha still compiles , rename files back to original naming ...
Now that we have decoder.do, add new files so we can start compiling other files
needed for MIPS syscall emulation mode

arch/mips/linux_process.cc:
arch/mips/linux_process.hh:
    New MIPS-specific file

--HG--
rename : arch/alpha/linux_process.cc => arch/alpha/alpha_linux_process.cc
rename : arch/alpha/linux_process.hh => arch/alpha/alpha_linux_process.hh
rename : arch/alpha/tru64_process.cc => arch/alpha/alpha_tru64_process.cc
rename : arch/alpha/tru64_process.hh => arch/alpha/alpha_tru64_process.hh
extra : convert_revision : 2bfc27e8772523cbeb95f40684f9a32fe5554f87
2006-02-22 04:08:08 -05:00
Korey Sewell
2d2510e94f Still builds "../MIPS_SE/arch/mips/decoder.do with no errors!
-----
uncomment out detailed model ... just commented to supress some compile errors

arch/isa_parser.py:
    uncomment out detailed model ... just commented to supress some compile errors

--HG--
extra : convert_revision : e884b9bd47794409f74043ad1aca6dadd1323185
2006-02-22 03:44:21 -05:00
Korey Sewell
54b47bc5ae MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!!
arch/mips/faults.hh:
    remove nonsense
arch/mips/isa/base.isa:
    define R31
arch/mips/isa/bitfields.isa:
    forgotten bitfields
arch/mips/isa/decoder.isa:
    INT64 -> int64_t
arch/mips/isa/formats.isa:
    fix comments
arch/mips/isa/formats/branch.isa:
    Branch -> BranchLikely
    RB -> RT
arch/mips/isa/formats/fp.isa:
    Make FP ops generates
arch/mips/isa/formats/mem.isa:
    RA,RB -> RS,RT
arch/mips/isa/formats/noop.isa:
    Rc -> Rd
arch/mips/isa/formats/util.isa:
    forgot brace and semicolon
arch/mips/isa/includes.isa:
    remove unnecessary files
arch/mips/isa_traits.hh:
    spacing
cpu/static_inst.hh:
    add cond_delay_slot flag

--HG--
extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
2006-02-22 03:33:35 -05:00
Korey Sewell
37cd6695eb Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch

--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh
extra : convert_revision : c641ba3c1009829b7276279b2dca441be1da5b30
2006-02-21 22:06:18 -05:00
Korey Sewell
a4799a89de Renaming alpha files and changing some MIPS stuff to be more like Alpha version
SConscript:
    changed the alpha_memory.hh to memory.hh in SConscript
arch/isa_parser.py:
    temporarily comment out o3 model
arch/mips/isa/base.isa:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
    Fix Up Base Class to mirror how Alpha generates StaticInsts
arch/mips/faults.cc:
    MIPS fault.cc file
arch/mips/faults.hh:
    MIPS fault.hh file

--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
2006-02-21 22:02:05 -05:00
Gabe Black
8d80fd1477 Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
2006-02-21 20:10:40 -05:00
Gabe Black
3f7979c99d Made Addr a global type
--HG--
extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
2006-02-21 03:38:21 -05:00
Ron Dreslinski
d96de69abc Add in a new translating port that allows syscalls to translate addresses via the page table before accessing the memory port.
Other compile issues cleaned up.

SConscript:
    Changes to compile the new Translating Port.
    Split out memtester and eio support, will rework them back in after first getting a simpleCPU to work
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Changes to use the new translating Port.
cpu/exec_context.cc:
cpu/exec_context.hh:
    Create a translating port in each execution context.
sim/process.cc:
    Fix the way we do proxy memory

--HG--
extra : convert_revision : 3d33218fe8b425a5d9ce24757f1112b4aa6001fd
2006-02-20 23:26:39 -05:00
Korey Sewell
bdf3fd92ba make MIPS specific
--HG--
extra : convert_revision : c019fad60fbf1a316bc6201b8ce8acf5a9875989
2006-02-20 14:48:10 -05:00
Korey Sewell
19534176e0 load/store instruction format ... now generates load/store code
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.

arch/mips/isa/bitfields.isa:
    comment change
arch/mips/isa/decoder.isa:
    re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
    Define LoadMemory & Store Memory formats
    Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
    Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
    change shw->sh and uhw->uh

--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
2006-02-20 14:30:23 -05:00
Korey Sewell
38ce95db3b Support for All Jump Instructions ...
Redo format for Branches and Jumps ( Must update NNPC not NPC )

Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!!

arch/mips/isa/decoder.isa:
    Support for All Jump Instructions ..
arch/mips/isa/formats/branch.isa:
    Redo format for Branches and Jumps ( Must update NNPC not NPC )
arch/mips/isa/formats/util.isa:
    define clear_exe_inst_hazards for later use

--HG--
extra : convert_revision : 63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
2006-02-20 01:49:16 -05:00
Gabe Black
7c642b7106 Reapplied changes which were undone by a pull
arch/alpha/faults.hh:
kern/linux/linux.hh:
    Added typedef for Addr
kern/tru64/tru64.hh:
    Fixed up namespaces

--HG--
extra : convert_revision : bf968e615bc0acc96abeb0eec0872f5b02b5a065
2006-02-19 04:00:05 -05:00
Gabe Black
f721a4d9ad Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

arch/alpha/faults.hh:
    ur
    Using cleaned up fault class deiffinitions

--HG--
extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
2006-02-19 03:20:05 -05:00
Gabe Black
0e4a80df1a Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
2006-02-19 02:34:52 -05:00
Gabe Black
463aa6d49d Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
    Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
    Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
    Added using directive for AlphaISA
arch/alpha/ev5.hh:
    Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
    Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
    Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
    Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
    Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
    Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
    Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
    Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
    Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
    Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
    Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
    Added a typedef for Addr
base/loader/symtab.hh:
    Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
    Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
    Added typedefs for Addr and MachInst
cpu/base.cc:
    Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
    Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
    Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
    Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
    Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
    Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
    Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
    Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
    Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
    Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
    Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
    untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
    Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
    Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
    Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
    Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
    Cleaned up namespace issues
cpu/o3/cpu.hh:
    Cleaned up namespace usage
cpu/o3/decode.hh:
    Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
    Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
    Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
    Removed typedef of ISA
cpu/o3/iew_impl.hh:
    Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
    Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
    Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
    Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
    Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
    Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
    Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
    Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
    Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
    Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
    Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
    Untemplatized StaticInst
cpu/static_inst.hh:
    Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
    Added using namespace AlphaISA
dev/simple_disk.hh:
    Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
    Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
    Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
    Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
    Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
    Added TheISA to Addr type in structs
sim/process.hh:
    Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
    Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
    Added typecast for Addr, and TheISA namespace specifier for where needed

--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-19 02:34:37 -05:00
Ali Saidi
14f2cdb1a1 Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

--HG--
extra : convert_revision : 774e4afbb0f9c3ae62843138b6d7195ea184ff92
2006-02-19 00:47:45 -05:00
Ali Saidi
00d58aeb4d forgot a negative sign
--HG--
extra : convert_revision : 9cdb00198979fca831d3e6840f9c534671ccead3
2006-02-19 00:28:53 -05:00
Ali Saidi
53d2c9398e Move Linux/Tru64 architecture independent code into kern/*
leaving dependent code making way  for solaris linux syscall emu.

SConscript:
    Add two new files for syscall emulation
    Add getDesc() function
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    move architecture independent code into kern/linux/linux.(hh|cc)
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
    Add getDesc function
kern/linux/linux.hh:
    move generi linux syscall emulation code into kern/linux
kern/tru64/tru64.hh:
    move generi tru64 syscall emulation code into kern/tru64
sim/process.cc:
sim/process.hh:
    Push the function determination and calling stuff down to LiveProcess
    and out of the Linux/Tru64 classes respectively
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    fnctl implementation was identical in tru64 and linux so moved to generic

--HG--
extra : convert_revision : 103293dbe6fe2f7892de4929d17dc085def77026
2006-02-18 23:44:22 -05:00
Korey Sewell
a48c24b61e Support NNPC and branch instructions ... Outputs to decoder.cc correctly
Edits to the CPU model may still need to be made to handle branch likely insts...

arch/isa_parser.py:
    add a NNPC operand ...
arch/mips/isa/base.isa:
    change SPARC to MIPS
arch/mips/isa/decoder.isa:
    typo < to >=
arch/mips/isa/formats/basic.isa:
    spacing
arch/mips/isa/formats/branch.isa:
    add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
    support for NNPC and R31
arch/mips/isa_traits.hh:
    NNPC Addr variable

--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
2006-02-18 23:17:45 -05:00
Gabe Black
bf4fb61fa1 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 8b2759d670a6a60142be748817ccef736d61dabf
2006-02-18 20:58:26 -05:00
Gabe Black
db40f25616 Changed the isa from a class to a namespace, untemplated StaticInst and StaticInstPtr, converted things to using TheISA, cleaned up some header file paths, and improved the system which pulls header files from the appropriate architecture.
--HG--
extra : convert_revision : 5087333fbaf442efb4b55e70376244629fff507d
2006-02-18 20:58:08 -05:00
Korey Sewell
bd17580928 changes from mergedmem
arch/mips/isa/formats/branch.isa:
    add branch_likely member functions
cpu/base.hh:
cpu/exec_context.hh:
cpu/static_inst.hh:
    change from mergedmem

--HG--
extra : convert_revision : d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
2006-02-18 14:38:23 -05:00
Korey Sewell
159e334531 use string name to figure out if we have a "AndLink" instruction
arch/mips/isa/operands.isa:
    uq -> uw

--HG--
extra : convert_revision : eeac6dba813de8174d080a5fa9b5a396b345113a
2006-02-18 04:17:11 -05:00
Korey Sewell
6bf71f96f3 MIPS generates ISA code through scons '.../decoder.cc'!!!
Now, must create g++ compilable code ...

arch/mips/isa/decoder.isa:
    missing a '}' ... edited a few instruction decodings ...
arch/mips/isa/formats.isa:
    rearranged #include
arch/mips/isa/formats/branch.isa:
    add Branch Likely  and Unconditional format
arch/mips/isa/formats/int.isa:
    move OperateNopCheckDecode template to another file ...
arch/mips/isa/formats/noop.isa:
    change Alpha to Mips in noop.isa

--HG--
extra : convert_revision : 4bf955fa6dffbbc99fb95fee7878f691e3df5424
2006-02-18 03:12:04 -05:00
Kevin Lim
d6a330ebb9 Remove fake fault.
Switch fault pointers to const pointers to prevent them from accidentally being changed.
Fix some coding style.

arch/alpha/ev5.cc:
cpu/o3/commit_impl.hh:
kern/kernel_stats.hh:
    Remove fake fault.
arch/alpha/faults.cc:
    Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally.
arch/alpha/faults.hh:
    Fix to have normal m5 line length limit, change pointers to const pointers.
sim/faults.cc:
sim/faults.hh:
    Remove fake fault, change pointers to const pointers.

--HG--
extra : convert_revision : 01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e
2006-02-16 14:55:15 -05:00
Kevin Lim
c7624c26e7 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-new

arch/alpha/isa/mem.isa:
    Hand merge.

--HG--
extra : convert_revision : c557aa4c867d84ab01139e509ee9f2ed05dd8ea0
2006-02-16 12:03:44 -05:00
Kevin Lim
485568efa9 Fixes to handle generating the initiateAcc and completeAcc functions a little more cleanly.
arch/alpha/isa/mem.isa:
    Avoid explicitly declaring the Mem variable.  Instead break up the code blocks used to generate the initiate and complete functions.  The templates reflect which operands need to be declared for each function (src, dest, or both).

    Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete.
    Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete.
arch/isa_parser.py:
    Remove hack for mem ops.

--HG--
extra : convert_revision : a367797a2cb698762bfc27be1da00bcbe9367150
2006-02-16 11:55:28 -05:00
Korey Sewell
7446238118 Get ISA parser to at least include all the ISA correctly ... crashes with "None" error
arch/mips/isa/decoder.isa:
    CondBranch format split up into Branch & BranchLikely formats
arch/mips/isa/formats.isa:
    include util.isa
arch/mips/isa/formats/branch.isa:
    erroneous 'e' at top of code
arch/mips/isa/formats/util.isa:
    util.isa

--HG--
extra : convert_revision : 4fc44a05e2838749e66cd70f210e8a718b34cbf3
2006-02-16 02:51:04 -05:00
Korey Sewell
e7d16b0aef Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 17b164847aee7e21d15d1a9d99aae43f46906c28
2006-02-16 02:40:04 -05:00
Korey Sewell
7c9ea671af file name changes ... minor ISA changes
arch/mips/isa/base.isa:
    restoring base.isa file ...
arch/mips/isa/formats/basic.isa:
    add c++ emacs header
arch/mips/isa/formats/branch.isa:
    added branch likely format
arch/mips/isa/formats/int.isa:
    small change to python code

--HG--
extra : convert_revision : defd592abb1a724f5f88b19c197b858420e92d17
2006-02-16 02:39:46 -05:00
Gabe Black
00f451cc02 Some changes which weren't needed before doing a bk pull were needed afterwards, for some reason.
arch/alpha/ev5.cc:
    Took out the unnecessary check for a null Fault pointer.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault *, and removed underscores from fault names.

--HG--
extra : convert_revision : 367a58a375f911185ddcc5fc826034af96427461
2006-02-16 02:08:13 -05:00
Gabe Black
b161d2a731 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d
2006-02-16 01:25:48 -05:00
Gabe Black
10c79efe55 Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-16 01:22:51 -05:00
Gabe Black
7f17f1f2df Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : b4bbf63ec3b1c6de0ea7220e6dda5366c0529c07
2006-02-15 23:24:35 -05:00
Ron Dreslinski
d142788172 More compilation fixes.
Should we add a proxy_port that does the v->p address translation?
Should the proxy port return a fault on translation errors, if we add one?

arch/alpha/alpha_linux_process.cc:
    Syscalls use a memPort through the CPU now instead of a xc functional memory.
cpu/base.hh:
    Add a pointer to the memPort syscalls will use.  Should this be a proxy_port that does address translation?
cpu/exec_context.cc:
cpu/exec_context.hh:
    Remove functional memory from the exec context
cpu/simple/cpu.cc:
    Set the memPort to be used as the syscall port as the dcache port
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Syscalls use a memPort through the CPU now instead of a xc functional memory.
    Also, fix the fact that readStringFunctional doesn't return a fault... should proxy_port handle this because it is doing the translation?

--HG--
extra : convert_revision : 1f65318c6594301a75dc4dc0c99fdd436b094a7f
2006-02-15 22:05:23 -05:00
Ron Dreslinski
90def9ea9e Changes to start making the tree use the new memory system. Trying to compile decoder.cc but fails still.
SConscript:
    Place the memory objects back in the right place
arch/alpha/isa_desc:
    Fix includes to point to the new memory requests
cpu/exec_context.hh:
    Exec context now points to memory object, fix the include paths.
    Convert to prot_read/prot_write functions instead of read and write.
    Convert to new CpuRequestPtr instead of MemReqPtr.
mem/request.hh:
    Add back in support for Request Flags (needed by decoder to tag request) Removed the flags that were associated with packets/coherence.
sim/process.hh:
    Converted to point to new memory objects

--HG--
extra : convert_revision : a0b95380915d63b53194e2a26336d6adb1a0086b
2006-02-15 14:53:02 -05:00
Korey Sewell
a0cdf213ab ...
arch/mips/isa/base.isa:
    restore base.isa

--HG--
extra : convert_revision : a551caae28f505b22bceae3297fc00b0fb6a0e23
2006-02-15 14:08:54 -05:00
Kevin Lim
2d04f18674 Gives separate methods for initiating and completing a memory access, which will be helpful for the merged memory model.
arch/alpha/isa/mem.isa:
    Include methods that allow a memory operation to be split between the part that initiates the access, and the part that completes the access.  In these functions the Mem variable is explicitly declared; in the default execute functions, the Mem variable is still handled through %(op_decl)s.
arch/isa_parser.py:
    Include recording the type of the memory access variable so that it can be used if it needs to be explicitly declared in a template.

    Have memory operands consider themselves neither a source nor a destination to avoid including themselves on the op_src_decl list or the op_dest_decl list.

    Record op_src_decl and op_dest_decl lists to allow for declaring only source or destination operands.  This is needed for the split memory access methods.

--HG--
extra : convert_revision : f674f7a2f747ae40ba8c3a0933b0337c87ee0b6c
2006-02-15 13:05:21 -05:00
Ali Saidi
7b42d61f13 Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

sim/byteswap.hh:
    SCCS merged

--HG--
extra : convert_revision : 65989fef265ddfafb59a6c96e3cdde76eb3e071d
2006-02-15 01:27:06 -05:00
Ali Saidi
18a0fa3e0c endian fixes and compiles on mac os x
arch/alpha/alpha_linux_process.cc:
    add endian conversions for fstat functions
arch/alpha/alpha_tru64_process.cc:
    add endian conversions for various functions
sim/byteswap.hh:
    for some reason gcc on macos really wants long and unsigned long
    Why int32_t and uint32_t isn't sufficient I don't know.
sim/process.cc:
sim/syscall_emul.hh:
    endian fixes

--HG--
extra : convert_revision : ce625d5660b70867c43c74fbed856149c0d8cd36
2006-02-15 01:23:13 -05:00
Korey Sewell
aee1bf5873 Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 5b0a3dd1a52ca9b29ea4a1c505a7435bfd6110fe
2006-02-14 22:43:26 -05:00
Korey Sewell
23bbec6a34 another big step to a parsable ISA ... no errors after I used a symbolic link for
arch/alpha/main.isa to test my files ...

arch/mips/isa/operands.isa:
    use sd and ud instead of sdw and udw

--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
2006-02-14 22:43:14 -05:00
Korey Sewell
5830200d78 trying to get ISA to parse correctly ...
arch/mips/isa/formats/unimp.isa:
    holds unimplemented formats
arch/mips/isa/formats/unknown.isa:
    holds unknown formats

--HG--
extra : convert_revision : 0f3a8ea7e3a1592322cce54527d6989152e57975
2006-02-14 21:26:01 -05:00
Gabe Black
7826fcd09d New files to fix building the SPARC_SE and MIPS_SE isa_parser.py generated files.
--HG--
extra : convert_revision : 94a9543376f8b4709a4aef54c5ac0d6f582a9dad
2006-02-14 20:13:08 -05:00
Gabe Black
085b73fe44 Fixed a path in the alpha isa description.
--HG--
extra : convert_revision : 2a73ef7703ffe5c5232619698a16c8b4ee265a21
2006-02-14 03:57:42 -05:00
Korey Sewell
9f584bcc6f Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 62d9346c44d5b7d455414fbebf0da3a8ef8d0754
2006-02-14 02:12:39 -05:00
Korey Sewell
d7ac2b56c2 make MIPS MT instructions decodable ...
arch/mips/isa/bitfields.isa:
    extra bitfield for decoding

--HG--
extra : convert_revision : 27f0afc3ee6ce00a94f44b2b1ac160ec26030866
2006-02-14 02:03:14 -05:00
Gabe Black
19e5efed03 Pseudo instructions are now passed whatever instructions they need by the decoder, rather than extracting them explicitly. This lets most of the pseudo instruction code to be shared across architectures.
SConscript:
    Moved pseudo_inst.hh from targetarch to full system sources
arch/alpha/SConscript:
    Moved pseudo_inst.cc out of the alpha specific sources
arch/alpha/isa/decoder.isa:
    The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI
arch/alpha/isa/main.isa:
    Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly
sim/pseudo_inst.cc:
    Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments.
sim/pseudo_inst.hh:
    Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context.

--HG--
rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc
rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh
extra : convert_revision : 76ce768cf1d8a838aa7b64878a7ab4c4215ac999
2006-02-12 17:38:10 -05:00
Gabe Black
2c5e03550a Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh.
SConscript:
    Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
    targetarch/isa_traits.hh is now included through arch/isa_traits.hh
    vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
    Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
    Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
    Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
    Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
    Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
    Fixed the assert in the equals operator.
    Changed the AlphaISA namespace reference to TheISA.
    Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
    Added an include of arch/isa_traits.hh so that TheISA would be defined.

--HG--
extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
2006-02-12 12:40:58 -05:00
Gabe Black
4d4c105ac5 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : baf9b0eb84df7da8152ddf9a25264e041a24b8ca
2006-02-12 12:17:51 -05:00
Gabe Black
47a065d9f0 vptr.hh:
Rename: arch/alpha/vptr.hh -> sim/vptr.hh

--HG--
rename : arch/alpha/vptr.hh => sim/vptr.hh
extra : convert_revision : 345745efec49f6169d1d9f61fd590240a995373b
2006-02-12 12:14:14 -05:00
Gabe Black
94590a4dba Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 427b5c957f91e66271444acebc01e1a861790363
2006-02-12 11:38:26 -05:00
Steve Reinhardt
79613686f0 Polishing of isa_parser.py internal operand handling, resulting in
minor change to syntax of 'def operands' in ISA descriptions.

arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
    Change 'def operands' statement to work with new
    isa_parser changes.
arch/isa_parser.py:
    Merge OperandTraits and OperandDescriptor objects into a
    unified hierarchy of Operand objects.
    Required a change in the syntax of the 'def operands'
    statement in the ISA description.

--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
2006-02-12 00:31:19 -05:00
Steve Reinhardt
8f2e096275 Minor cleanup of operand type and traits code in isa_parser.py.
arch/isa_parser.py:
    Minor cleanup of operand type and traits code:
    - build operand size map right away when types are defined
    instead of waiting to do it lazily
    - check that operand types have been defined before operands
    - don't use 'type' as a variable name
    - use isinstance() instead of checking for types directly

--HG--
extra : convert_revision : 099c1ee8d490f9c38316749bf87209388c55c971
2006-02-11 21:26:49 -05:00
Steve Reinhardt
3cc6c59582 Add keyword parameters and list-valued arguments to
instruction format functions in ISA description language.

Take advantage of these features to clean up memory
instruction definitions in Alpha.

arch/alpha/isa/decoder.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
    Take advantage of new keyword parameters to disambiguate
    instruction vs. memory-request flags, and to provide
    a default EA calculation for memory ops (since 99% of them
    are the same).
arch/isa_parser.py:
    Add two new features to instruction format functions:
    - Keyword parameters, a la Python.
    - List-valued arguments.

    Also export makeList() function to Python code blocks,
    as this is handy for dealing with flags.

--HG--
extra : convert_revision : 99bbbaa2e765230aa96b6a06ed193793325f9fb0
2006-02-11 15:11:00 -05:00
Ali Saidi
59ba3d463c fix #if. I wonder why my compiler had no issues. Even though it is clearly
wrong

arch/alpha/alpha_linux_process.cc:
    fix #if. I wonder why my compiler had no issues

--HG--
extra : convert_revision : 880a0442b28811db5ec548ce940060d4b26ec634
2006-02-11 11:01:51 -05:00
Ali Saidi
96d6ac441c hello world works on a BE host for a LE guest
arch/alpha/alpha_linux_process.cc:
    Add endian conversions to fstat
sim/byteswap.hh:
    for some reason I don't understand g++ really wanted a long version defined
    even though int32_t should be the same.

--HG--
extra : convert_revision : 5bfe9d3f0b31824fa5a7ae3f51fd0be5ed4d555d
2006-02-11 00:55:36 -05:00
Ali Saidi
f2e97427be Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

--HG--
extra : convert_revision : b8631bcea38e3a75e4442927500ddfc7763ba9cf
2006-02-10 20:06:44 -05:00
Gabe Black
b070018266 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 219377d0e4b70c30c17644991f39282b4aef14f8
2006-02-10 17:35:26 -05:00
Ali Saidi
a86a3fa525 Merge zizzer:/bk/m5
into  udhcp-macvpn-776.public.engin.umich.edu:/Users/ali/work/m5.head

--HG--
extra : convert_revision : e9ffaa1d4b7eee1f5bd0c492e162aac1e0806099
2006-02-10 14:38:15 -05:00
Ali Saidi
fb7899aa68 fix problems on darwin/*BSD for syscall emulation mode
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    fixup for bsd hosts. Some headers are included by default which means that
    more variables need TGT_ prefixes and there isn't a stat call (everything
    is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
    this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
    just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
    I much cleaner way to get max int
sim/syscall_emul.hh:
    fix stat64 problems on *BSD

--HG--
extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942
2006-02-10 14:21:32 -05:00
Steve Reinhardt
3923eec0ef Change how memory operands are handled in ISA descriptions.
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used.  I haven't
looked into this in any detail though.

arch/alpha/isa/decoder.isa:
    HwLoadStore format split into separate HwLoad and
    HwStore formats.
    Copy instructions now fall under MiscPrefetch format.
    Mem_write_result is now just write_result in store
    conditionals.
arch/alpha/isa/mem.isa:
    Split MemAccExecute and LoadStoreExecute templates
    into separate templates for loads and stores; now
    that memory operands are handled differently from
    registers, it's impossible to have a single template
    serve both.
    Also unified the handling of "regular" prefetches
    (loads to r31) and "misc" prefetches (e.g., wh64)
    under the new scheme.  It looks like SW prefetches
    were not handled correctly in FullCPU up til now,
    since we generated an execute() method for the outer
    instruction but didn't generate a proper method for
    MemAcc::execute() (instead getting a default no-op
    method for that).
arch/alpha/isa/pal.isa:
    Split HwLoadStore into separate HwLoad and HwStore
    formats to select proper template (see change to
    mem.isa in this changeset).
arch/isa_parser.py:
    Stop trying to treat memory operands like register
    operands, since we never used them in a uniform way
    anyway, and it made it impossible to do split-phase
    loads as needed for the new CPU model.  Now there's no
    more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
    register operands, and the template code is responsible
    for formulating the call to the memory system.  Right now
    the only thing exported by InstObjParams is a new attribute
    'mem_acc_size' which gives the memory access size in bits,
    though more attributes can be added if needed.

    Also moved code in findOperands() method to
    OperandDescriptorList.__init__(), which is where it belongs.

--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
2006-02-10 09:12:55 -05:00
Korey Sewell
2865768112 Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : c78773ba1acb2c6a45f0e92d80fdfc7f23ea6973
2006-02-10 03:31:13 -05:00
Korey Sewell
5cfc5e8080 The first fully coded version of decoder.isa!!!!!
=================================================
-every MIPS32 ISA is represented with some type
of code block.
-any instruction that doesnt have a code block
would be of format WarnUnimpl. Examples of the
ones I am waiting on further info to implement
are the TLB register insts, memory consistency
instructions (ll,sc,etc.) and software debug
insts.

--HG--
extra : convert_revision : 4a26c72e4fa1f63b8689fe2631a7508daf660969
2006-02-10 03:27:19 -05:00
Steve Reinhardt
dd473ecd57 Split Alpha ISA description into multiple files
(thanks to Gabe's include feature!).

arch/alpha/isa/main.isa:
    Split out into multiple .isa files.

--HG--
extra : convert_revision : 30d8edf74ea194d4a208febf1e66edc72a7dbd5d
2006-02-09 23:02:38 -05:00
Steve Reinhardt
fb90b1dd13 Minor cleanup of include-handling code in isa_parser.py.
arch/isa_parser.py:
    Clean up ##include code a bit.
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
    Fix include paths.

--HG--
extra : convert_revision : 0689963c2948e5f1088ecbf2cf6018d29bdaceff
2006-02-09 22:27:41 -05:00
Steve Reinhardt
2c528d5865 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 6e30fb802265c6a0d4afc00141b89ee529595549
2006-02-09 14:58:56 -05:00
Steve Reinhardt
730ee42ab8 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : 10146c85d2fa6f565568cc30a4564b3674e4768d
2006-02-09 14:51:56 -05:00
Steve Reinhardt
879aaa5569 Change how isa_parser.py generates C++ names for isa_desc operands.
arch/isa_parser.py:
    Get rid of "munged name" for operands in C++ code.
    That is, "Ra.uq" will now be known in the C++ as "Ra"
    rather than "Ra_uq".  It wasn't legal to use different
    type extensions for the same operand at the same time
    anyway, and now it will be easier to refer to explicit
    operands in template code if necessary.

--HG--
extra : convert_revision : 9ff41e0201aeefe761743084ecdb34f4b9c84fdb
2006-02-09 14:51:37 -05:00
Gabe Black
7d9b93d825 Changed the filenames to the new standard again
arch/sparc/isa/formats.isa:
    Changed the file extensions to .isa again.
arch/sparc/isa/main.isa:
    Changed the file extensions to .isa again

--HG--
rename : arch/sparc/isa_desc/base.h => arch/sparc/isa/base.isa
rename : arch/sparc/isa_desc/bitfields.h => arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa_desc/decoder.h => arch/sparc/isa/decoder.isa
rename : arch/sparc/isa_desc/formats.h => arch/sparc/isa/formats.isa
rename : arch/sparc/isa_desc/formats/basic.format => arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa_desc/formats/branch.format => arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa_desc/formats/integerop.format => arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa_desc/formats/mem.format => arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa_desc/formats/noop.format => arch/sparc/isa/formats/noop.isa
rename : arch/sparc/isa_desc/formats/trap.format => arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa_desc/includes.h => arch/sparc/isa/includes.isa
rename : arch/sparc/isa_desc/isa_desc => arch/sparc/isa/main.isa
rename : arch/sparc/isa_desc/operands.h => arch/sparc/isa/operands.isa
extra : convert_revision : acb087e81d06ca5d67fe9b402423d7930f6ae798
2006-02-09 13:56:24 -05:00
Korey Sewell
fb10300c4f more code for instructions... Mainly for coprocessor0 and coprocessor1 move instructions
--HG--
extra : convert_revision : 34e017fd0a6f330f2ac17d34af216fc14f09dd42
2006-02-09 04:26:04 -05:00
Korey Sewell
710b894351 Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 2bfc19cfa186776ff94440b01ea51f520f61234f
2006-02-08 16:24:25 -05:00
Korey Sewell
b6d21b7a34 Code for more "BasicOp" instructions ... formats for all instructions in place ... Edits to Branch Format
arch/mips/isa/decoder.isa:
    Code for di,ei,seb,seh,clz,and clo ....

    Every instruction has a format now (of course these are initial formats are still subject to change!)
arch/mips/isa/formats/branch.isa:
    Format Branch in MIPS similar to Alpha Format

--HG--
extra : convert_revision : 2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
2006-02-08 16:24:04 -05:00
Korey Sewell
b203d7bd33 add at least BasicOp Format to most if not all instructions
and file name changes ...

arch/mips/isa/decoder.isa:
    add at least BasicOp Format to most if not all instructions

--HG--
rename : arch/mips/isa/formats/basic.format => arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.format => arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/fp.format => arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.format => arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.format => arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.format => arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.format => arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.format => arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/mips.isa => arch/mips/isa/main.isa
extra : convert_revision : 0b2f3aee13fee3e0e25c0c746af4216c4a596391
2006-02-08 14:50:07 -05:00
Gabe Black
f444a7e799 Moved the alpha isa_desc to conform to the new naming system.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
extra : convert_revision : a3cc14c202ae606db270c2c29847170d90c05216
2006-02-08 02:17:47 -05:00
Gabe Black
e59fdcdd39 Some fixups
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    Replaced the namespace declaration with including arch/alpha/isa_traits.hh

--HG--
extra : convert_revision : 07cb73a9f30f0e165809668f9baff6a3e3f94580
2006-02-08 01:57:47 -05:00
Gabe Black
29bc6c086a Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : c7caf571575fb0e7136770864371300d3f11787e
2006-02-08 01:04:32 -05:00
Gabe Black
82f2ae56ed Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh
SConscript:
    Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
    Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
    Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
    Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
    Added MIPS as a valid architecture
cpu/exec_context.hh:
    Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.

--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
2006-02-08 01:03:55 -05:00
Korey Sewell
7219693f4c Actually we do need a separate class for Integer Ops with Immediates!!!
The extra class is needed because of the necessisty of an immediate member variable.

Also, added some 'very modest' python code to choose between the IntOp and
the IntImmOp based on the instruction name ...

--HG--
extra : convert_revision : f109c12418202a99b40e270360134e8335739836
2006-02-07 19:28:19 -05:00
Korey Sewell
d30262d480 name changes ... minor IntOP format change
arch/mips/isa/formats/int.format:
    Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
    their reg-reg counterparts

--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
2006-02-07 18:36:08 -05:00
Korey Sewell
6d2807ded8 1st full draft switch statement actions for all integer arithmetic operations and the majority of the load & store operations (not all of FP-Ops),
Output,Format, & Template code needs to be adjusted to correctly take these "decoder.h" inputs ...

--HG--
extra : convert_revision : 3dcde1f2f587e2766fd61231a93d34d1d7727356
2006-02-04 18:59:44 -05:00
Korey Sewell
035b443093 mainly added minor support for the basic arithmetic operations (add, mult, shift)
arch/mips/isa/bitfields.def:
    Add comment, move definition up in file
arch/mips/isa/decoder.def:
    add basic arithmetic operations
arch/mips/isa/formats/fp.format:
    change Integer -> FP words
arch/mips/isa/formats/int.format:
    Add derived IntImm class
arch/mips/isa/operands.def:
    change to MIPS sytle operands

--HG--
rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format
rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format
extra : convert_revision : a95da47bc981e56a9898421da4eeb9c442d1dc15
2006-02-03 23:04:06 -05:00
Korey Sewell
1e222c1502 .h -> .def
--HG--
rename : arch/mips/isa/bitfields.h => arch/mips/isa/bitfields.def
rename : arch/mips/isa/decoder.h => arch/mips/isa/decoder.def
rename : arch/mips/isa/formats.h => arch/mips/isa/formats.def
rename : arch/mips/isa/operands.h => arch/mips/isa/operands.def
extra : convert_revision : 45cb5485311d51982ebcaf1c7eec34e8751c31f5
2006-02-03 03:56:57 -05:00
Korey Sewell
de1f3a7b6b Rename: arch/mips/isa/formats/tlb.format -> arch/mips/isa/formats/tlbop.format
--HG--
rename : arch/mips/isa/formats/tlb.format => arch/mips/isa/formats/tlbop.format
extra : convert_revision : 5b1cfba4a5b687c9a271e1a3f67f75e3fa6c2dde
2006-02-03 03:39:08 -05:00
Korey Sewell
f7a75d872b Checkin (Merge?) files ... Added a few new format files
arch/mips/isa/formats/fpop.format:
    Floating Point Formats
arch/mips/isa/formats/tlb.format:
    TLB Ops Format
arch/mips/isa/mips.isa:
    Name change to mips.isa

--HG--
rename : arch/mips/isa_desc/bitfields.h => arch/mips/isa/bitfields.h
rename : arch/mips/isa_desc/decoder.h => arch/mips/isa/decoder.h
rename : arch/mips/isa_desc/formats.h => arch/mips/isa/formats.h
rename : arch/mips/isa_desc/formats/basic.format => arch/mips/isa/formats/basic.format
rename : arch/mips/isa_desc/formats/branch.format => arch/mips/isa/formats/branch.format
rename : arch/mips/isa_desc/formats/integerop.format => arch/mips/isa/formats/integerop.format
rename : arch/mips/isa_desc/formats/mem.format => arch/mips/isa/formats/mem.format
rename : arch/mips/isa_desc/formats/noop.format => arch/mips/isa/formats/noop.format
rename : arch/mips/isa_desc/formats/trap.format => arch/mips/isa/formats/trap.format
rename : arch/mips/isa_desc/includes.h => arch/mips/isa/includes.h
rename : arch/mips/isa_desc/operands.h => arch/mips/isa/operands.h
extra : convert_revision : 069a24da405b613f688e693fd038ac7a30a4faed
2006-02-03 03:38:27 -05:00
Gabe Black
2939a7089a byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    Added the endianness namespace. This may change.
cpu/exec_context.hh:
    Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
    Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
    Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
    Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
    Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
    Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
    Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
    Forced LittleEndianness for lack of a better solution.

--HG--
extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206
2006-02-03 00:16:44 -05:00
Steve Reinhardt
0e79d188e1 Hacks to avoid compiling in old FullCPU model.
Needed in the interim until we port the old model over
to the new interface.  Long term we should have a cleaner
solution for controlling which models get compiled in.

SConscript:
    Move old FullCPU source file list to separate full_cpu_sources
    list so we can choose to not include it in compile.
arch/isa_parser.py:
    Hack to avoid generating FullCPU execute files.
    Need a better way to control this.
cpu/exetrace.cc:
    Don't include old FullCPU-specific headers (apparently
    unnecessary anyway--or if not they should be).

--HG--
extra : convert_revision : 00d5a91a9e4d71507404b8c7f4c6e7c7b7ba3853
2006-01-29 17:35:53 -05:00
Korey Sewell
8b783f8ad2 sparc files that were removed from revision 1.888
--HG--
extra : convert_revision : f285a442b64eee183f7d0f6c203f0b0aa7ea8586
2006-01-29 17:25:54 -05:00
Steve Reinhardt
03a2aca9a9 Changes for Process object initialization in merged-memory environment.
System object now exists for both fullsys and syscall emulation, as the
latter needs it so that Process objects can find the shared PhysicalMemory
for initialization.
Changes are incomplete: still need to fix up Process (& EioProcess) memory
initialization and syscall emulation code for new mem interface.

arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
cpu/base.cc:
cpu/base.hh:
    Take System argument in constructor.
cpu/exec_context.cc:
    Take System argument in constructor.
    Merge two constructors into a single one.
cpu/exec_context.hh:
    Take System argument in constructor.
    Merge two constructors into a single one.
    Replace dummy translation with lookup in Process object's page table.
python/m5/objects/Process.py:
    Add System parameter to Process object (& subobjects).
python/m5/objects/System.py:
    Segregate full-system only Process parameters (most of them!).
sim/process.cc:
    Take System argument in constructor.
    Move initialization to startup() callback to occur after system & cpus
    are initialized.
    Generate ProxyMemory object to pass to loader for transparent
    virtual page allocation.
sim/process.hh:
    Take System argument in constructor.
    Move initialization to startup() callback to occur after system & cpus
    are initialized.
sim/system.cc:
sim/system.hh:
    Enable System object for non-full-system too.
    Basically involved putting most of the existing code
    inside '#ifdef FULL_SYSTEM'.
    Key thing needed for syscall emulation at this point is
    the PhysicalMemory object (for Process initialization).

--HG--
extra : convert_revision : f0f34b47bd4f77b502191affd3d03b4d6d9bcdd8
2006-01-28 00:08:22 -05:00
Korey Sewell
0162c52f17 bitfields definition to support current decoder.h
--HG--
extra : convert_revision : 75ccc53181b857605d051024d86ef62ec43f3b7f
2006-01-26 17:07:01 -05:00
Korey Sewell
2bc106a8e7 "sparc" -> "mips"
arch/mips/isa_desc/formats.h:
arch/mips/isa_desc/formats/basic.format:
arch/mips/isa_desc/formats/branch.format:
arch/mips/isa_desc/formats/integerop.format:
arch/mips/isa_desc/formats/mem.format:
arch/mips/isa_desc/formats/noop.format:
arch/mips/isa_desc/formats/trap.format:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
    changing "sparc" strings to "mips" everywhere

--HG--
extra : convert_revision : eaecf9eeac26e3ef0726deef2fb5d7e9ad172984
2006-01-26 16:19:44 -05:00
Korey Sewell
efc4620de1 decoder skeleton code: this should be able to read any MIPS instruction and decode it but NOT produce any C++ class object.
All of the code literals are empty as of now. As much as possible instructions were organized into relevant "formats"
and also references to the tables I used from the MIPS manual were noted via appropriate comments.

--HG--
extra : convert_revision : 9b44fb40e900061a4cdb290b6a5aaceb9750ae13
2006-01-26 01:34:43 -05:00
Korey Sewell
4be1f418bc more changes to the decoder ... Now does special 3 table
arch/mips/isa_desc/bitfields.h:
    Change from table names to actual bitfield name ...

--HG--
extra : convert_revision : ead69065eb9c3e9c4ea4f67587a6fb07091898ed
2006-01-25 17:36:38 -05:00
Korey Sewell
14fc0996e3 first version of my decoder function skeleton
- this will decode the instructions but not doing anything to create the C++ object yet
(the 1st of many steps!)

arch/mips/isa_desc/bitfields.h:
    initial bitfield constants ... copied some from original alpha bitfields
arch/mips/isa_desc/decoder.h:
    decoder function skeleton pt.1
    - this will decode the instructions but not doing anything to create the C++ object yet
    (the 1st of many steps!)

--HG--
extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
2006-01-25 17:06:23 -05:00
Korey Sewell
90aa2dbfc2 initial changes to decoder.hh and copied files from arch/sparc directory
arch/mips/isa_desc/bitfields.h:
arch/mips/isa_desc/formats.h:
arch/mips/isa_desc/formats/basic.format:
arch/mips/isa_desc/formats/branch.format:
arch/mips/isa_desc/formats/integerop.format:
arch/mips/isa_desc/formats/mem.format:
arch/mips/isa_desc/formats/noop.format:
arch/mips/isa_desc/formats/trap.format:
arch/mips/isa_desc/includes.h:
arch/mips/isa_desc/operands.h:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
    copied from sparc ISA directory
arch/mips/isa_desc/decoder.h:
    decoder I started to work on...

--HG--
rename : arch/sparc/isa_desc/bitfields.h => arch/mips/isa_desc/bitfields.h
rename : arch/sparc/isa_desc/decoder.h => arch/mips/isa_desc/decoder.h
rename : arch/sparc/isa_desc/formats.h => arch/mips/isa_desc/formats.h
rename : arch/sparc/isa_desc/formats/basic.format => arch/mips/isa_desc/formats/basic.format
rename : arch/sparc/isa_desc/formats/branch.format => arch/mips/isa_desc/formats/branch.format
rename : arch/sparc/isa_desc/formats/integerop.format => arch/mips/isa_desc/formats/integerop.format
rename : arch/sparc/isa_desc/formats/mem.format => arch/mips/isa_desc/formats/mem.format
rename : arch/sparc/isa_desc/formats/noop.format => arch/mips/isa_desc/formats/noop.format
rename : arch/sparc/isa_desc/formats/trap.format => arch/mips/isa_desc/formats/trap.format
rename : arch/sparc/isa_desc/includes.h => arch/mips/isa_desc/includes.h
rename : arch/sparc/isa_desc/operands.h => arch/mips/isa_desc/operands.h
rename : arch/sparc/isa_traits.cc => arch/mips/isa_traits.cc
rename : arch/sparc/isa_traits.hh => arch/mips/isa_traits.hh
extra : convert_revision : d4f281960ecf2dce479fb665469c6f2c5dd3063e
2006-01-25 14:43:47 -05:00
Gabe Black
89596f0cfa Some stuff aparently didn't get committed which was from before the new repository was created.
SConscript:
    There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
    The isa parser now supports include directives. These are done with ##include
build/SConstruct:
    The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
    This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
    This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
    Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
    The default options for a sparc syscall emulation build.

--HG--
extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-24 19:57:17 -05:00
Gabe Black
79a4683876 Adding the sparc ISA files which were worked on locally
arch/sparc/isa_desc/bitfields.h:
    This file defines the bit fields used by the isa description system
arch/sparc/isa_desc/decoder.h:
    This file describes the decoder for the isa description system
arch/sparc/isa_desc/formats.h:
    This file declares the instruction formats
arch/sparc/isa_desc/formats/basic.format:
    This file implements the "basic" instruction format
arch/sparc/isa_desc/formats/branch.format:
    This file implements the "branch" instruction format
arch/sparc/isa_desc/formats/integerop.format:
    This file implements the "integerop" instruction format
arch/sparc/isa_desc/formats/mem.format:
    This file implements the "mem" instruction format
arch/sparc/isa_desc/formats/noop.format:
    This file implements the "noop" instruction format
arch/sparc/isa_desc/formats/trap.format:
    This file implements the "trap" instruction format
arch/sparc/isa_desc/includes.h:
    This file is all of the inclues that are used by the isa description system

--HG--
extra : convert_revision : 12a2ffe949317b8b57d83263a4261131b9432c2a
2006-01-10 14:57:37 -05:00
Steve Reinhardt
0cdcb08d90 Change base/intmath.{cc,hh} to follow m5 style.
arch/alpha/alpha_tru64_process.cc:
base/intmath.hh:
base/statistics.cc:
base/str.cc:
cpu/o3/btb.cc:
sim/process.cc:
sim/syscall_emul.hh:
    Rename intmath.hh functions to follow m5 style
    (RoundUp -> roundUp, etc.).
base/intmath.cc:
    Rename intmath.hh functions to follow m5 style
    (RoundUp -> roundUp, etc.).
    Also reindent code in m5 style.

--HG--
extra : convert_revision : 57b853002bc3c9911e122599d9062b41a06d8e6a
2005-12-23 13:32:31 -05:00
Kevin Lim
6da93ea526 Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi). It provides support for more syscalls in syscall emulation mode.
arch/alpha/alpha_linux_process.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).

--HG--
extra : convert_revision : 37fbc78a927110b7798343afd2c5f37a269e42b4
2005-11-22 12:08:08 -05:00
Nathan Binkert
0dcb288365 Cleanup the StackTrace interfaces and profile interfaces so they
are more efficient and reduce the number of new/delete calls

arch/alpha/stacktrace.cc:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
    - switch to using kernelSymtab instead of allSymtab which will be
    going away
    - if the stack adjustment doesn't make any sense, exit and push
    unknown so we don't get into an infinite loop or record garbage.
    - check to see if we've made too many iterations through the stack
    and panic to avoid an infinite loop
arch/alpha/stacktrace.hh:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
cpu/base.cc:
    only clear the profile if we have one
    include profile.hh here since base.hh doesn't do it anymore
cpu/base.hh:
    no need to include cpu/profile.hh here
cpu/profile.cc:
    use ProfileNode pointers instead of objects in the ChildList
    Consume a vector of addresses since that's really all we
    care about.
cpu/profile.hh:
    Keep pointers to ProfileNodes to reduce the size of these structures
    keep a StackTrace around so that we may reuse it.
    provide consume functions that use the new StackTrace trace interface
    one consume function is inline and tries to fastpath the no trace
    condition, it calls the outlined consume function if a trace is generated.
cpu/simple/cpu.cc:
    include cpu/profile.hh here since base.hh no longer does
    use the new FunctionProfile::consume interface
    (which contains the tracing functions)

--HG--
extra : convert_revision : 5a1d9265289a75f67a497b322926be1f8c2d8eb3
2005-11-20 17:44:58 -05:00
Ali Saidi
ccae5838fd add symbol opcode
--HG--
extra : convert_revision : e050d2c4fec33c41ac21b6f17b3be329b9521429
2005-11-19 01:25:34 -05:00
Steve Reinhardt
e701cf48d9 A couple of FP-related fixes (prompted by Adam having trouble
running SPEC FP codes).

arch/alpha/isa_desc:
    Don't warn about non-standard trapping modes more than
    once per static instruction.  (Had the flag to suppress
    these but forgot to check it!)
build/SConstruct:
    Add USE_SSE2 option to enable compiling w/SSE2 (important
    for getting IEEE-compliant FP on x86).

--HG--
extra : convert_revision : eac69efb28cce7b48035480d8b7cb004782969f4
2005-11-09 09:52:07 -05:00
Steve Reinhardt
9a881c5a82 Minor tweak to isa_parser.
arch/isa_parser.py:
    Derive Stack class directly from list.

--HG--
extra : convert_revision : 4f09db4baec0bb2144d71ffad5ce53651e8c3ac6
2005-10-20 14:14:59 -04:00
Nathan Binkert
e999645caf define a couple more abi regiesters
--HG--
extra : convert_revision : 2b909cc784d4fdd4833a70e86d13c207a7c1dd23
2005-10-18 20:02:23 -04:00
Nathan Binkert
a81c03737a Add new function profiling stuff, wrap the pc_sample stuff into it.
SConscript:
    Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
    DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
    Add profiling stuff
kern/kernel_stats.hh:
    Use a smart pointer
sim/system.cc:
sim/system.hh:
    Create a new symbol table that has all of the symbols for a
    particular system
util/stats/categories.py:
    change around the categories, add categories for function
    profiling stuff
util/stats/profile.py:
    No profile parsing and display code to deal with function
    profiling stuff, graph, dot, and text outputs.

--HG--
extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
2005-10-18 19:07:42 -04:00
Steve Reinhardt
310f608757 Clean up indentation in isa_desc.
arch/alpha/isa_desc:
    Little bit of re-ordering and indentation clean-up.

--HG--
extra : convert_revision : e538ff89d8b507c3e1aa68a032578fcaa645d7ee
2005-09-24 18:17:51 -04:00
Steve Reinhardt
11cb904ad7 Explicitly handle rounding on FP-to-integer conversions.
Seems to avoid the significant problems on platforms w/o fenv.h.

arch/alpha/isa_desc:
    Explicitly handle rounding on FP-to-integer conversions.
    Seems to avoid the significant problems on platforms w/o fenv.h.
    Get rid of FP "Fast" vs "General" distinction... more headache than
    it's worth.
arch/isa_parser.py:
    Fix bug with "%s" in C++ templates (must escape properly to
    pass through Python string interpolation).

--HG--
extra : convert_revision : de964d764e67e0934ac0ef535f53c974640731fb
2005-09-11 19:29:41 -04:00
Steve Reinhardt
39ce4fbaf9 Bug fix: can't increment an iterator after you erase
the thing it points to.  Somehow Linux doesn't care,
but Cygwin sure does.

--HG--
extra : convert_revision : 1209a75831f080f17a95433e546d7074f9f07332
2005-09-02 14:38:11 -04:00
Steve Reinhardt
c4793184bd Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.  Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.

SConscript:
    MySQL detection moved to SConstruct.
    Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
    Revamp fenv.h support... most of the ugliness is hidden
    in base/fenv.hh now.
base/mysql.hh:
    Fix typo in #ifndef guard.
build/SConstruct:
    Build options are set via a build_options file in the
    build directory instead of being inferred from the name
    of the build directory.
    Options are passed to C++ via config/*.hh files instead of
    via the command line.
python/SConscript:
    Generate m5_build_env directly from scons options
    instead of indirectly via CPPDEFINES.
python/m5/convert.py:
    Allow '0' and '1' for booleans.
    Rewrite toBool to use dict.
base/fenv.hh:
    Revamp <fenv.h> support to make it a compile option
    (so we can test w/o it even if it's present) and to
    make isa_desc cleaner.

--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-08-30 13:18:54 -04:00
Benjamin Nash
bc76a807af Merge m5read@m5.eecs.umich.edu:/bk/m5
into zed.eecs.umich.edu:/z/benash/bk/m5

--HG--
extra : convert_revision : 453615c8194ae9ca96330b7493c6b19fc89c3a72
2005-06-28 14:03:04 -04:00
Nathan Binkert
036a8ceb8d Don't hard code the location of m5AlphaAccess. Instead, move the
code into a function that can be called by the AlphaConsole class.
AlphaConsole will pass in its address.

arch/alpha/ev5.hh:
    Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable
    bits so that they will be converted correctly.
dev/alpha_access.h:
    Do not hard code the location of the AlphaConsole
dev/alpha_console.cc:
    fixup #includes
    tell the system where the alpha console is
sim/system.hh:
    Provide a function that will tell the system where the AlphaAccess
    structure (device) lives

--HG--
extra : convert_revision : 92d70ca926151a32eebe9925de597459ac58013e
2005-06-28 12:42:15 -04:00
Benjamin Nash
f4e5776df4 I/O changes and SkipFuncEvents to increase FreeBSD compatibility.
SConscript:
    Added kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added Argument to support replacement of calibrate_clocks function in FreeBSD.
dev/ns_gige.hh:
    Fixed NIC model number typo.
dev/tsunami_io.cc:
    Added support for RTC writes and PIC 2 mask reads.  Made RTC static member.
dev/tsunami_io.hh:
    Made RTC static member.
kern/freebsd/freebsd_system.cc:
    Added events to skip functions in FreeBSD.
kern/freebsd/freebsd_system.hh:
    Added events to skip certain functions.

--HG--
extra : convert_revision : 8aaca51d3f9b1bb601722a5bae240aae77b445db
2005-06-17 18:08:05 -04:00
Steve Reinhardt
ad8b9636f8 Many files:
Update copyright dates and author list

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
build/SConstruct:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/memtest/memtest.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunamireg.h:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/linux_threadinfo.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
python/SConscript:
python/m5/__init__.py:
python/m5/config.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/genini.py:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/ccdrv/devtime.c:
util/m5/m5.c:
util/oprofile-top.py:
util/rundiff:
util/m5/m5op.h:
util/m5/m5op.s:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
util/tap/tap.cc:
    Update copyright dates and author list

--HG--
extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 05:16:00 -04:00
Steve Reinhardt
39d8c49479 Fix a few broken or inconsistently formatted copyrights
that the script doesn't deal with.
Don't bother with copyright notices in generated files.

LICENSE:
    Fix author list.
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
    Fix inconsistently formatted copyright.
arch/isa_parser.py:
base/traceflags.py:
    Fix copyright & author list.
    Don't bother with copyrights in generated files.
dev/rtcreg.h:
    Fix broken copyright.

--HG--
extra : convert_revision : d628e63c495960e2b129cef0aa8fddbdd4dabd45
2005-06-05 05:08:37 -04:00
Steve Reinhardt
18115a4d67 Many files:
Remove RCS Id string

arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ecoff_machdep.h:
arch/isa_parser.py:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.cc:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/kgdb.h:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/coff_sym.h:
base/loader/coff_symconst.h:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/exec_aout.h:
base/loader/exec_ecoff.h:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/traceflags.py:
base/userinfo.cc:
base/userinfo.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/o3/2bit_local_pred.cc:
cpu/o3/2bit_local_pred.hh:
cpu/o3/alpha_cpu.cc:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/bpred_unit.cc:
cpu/o3/bpred_unit.hh:
cpu/o3/bpred_unit_impl.hh:
cpu/o3/btb.cc:
cpu/o3/btb.hh:
cpu/o3/comm.hh:
cpu/o3/commit.cc:
cpu/o3/commit.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/cpu_policy.hh:
cpu/o3/decode.cc:
cpu/o3/decode.hh:
cpu/o3/decode_impl.hh:
cpu/o3/fetch.cc:
cpu/o3/fetch.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/free_list.cc:
cpu/o3/free_list.hh:
cpu/o3/iew.cc:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue.cc:
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
cpu/o3/mem_dep_unit.cc:
cpu/o3/mem_dep_unit.hh:
cpu/o3/mem_dep_unit_impl.hh:
cpu/o3/ras.cc:
cpu/o3/ras.hh:
cpu/o3/regfile.hh:
cpu/o3/rename.cc:
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rename_map.cc:
cpu/o3/rename_map.hh:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/o3/store_set.cc:
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.cc:
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/Makefile:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/m5/m5.c:
util/m5/m5op.h:
util/m5/m5op.s:
util/tap/Makefile:
util/tap/tap.cc:
util/term/Makefile:
util/term/term.c:
    Remove RCS Id string

--HG--
extra : convert_revision : fc5b0a6ee2a213785bd58c51ce82eb2f769d6b88
2005-06-05 04:21:22 -04:00
Ali Saidi
5070f27c69 added copyright
kern/linux/sched.hh:
kern/linux/thread_info.hh:
    got rid of everything but exactly what we needed
util/categories.py:
    newest version from one of my repositories

--HG--
extra : convert_revision : c4328e5938d421d60493c0da07022bfa9e92c404
2005-06-05 04:08:05 -04:00
Steve Reinhardt
550003e1b7 Change SamplingCPU to Sampler.
--HG--
extra : convert_revision : ddba327a572804954adcebfff1182b97d474c020
2005-06-05 02:59:43 -04:00
Nathan Binkert
13c005a8af shuffle files around for new directory structure
--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-04 20:50:10 -04:00