Cleaned up and slightly reorganized the Fault class heirarchy.

arch/alpha/ev5.cc:
    Changed c style casts of Faults to dynamic_casts
arch/alpha/faults.cc:
    AlphaFault is now an abstract class.
arch/alpha/faults.hh:
    AlphaFault is now an abstract class. Also, AlphaMachineCheckFault and AlphaAlignmentFault multiply inherit from both AlphaFault and from MachineCheckFault and AlignmentFault respectively. These classes get their name from the generic classes.
cpu/o3/alpha_cpu_impl.hh:
    Changed a c style cast to a dynamic_cast for a Fault
sim/faults.hh:
    All generic Fault classes are now abstract. Also, MachineCheckFault and AlignmentFault inherit FaultBase as a virtual base class to help resolve ambiguities when they are multiply inherited in ISA specific classes. The override the isMachineCheckFault and isAlignmentFault functions appropriately, and provide a standard name for these faults.

--HG--
extra : convert_revision : 2cb906708e3eaec4a12587484c09e50ed6ef88fc
This commit is contained in:
Gabe Black 2006-02-28 06:02:18 -05:00
parent 6165419d35
commit 299efffaf5
5 changed files with 16 additions and 23 deletions

View file

@ -192,7 +192,8 @@ ExecContext::ev5_temp_trap(Fault fault)
if (!inPalMode())
AlphaISA::swap_palshadow(&regs, true);
regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + ((AlphaFault *)(fault.get()))->vect();
regs.pc = ipr[AlphaISA::IPR_PAL_BASE] +
(dynamic_cast<AlphaFault *>(fault.get()))->vect();
regs.npc = regs.pc + sizeof(MachInst);
}
@ -217,7 +218,8 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
// jump to expection address (PAL PC bit set here as well...)
if (!use_pc)
regs->npc = ipr[IPR_PAL_BASE] + ((AlphaFault *)(fault.get()))->vect();
regs->npc = ipr[IPR_PAL_BASE] +
(dynamic_cast<AlphaFault *>(fault.get()))->vect();
else
regs->npc = ipr[IPR_PAL_BASE] + pc;

View file

@ -32,10 +32,6 @@
namespace AlphaISA
{
FaultName AlphaFault::_name = "alphafault";
FaultVect AlphaFault::_vect = 0x0000;
FaultStat AlphaFault::_stat;
FaultVect AlphaMachineCheckFault::_vect = 0x0401;
FaultStat AlphaMachineCheckFault::_stat;

View file

@ -38,22 +38,18 @@ namespace AlphaISA
typedef const Addr FaultVect;
class AlphaFault : public FaultBase
class AlphaFault : public virtual FaultBase
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _stat;
public:
#if FULL_SYSTEM
void ev5_trap(ExecContext * xc);
#endif
FaultName name() {return _name;}
virtual FaultVect vect() {return _vect;}
virtual FaultStat & stat() {return _stat;}
virtual FaultVect vect() = 0;
};
class AlphaMachineCheckFault : public MachineCheckFault
class AlphaMachineCheckFault :
public MachineCheckFault,
public AlphaFault
{
private:
static FaultVect _vect;
@ -66,7 +62,9 @@ class AlphaMachineCheckFault : public MachineCheckFault
FaultStat & stat() {return _stat;}
};
class AlphaAlignmentFault : public AlignmentFault
class AlphaAlignmentFault :
public AlignmentFault,
public AlphaFault
{
private:
static FaultVect _vect;

View file

@ -353,7 +353,7 @@ AlphaFullCPU<Impl>::trap(Fault fault)
swapPALShadow(true);
this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
((AlphaFault *)(fault.get()))->vect());
(dynamic_cast<AlphaFault *>(fault.get()))->vect());
this->regFile.setNextPC(PC + sizeof(MachInst));
}

View file

@ -50,10 +50,7 @@ typedef Stats::Scalar<> FaultStat;
class FaultBase : public RefCounted
{
public:
virtual FaultName name()
{
return "none";
}
virtual FaultName name() = 0;
virtual FaultStat & stat() = 0;
#if FULL_SYSTEM
virtual void ev5_trap(ExecContext * xc) = 0;
@ -72,7 +69,7 @@ FaultBase * const NoFault = 0;
//provide the name() function, and the isMachineCheckFault and isAlignmentFault
//functions are provided below.
class MachineCheckFault : public FaultBase
class MachineCheckFault : public virtual FaultBase
{
private:
static FaultName _name;
@ -81,7 +78,7 @@ class MachineCheckFault : public FaultBase
bool isMachineCheckFault() {return true;}
};
class AlignmentFault : public FaultBase
class AlignmentFault : public virtual FaultBase
{
private:
static FaultName _name;