Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
This commit is contained in:
parent
51647e7bec
commit
70b35bab57
24 changed files with 273 additions and 642 deletions
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@ -293,12 +293,11 @@ AlphaITB::regStats()
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void
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AlphaITB::fault(Addr pc, ExecContext *xc) const
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{
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uint64_t *ipr = xc->regs.ipr;
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if (!xc->misspeculating()) {
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ipr[AlphaISA::IPR_ITB_TAG] = pc;
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ipr[AlphaISA::IPR_IFAULT_VA_FORM] =
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ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3);
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xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
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xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
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xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
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(AlphaISA::VAddr(pc).vpn() << 3));
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}
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}
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@ -306,7 +305,7 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const
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Fault
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AlphaITB::translate(MemReqPtr &req) const
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{
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InternalProcReg *ipr = req->xc->regs.ipr;
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ExecContext *xc = req->xc;
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if (AlphaISA::PcPAL(req->vaddr)) {
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// strip off PAL PC marker (lsb is 1)
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@ -329,13 +328,13 @@ AlphaITB::translate(MemReqPtr &req) const
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
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// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
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#if ALPHA_TLASER
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if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
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if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
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VAddrSpaceEV5(req->vaddr) == 2) {
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#else
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if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
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#endif
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// only valid in kernel mode
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if (ICM_CM(ipr[AlphaISA::IPR_ICM]) !=
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if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
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AlphaISA::mode_kernel) {
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fault(req->vaddr, req->xc);
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acv++;
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@ -354,8 +353,9 @@ AlphaITB::translate(MemReqPtr &req) const
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} else {
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// not a physical address: need to look up pte
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int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
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AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
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DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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asn);
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if (!pte) {
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fault(req->vaddr, req->xc);
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@ -367,7 +367,8 @@ AlphaITB::translate(MemReqPtr &req) const
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(AlphaISA::VAddr(req->vaddr).offset() & ~3);
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// check permissions for this access
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if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) {
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if (!(pte->xre &
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(1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
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// instruction access fault
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fault(req->vaddr, req->xc);
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acv++;
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@ -469,7 +470,6 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
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{
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ExecContext *xc = req->xc;
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AlphaISA::VAddr vaddr = req->vaddr;
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uint64_t *ipr = xc->regs.ipr;
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// Set fault address and flags. Even though we're modeling an
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// EV5, we use the EV6 technique of not latching fault registers
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@ -479,17 +479,17 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
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if (!xc->misspeculating()
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&& !(req->flags & VPTE) && !(req->flags & NO_FAULT)) {
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// set VA register with faulting address
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ipr[AlphaISA::IPR_VA] = req->vaddr;
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xc->setMiscReg(AlphaISA::IPR_VA, req->vaddr);
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// set MM_STAT register flags
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ipr[AlphaISA::IPR_MM_STAT] =
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xc->setMiscReg(AlphaISA::IPR_MM_STAT,
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(((Opcode(xc->getInst()) & 0x3f) << 11)
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| ((Ra(xc->getInst()) & 0x1f) << 6)
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| (flags & 0x3f));
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| (flags & 0x3f)));
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// set VA_FORM register with faulting formatted address
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ipr[AlphaISA::IPR_VA_FORM] =
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ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3);
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xc->setMiscReg(AlphaISA::IPR_VA_FORM,
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xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
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}
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}
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@ -497,11 +497,11 @@ Fault
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AlphaDTB::translate(MemReqPtr &req, bool write) const
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{
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RegFile *regs = &req->xc->regs;
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ExecContext *xc = req->xc;
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Addr pc = regs->pc;
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InternalProcReg *ipr = regs->ipr;
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AlphaISA::mode_type mode =
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(AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]);
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(AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
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/**
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if (pc & 0x1) {
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mode = (req->flags & ALTMODE) ?
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(AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE])
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(AlphaISA::mode_type)ALT_MODE_AM(
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xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
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: AlphaISA::mode_kernel;
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}
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@ -535,14 +536,14 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
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// Check for "superpage" mapping
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#if ALPHA_TLASER
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if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
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if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
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VAddrSpaceEV5(req->vaddr) == 2) {
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#else
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if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
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#endif
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// only valid in kernel mode
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if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
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if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
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AlphaISA::mode_kernel) {
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fault(req, ((write ? MM_STAT_WR_MASK : 0) |
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MM_STAT_ACV_MASK));
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else
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read_accesses++;
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int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
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// not a physical address: need to look up pte
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AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
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DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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asn);
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if (!pte) {
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// page fault
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@ -72,14 +72,14 @@ AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
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void
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AlphaISA::initCPU(RegFile *regs, int cpuId)
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{
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initIPRs(regs, cpuId);
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initIPRs(®s->miscRegs, cpuId);
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// CPU comes up with PAL regs enabled
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swap_palshadow(regs, true);
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regs->intRegFile[16] = cpuId;
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regs->intRegFile[0] = cpuId;
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regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
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regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + fault_addr(ResetFault);
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regs->npc = regs->pc + sizeof(MachInst);
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}
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//
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//
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void
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AlphaISA::initIPRs(RegFile *regs, int cpuId)
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AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId)
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{
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uint64_t *ipr = regs->ipr;
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miscRegs->clearIprs();
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bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
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ipr[IPR_PAL_BASE] = PalBase;
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ipr[IPR_MCSR] = 0x6;
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ipr[IPR_PALtemp16] = cpuId;
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miscRegs->setReg(IPR_PAL_BASE, PalBase);
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miscRegs->setReg(IPR_MCSR, 0x6);
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miscRegs->setReg(IPR_PALtemp16, cpuId);
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}
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//Handle the interrupts
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int ipl = 0;
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int summary = 0;
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IntReg *ipr = cpu->getIprPtr();
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cpu->checkInterrupts = false;
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if (ipr[IPR_ASTRR])
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if (cpu->readMiscReg(IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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if (ipr[IPR_SIRR]) {
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if (cpu->readMiscReg(IPR_SIRR)) {
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for (int i = INTLEVEL_SOFTWARE_MIN;
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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if (ipr[IPR_SIRR] & (ULL(1) << i)) {
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if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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if (ipl && ipl > ipr[IPR_IPLR]) {
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ipr[IPR_ISR] = summary;
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ipr[IPR_INTID] = ipl;
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if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
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cpu->setMiscReg(IPR_ISR, summary);
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cpu->setMiscReg(IPR_INTID, ipl);
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cpu->trap(InterruptFault);
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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ipr[IPR_IPLR], ipl, summary);
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cpu->readMiscReg(IPR_IPLR), ipl, summary);
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}
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}
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if (fault == ArithmeticFault)
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panic("Arithmetic traps are unimplemented!");
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AlphaISA::InternalProcReg *ipr = regs.ipr;
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// exception restart address
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if (fault != InterruptFault || !inPalMode())
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ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
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setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
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if (fault == PalFault || fault == ArithmeticFault /* ||
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fault == InterruptFault && !inPalMode() */) {
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// traps... skip faulting instruction
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ipr[AlphaISA::IPR_EXC_ADDR] += 4;
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setMiscReg(AlphaISA::IPR_EXC_ADDR,
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readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
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}
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if (!inPalMode())
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AlphaISA::swap_palshadow(®s, true);
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regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
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regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) + AlphaISA::fault_addr(fault);
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regs.npc = regs.pc + sizeof(MachInst);
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}
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void
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AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
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{
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InternalProcReg *ipr = regs->ipr;
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bool use_pc = (fault == NoFault);
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if (fault == ArithmeticFault)
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// compute exception restart address
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if (use_pc || fault == PalFault || fault == ArithmeticFault) {
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// traps... skip faulting instruction
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ipr[IPR_EXC_ADDR] = regs->pc + 4;
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regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
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} else {
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// fault, post fault at excepting instruction
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ipr[IPR_EXC_ADDR] = regs->pc;
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regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
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}
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// jump to expection address (PAL PC bit set here as well...)
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if (!use_pc)
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regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
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regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
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fault_addr(fault);
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else
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regs->npc = ipr[IPR_PAL_BASE] + pc;
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regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
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// that's it! (orders of magnitude less painful than x86)
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}
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@ -242,17 +239,15 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
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Fault
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ExecContext::hwrei()
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{
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uint64_t *ipr = regs.ipr;
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if (!inPalMode())
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return UnimplementedOpcodeFault;
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setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
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setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
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if (!misspeculating()) {
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kernelStats->hwrei();
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if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
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if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
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AlphaISA::swap_palshadow(®s, false);
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cpu->checkInterrupts = true;
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@ -262,10 +257,15 @@ ExecContext::hwrei()
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return NoFault;
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}
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uint64_t
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ExecContext::readIpr(int idx, Fault &fault)
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void
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AlphaISA::MiscRegFile::clearIprs()
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{
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bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
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}
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AlphaISA::MiscReg
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AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
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{
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uint64_t *ipr = regs.ipr;
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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@ -318,7 +318,7 @@ ExecContext::readIpr(int idx, Fault &fault)
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case AlphaISA::IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= cpu->curCycle() & ULL(0x00000000ffffffff);
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retval |= xc->cpu->curCycle() & ULL(0x00000000ffffffff);
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break;
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case AlphaISA::IPR_VA:
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@ -335,7 +335,7 @@ ExecContext::readIpr(int idx, Fault &fault)
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case AlphaISA::IPR_DTB_PTE:
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{
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AlphaISA::PTE &pte = dtb->index(!misspeculating());
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AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating());
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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@ -375,12 +375,11 @@ int break_ipl = -1;
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#endif
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Fault
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ExecContext::setIpr(int idx, uint64_t val)
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AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
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{
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uint64_t *ipr = regs.ipr;
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uint64_t old;
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if (misspeculating())
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if (xc->misspeculating())
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return NoFault;
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switch (idx) {
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@ -433,7 +432,7 @@ ExecContext::setIpr(int idx, uint64_t val)
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// write entire quad w/ no side-effect
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old = ipr[idx];
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ipr[idx] = val;
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kernelStats->context(old, val);
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xc->kernelStats->context(old, val);
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||||
break;
|
||||
|
||||
case AlphaISA::IPR_DTB_PTE:
|
||||
|
@ -460,14 +459,14 @@ ExecContext::setIpr(int idx, uint64_t val)
|
|||
|
||||
// only write least significant five bits - interrupt level
|
||||
ipr[idx] = val & 0x1f;
|
||||
kernelStats->swpipl(ipr[idx]);
|
||||
xc->kernelStats->swpipl(ipr[idx]);
|
||||
break;
|
||||
|
||||
case AlphaISA::IPR_DTB_CM:
|
||||
if (val & 0x18)
|
||||
kernelStats->mode(Kernel::user);
|
||||
xc->kernelStats->mode(Kernel::user);
|
||||
else
|
||||
kernelStats->mode(Kernel::kernel);
|
||||
xc->kernelStats->mode(Kernel::kernel);
|
||||
|
||||
case AlphaISA::IPR_ICM:
|
||||
// only write two mode bits - processor mode
|
||||
|
@ -541,21 +540,21 @@ ExecContext::setIpr(int idx, uint64_t val)
|
|||
// really a control write
|
||||
ipr[idx] = 0;
|
||||
|
||||
dtb->flushAll();
|
||||
xc->dtb->flushAll();
|
||||
break;
|
||||
|
||||
case AlphaISA::IPR_DTB_IAP:
|
||||
// really a control write
|
||||
ipr[idx] = 0;
|
||||
|
||||
dtb->flushProcesses();
|
||||
xc->dtb->flushProcesses();
|
||||
break;
|
||||
|
||||
case AlphaISA::IPR_DTB_IS:
|
||||
// really a control write
|
||||
ipr[idx] = val;
|
||||
|
||||
dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
||||
xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
||||
break;
|
||||
|
||||
case AlphaISA::IPR_DTB_TAG: {
|
||||
|
@ -578,7 +577,7 @@ ExecContext::setIpr(int idx, uint64_t val)
|
|||
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
|
||||
|
||||
// insert new TAG/PTE value into data TLB
|
||||
dtb->insert(val, pte);
|
||||
xc->dtb->insert(val, pte);
|
||||
}
|
||||
break;
|
||||
|
||||
|
@ -602,7 +601,7 @@ ExecContext::setIpr(int idx, uint64_t val)
|
|||
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
|
||||
|
||||
// insert new TAG/PTE value into data TLB
|
||||
itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
|
||||
xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
|
||||
}
|
||||
break;
|
||||
|
||||
|
@ -610,21 +609,21 @@ ExecContext::setIpr(int idx, uint64_t val)
|
|||
// really a control write
|
||||
ipr[idx] = 0;
|
||||
|
||||
itb->flushAll();
|
||||
xc->itb->flushAll();
|
||||
break;
|
||||
|
||||
case AlphaISA::IPR_ITB_IAP:
|
||||
// really a control write
|
||||
ipr[idx] = 0;
|
||||
|
||||
itb->flushProcesses();
|
||||
xc->itb->flushProcesses();
|
||||
break;
|
||||
|
||||
case AlphaISA::IPR_ITB_IS:
|
||||
// really a control write
|
||||
ipr[idx] = val;
|
||||
|
||||
itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
||||
xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
@ -618,7 +618,7 @@ decode OPCODE default Unknown::unknown() {
|
|||
/* Rb is a fake dependency so here is a fun way to get
|
||||
* the parser to understand that.
|
||||
*/
|
||||
Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
|
||||
Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
|
||||
|
||||
#else
|
||||
Ra = curTick;
|
||||
|
@ -670,7 +670,7 @@ decode OPCODE default Unknown::unknown() {
|
|||
0x00: CallPal::call_pal({{
|
||||
if (!palValid ||
|
||||
(palPriv
|
||||
&& xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
|
||||
&& xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
|
||||
// invalid pal function code, or attempt to do privileged
|
||||
// PAL call in non-kernel mode
|
||||
fault = UnimplementedOpcodeFault;
|
||||
|
@ -682,8 +682,8 @@ decode OPCODE default Unknown::unknown() {
|
|||
|
||||
if (dopal) {
|
||||
AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
|
||||
xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
|
||||
NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
|
||||
xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
|
||||
NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
|
||||
}
|
||||
}
|
||||
}}, IsNonSpeculative);
|
||||
|
@ -732,7 +732,7 @@ decode OPCODE default Unknown::unknown() {
|
|||
fault = UnimplementedOpcodeFault;
|
||||
}
|
||||
else {
|
||||
Ra = xc->readIpr(ipr_index, fault);
|
||||
Ra = xc->readMiscRegWithEffect(ipr_index, fault);
|
||||
}
|
||||
}});
|
||||
0x1d: hw_mtpr({{
|
||||
|
@ -741,7 +741,7 @@ decode OPCODE default Unknown::unknown() {
|
|||
fault = UnimplementedOpcodeFault;
|
||||
}
|
||||
else {
|
||||
xc->setIpr(ipr_index, Ra);
|
||||
xc->setMiscRegWithEffect(ipr_index, Ra);
|
||||
if (traceData) { traceData->setData(Ra); }
|
||||
}
|
||||
}});
|
||||
|
|
|
@ -35,7 +35,7 @@ output exec {{
|
|||
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
|
||||
{
|
||||
Fault fault = NoFault; // dummy... this ipr access should not fault
|
||||
if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
|
||||
if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) {
|
||||
fault = FloatEnableFault;
|
||||
}
|
||||
return fault;
|
||||
|
@ -217,7 +217,8 @@ def template FloatingPointExecute {{
|
|||
if (roundingMode == Normal) {
|
||||
%(code)s;
|
||||
} else {
|
||||
fesetround(getC99RoundingMode(xc->readFpcr()));
|
||||
fesetround(getC99RoundingMode(
|
||||
xc->readMiscReg(AlphaISA::Fpcr_DepTag)));
|
||||
%(code)s;
|
||||
fesetround(FE_TONEAREST);
|
||||
}
|
||||
|
|
|
@ -161,8 +161,8 @@ def operands {{
|
|||
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
|
||||
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
||||
'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
|
||||
'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
|
||||
'FPCR': (' ControlReg', 'uq', 'Fpcr', None, 1),
|
||||
'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
|
||||
'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
|
||||
# The next two are hacks for non-full-system call-pal emulation
|
||||
'R0': ('IntReg', 'uq', '0', None, 1),
|
||||
'R16': ('IntReg', 'uq', '16', None, 1),
|
||||
|
@ -194,6 +194,8 @@ output header {{
|
|||
FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
|
||||
Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
|
||||
Uniq_DepTag = AlphaISA::Uniq_DepTag,
|
||||
Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
|
||||
Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
|
||||
IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
|
||||
};
|
||||
|
||||
|
|
|
@ -38,6 +38,7 @@ using namespace LittleEndianGuest;
|
|||
#include "sim/host.hh"
|
||||
#include "sim/faults.hh"
|
||||
|
||||
class ExecContext;
|
||||
class FastCPU;
|
||||
class FullCPU;
|
||||
class Checkpoint;
|
||||
|
@ -64,6 +65,7 @@ namespace AlphaISA
|
|||
|
||||
NumIntRegs = 32,
|
||||
NumFloatRegs = 32,
|
||||
// @todo: Figure out what this number really should be.
|
||||
NumMiscRegs = 32,
|
||||
|
||||
MaxRegsOfAnyType = 32,
|
||||
|
@ -106,7 +108,9 @@ namespace AlphaISA
|
|||
Ctrl_Base_DepTag = 64,
|
||||
Fpcr_DepTag = 64, // floating point control register
|
||||
Uniq_DepTag = 65,
|
||||
IPR_Base_DepTag = 66
|
||||
Lock_Flag_DepTag = 66,
|
||||
Lock_Addr_DepTag = 67,
|
||||
IPR_Base_DepTag = 68
|
||||
};
|
||||
|
||||
typedef uint64_t IntReg;
|
||||
|
@ -123,15 +127,6 @@ namespace AlphaISA
|
|||
double d[NumFloatRegs]; // double-precision floating point view
|
||||
} FloatRegFile;
|
||||
|
||||
// control register file contents
|
||||
typedef uint64_t MiscReg;
|
||||
typedef struct {
|
||||
uint64_t fpcr; // floating point condition codes
|
||||
uint64_t uniq; // process-unique register
|
||||
bool lock_flag; // lock flag for LL/SC
|
||||
Addr lock_addr; // lock address for LL/SC
|
||||
} MiscRegFile;
|
||||
|
||||
extern const Addr PageShift;
|
||||
extern const Addr PageBytes;
|
||||
extern const Addr PageMask;
|
||||
|
@ -149,6 +144,39 @@ extern const Addr PageOffset;
|
|||
};
|
||||
#endif
|
||||
|
||||
// control register file contents
|
||||
typedef uint64_t MiscReg;
|
||||
class MiscRegFile {
|
||||
protected:
|
||||
uint64_t fpcr; // floating point condition codes
|
||||
uint64_t uniq; // process-unique register
|
||||
bool lock_flag; // lock flag for LL/SC
|
||||
Addr lock_addr; // lock address for LL/SC
|
||||
|
||||
public:
|
||||
MiscReg readReg(int misc_reg);
|
||||
|
||||
MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
|
||||
|
||||
Fault setReg(int misc_reg, const MiscReg &val);
|
||||
|
||||
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
|
||||
ExecContext *xc);
|
||||
|
||||
#if FULL_SYSTEM
|
||||
void clearIprs();
|
||||
|
||||
protected:
|
||||
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
|
||||
|
||||
private:
|
||||
MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
|
||||
|
||||
Fault setIpr(int idx, uint64_t val, ExecContext *xc);
|
||||
#endif
|
||||
friend class RegFile;
|
||||
};
|
||||
|
||||
enum {
|
||||
TotalNumRegs =
|
||||
NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
|
||||
|
@ -172,11 +200,12 @@ extern const Addr PageOffset;
|
|||
Addr npc; // next-cycle program counter
|
||||
#if FULL_SYSTEM
|
||||
IntReg palregs[NumIntRegs]; // PAL shadow registers
|
||||
InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
|
||||
int intrflag; // interrupt flag
|
||||
bool pal_shadow; // using pal_shadow registers
|
||||
inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
|
||||
inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
|
||||
inline int instAsid()
|
||||
{ return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
|
||||
inline int dataAsid()
|
||||
{ return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
void serialize(std::ostream &os);
|
||||
|
|
|
@ -124,7 +124,7 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
|
|||
{
|
||||
xc = _xc;
|
||||
|
||||
bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0;
|
||||
bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
|
||||
|
||||
Addr pc = xc->regs.npc;
|
||||
bool kernel = xc->system->kernelStart <= pc && pc <= xc->system->kernelEnd;
|
||||
|
@ -196,22 +196,22 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
|
|||
bool
|
||||
StackTrace::isEntry(Addr addr)
|
||||
{
|
||||
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp12])
|
||||
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp12))
|
||||
return true;
|
||||
|
||||
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp7])
|
||||
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp7))
|
||||
return true;
|
||||
|
||||
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp11])
|
||||
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp11))
|
||||
return true;
|
||||
|
||||
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp21])
|
||||
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp21))
|
||||
return true;
|
||||
|
||||
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp9])
|
||||
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp9))
|
||||
return true;
|
||||
|
||||
if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp2])
|
||||
if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp2))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
|
|
|
@ -82,7 +82,7 @@ Addr
|
|||
vtophys(ExecContext *xc, Addr addr)
|
||||
{
|
||||
AlphaISA::VAddr vaddr = addr;
|
||||
Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
|
||||
Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
|
||||
Addr paddr = 0;
|
||||
//@todo Andrew couldn't remember why he commented some of this code
|
||||
//so I put it back in. Perhaps something to do with gdb debugging?
|
||||
|
|
|
@ -1263,10 +1263,10 @@ class ControlRegOperand(Operand):
|
|||
def makeConstructor(self):
|
||||
c = ''
|
||||
if self.is_src:
|
||||
c += '\n\t_srcRegIdx[%d] = %s_DepTag;' % \
|
||||
c += '\n\t_srcRegIdx[%d] = %s;' % \
|
||||
(self.src_reg_idx, self.reg_spec)
|
||||
if self.is_dest:
|
||||
c += '\n\t_destRegIdx[%d] = %s_DepTag;' % \
|
||||
c += '\n\t_destRegIdx[%d] = %s;' % \
|
||||
(self.dest_reg_idx, self.reg_spec)
|
||||
return c
|
||||
|
||||
|
@ -1274,7 +1274,7 @@ class ControlRegOperand(Operand):
|
|||
bit_select = 0
|
||||
if (self.ctype == 'float' or self.ctype == 'double'):
|
||||
error(0, 'Attempt to read control register as FP')
|
||||
base = 'xc->read%s()' % self.reg_spec
|
||||
base = 'xc->readMiscReg(%s)' % self.reg_spec
|
||||
if self.size == self.dflt_size:
|
||||
return '%s = %s;\n' % (self.base_name, base)
|
||||
else:
|
||||
|
@ -1284,7 +1284,7 @@ class ControlRegOperand(Operand):
|
|||
def makeWrite(self):
|
||||
if (self.ctype == 'float' or self.ctype == 'double'):
|
||||
error(0, 'Attempt to write control register as FP')
|
||||
wb = 'xc->set%s(%s);\n' % (self.reg_spec, self.base_name)
|
||||
wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name)
|
||||
wb += 'if (traceData) { traceData->setData(%s); }' % \
|
||||
self.base_name
|
||||
return wb
|
||||
|
|
|
@ -371,7 +371,7 @@ RemoteGDB::acc(Addr va, size_t len)
|
|||
if (AlphaISA::PcPAL(va) || va < 0x10000)
|
||||
return true;
|
||||
|
||||
Addr ptbr = context->regs.ipr[AlphaISA::IPR_PALtemp20];
|
||||
Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20);
|
||||
TheISA::PageTableEntry pte = kernel_pte_lookup(pmem, ptbr, va);
|
||||
if (!pte.valid()) {
|
||||
DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
|
||||
|
|
|
@ -71,6 +71,7 @@ class ExecContext
|
|||
typedef TheISA::RegFile RegFile;
|
||||
typedef TheISA::MachInst MachInst;
|
||||
typedef TheISA::MiscRegFile MiscRegFile;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
public:
|
||||
enum Status
|
||||
{
|
||||
|
@ -270,8 +271,8 @@ class ExecContext
|
|||
#if FULL_SYSTEM && defined(TARGET_ALPHA)
|
||||
if (req->flags & LOCKED) {
|
||||
MiscRegFile *cregs = &req->xc->regs.miscRegs;
|
||||
cregs->lock_addr = req->paddr;
|
||||
cregs->lock_flag = true;
|
||||
cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr);
|
||||
cregs->setReg(TheISA::Lock_Flag_DepTag, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -297,10 +298,12 @@ class ExecContext
|
|||
req->result = 2;
|
||||
req->xc->storeCondFailures = 0;//Needed? [RGD]
|
||||
} else {
|
||||
req->result = cregs->lock_flag;
|
||||
if (!cregs->lock_flag ||
|
||||
((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
|
||||
cregs->lock_flag = false;
|
||||
bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag);
|
||||
Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag);
|
||||
req->result = lock_flag;
|
||||
if (!lock_flag ||
|
||||
((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
|
||||
cregs->setReg(TheISA::Lock_Flag_DepTag, false);
|
||||
if (((++req->xc->storeCondFailures) % 100000) == 0) {
|
||||
std::cerr << "Warning: "
|
||||
<< req->xc->storeCondFailures
|
||||
|
@ -321,8 +324,9 @@ class ExecContext
|
|||
// through.
|
||||
for (int i = 0; i < system->execContexts.size(); i++){
|
||||
cregs = &system->execContexts[i]->regs.miscRegs;
|
||||
if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
|
||||
cregs->lock_flag = false;
|
||||
if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
|
||||
(req->paddr & ~0xf)) {
|
||||
cregs->setReg(TheISA::Lock_Flag_DepTag, false);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -398,29 +402,27 @@ class ExecContext
|
|||
regs.npc = val;
|
||||
}
|
||||
|
||||
uint64_t readUniq()
|
||||
MiscReg readMiscReg(int misc_reg)
|
||||
{
|
||||
return regs.miscRegs.uniq;
|
||||
return regs.miscRegs.readReg(misc_reg);
|
||||
}
|
||||
|
||||
void setUniq(uint64_t val)
|
||||
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
|
||||
{
|
||||
regs.miscRegs.uniq = val;
|
||||
return regs.miscRegs.readRegWithEffect(misc_reg, fault, this);
|
||||
}
|
||||
|
||||
uint64_t readFpcr()
|
||||
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
||||
{
|
||||
return regs.miscRegs.fpcr;
|
||||
return regs.miscRegs.setReg(misc_reg, val);
|
||||
}
|
||||
|
||||
void setFpcr(uint64_t val)
|
||||
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
||||
{
|
||||
regs.miscRegs.fpcr = val;
|
||||
return regs.miscRegs.setRegWithEffect(misc_reg, val, this);
|
||||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
uint64_t readIpr(int idx, Fault &fault);
|
||||
Fault setIpr(int idx, uint64_t val);
|
||||
int readIntrFlag() { return regs.intrflag; }
|
||||
void setIntrFlag(int val) { regs.intrflag = val; }
|
||||
Fault hwrei();
|
||||
|
|
|
@ -41,6 +41,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
|
|||
{
|
||||
protected:
|
||||
typedef TheISA::IntReg IntReg;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
|
||||
public:
|
||||
typedef typename Impl::Params Params;
|
||||
|
||||
|
@ -111,33 +113,24 @@ class AlphaFullCPU : public FullO3CPU<Impl>
|
|||
// Later on may want to remove this misc stuff from the regfile and
|
||||
// have it handled at this level. Might prove to be an issue when
|
||||
// trying to rename source/destination registers...
|
||||
uint64_t readUniq()
|
||||
MiscReg readMiscReg(int misc_reg)
|
||||
{
|
||||
return this->regFile.readUniq();
|
||||
// Dummy function for now.
|
||||
// @todo: Fix this once reg file gets fixed.
|
||||
return 0;
|
||||
}
|
||||
|
||||
void setUniq(uint64_t val)
|
||||
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
||||
{
|
||||
this->regFile.setUniq(val);
|
||||
}
|
||||
|
||||
uint64_t readFpcr()
|
||||
{
|
||||
return this->regFile.readFpcr();
|
||||
}
|
||||
|
||||
void setFpcr(uint64_t val)
|
||||
{
|
||||
this->regFile.setFpcr(val);
|
||||
// Dummy function for now.
|
||||
// @todo: Fix this once reg file gets fixed.
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
// Most of the full system code and syscall emulation is not yet
|
||||
// implemented. These functions do show what the final interface will
|
||||
// look like.
|
||||
#if FULL_SYSTEM
|
||||
uint64_t *getIpr();
|
||||
uint64_t readIpr(int idx, Fault &fault);
|
||||
Fault setIpr(int idx, uint64_t val);
|
||||
int readIntrFlag();
|
||||
void setIntrFlag(int val);
|
||||
Fault hwrei();
|
||||
|
@ -216,8 +209,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
|
|||
#if FULL_SYSTEM && defined(TARGET_ALPHA)
|
||||
if (req->flags & LOCKED) {
|
||||
MiscRegFile *cregs = &req->xc->regs.miscRegs;
|
||||
cregs->lock_addr = req->paddr;
|
||||
cregs->lock_flag = true;
|
||||
cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr);
|
||||
cregs->setReg(TheISA::Lock_Flag_DepTag, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -242,22 +235,24 @@ class AlphaFullCPU : public FullO3CPU<Impl>
|
|||
|
||||
// If this is a store conditional, act appropriately
|
||||
if (req->flags & LOCKED) {
|
||||
cregs = &this->xc->regs.miscRegs;
|
||||
cregs = &req->xc->regs.miscRegs;
|
||||
|
||||
if (req->flags & UNCACHEABLE) {
|
||||
// Don't update result register (see stq_c in isa_desc)
|
||||
req->result = 2;
|
||||
req->xc->storeCondFailures = 0;//Needed? [RGD]
|
||||
} else {
|
||||
req->result = cregs->lock_flag;
|
||||
if (!cregs->lock_flag ||
|
||||
((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
|
||||
cregs->lock_flag = false;
|
||||
bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag);
|
||||
Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag);
|
||||
req->result = lock_flag;
|
||||
if (!lock_flag ||
|
||||
((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
|
||||
cregs->setReg(TheISA::Lock_Flag_DepTag, false);
|
||||
if (((++req->xc->storeCondFailures) % 100000) == 0) {
|
||||
std::cerr << "Warning: "
|
||||
<< req->xc->storeCondFailures
|
||||
<< " consecutive store conditional failures "
|
||||
<< "on cpu " << this->cpu_id
|
||||
<< "on cpu " << req->xc->cpu_id
|
||||
<< std::endl;
|
||||
}
|
||||
return NoFault;
|
||||
|
@ -273,8 +268,9 @@ class AlphaFullCPU : public FullO3CPU<Impl>
|
|||
// through.
|
||||
for (int i = 0; i < this->system->execContexts.size(); i++){
|
||||
cregs = &this->system->execContexts[i]->regs.miscRegs;
|
||||
if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
|
||||
cregs->lock_flag = false;
|
||||
if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
|
||||
(req->paddr & ~0xf)) {
|
||||
cregs->setReg(TheISA::Lock_Flag_DepTag, false);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -179,12 +179,12 @@ AlphaFullCPU<Impl>::copyToXC()
|
|||
this->xc->regs.floatRegFile.q[i] =
|
||||
this->regFile.readFloatRegInt(renamed_reg);
|
||||
}
|
||||
|
||||
/*
|
||||
this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr;
|
||||
this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq;
|
||||
this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag;
|
||||
this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr;
|
||||
|
||||
*/
|
||||
this->xc->regs.pc = this->rob.readHeadPC();
|
||||
this->xc->regs.npc = this->xc->regs.pc+4;
|
||||
|
||||
|
@ -221,13 +221,13 @@ AlphaFullCPU<Impl>::copyFromXC()
|
|||
this->regFile.setFloatRegInt(renamed_reg,
|
||||
this->xc->regs.floatRegFile.q[i]);
|
||||
}
|
||||
|
||||
/*
|
||||
// Then loop through the misc registers.
|
||||
this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr;
|
||||
this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq;
|
||||
this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag;
|
||||
this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr;
|
||||
|
||||
*/
|
||||
// Then finally set the PC and the next PC.
|
||||
// regFile.pc = xc->regs.pc;
|
||||
// regFile.npc = xc->regs.npc;
|
||||
|
@ -237,27 +237,6 @@ AlphaFullCPU<Impl>::copyFromXC()
|
|||
|
||||
#if FULL_SYSTEM
|
||||
|
||||
template <class Impl>
|
||||
uint64_t *
|
||||
AlphaFullCPU<Impl>::getIpr()
|
||||
{
|
||||
return this->regFile.getIpr();
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
uint64_t
|
||||
AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
|
||||
{
|
||||
return this->regFile.readIpr(idx, fault);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
Fault
|
||||
AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
|
||||
{
|
||||
return this->regFile.setIpr(idx, val);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
int
|
||||
AlphaFullCPU<Impl>::readIntrFlag()
|
||||
|
@ -277,16 +256,14 @@ template <class Impl>
|
|||
Fault
|
||||
AlphaFullCPU<Impl>::hwrei()
|
||||
{
|
||||
uint64_t *ipr = getIpr();
|
||||
|
||||
if (!inPalMode())
|
||||
return UnimplementedOpcodeFault;
|
||||
|
||||
this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
|
||||
this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
|
||||
|
||||
// kernelStats.hwrei();
|
||||
|
||||
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
|
||||
if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
|
||||
// AlphaISA::swap_palshadow(®s, false);
|
||||
|
||||
this->checkInterrupts = true;
|
||||
|
@ -337,22 +314,23 @@ AlphaFullCPU<Impl>::trap(Fault fault)
|
|||
if (fault == ArithmeticFault)
|
||||
panic("Arithmetic traps are unimplemented!");
|
||||
|
||||
AlphaISA::InternalProcReg *ipr = getIpr();
|
||||
|
||||
// exception restart address - Get the commit PC
|
||||
if (fault != InterruptFault || !inPalMode(PC))
|
||||
ipr[AlphaISA::IPR_EXC_ADDR] = PC;
|
||||
this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
|
||||
|
||||
if (fault == PalFault || fault == ArithmeticFault /* ||
|
||||
fault == InterruptFault && !PC_PAL(regs.pc) */) {
|
||||
// traps... skip faulting instruction
|
||||
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
|
||||
AlphaISA::MiscReg ipr_exc_addr =
|
||||
this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
|
||||
this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR,
|
||||
ipr_exc_addr + 4);
|
||||
}
|
||||
|
||||
if (!inPalMode(PC))
|
||||
swapPALShadow(true);
|
||||
|
||||
this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
|
||||
this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
|
||||
AlphaISA::fault_addr(fault) );
|
||||
this->regFile.setNextPC(PC + sizeof(MachInst));
|
||||
}
|
||||
|
|
|
@ -54,6 +54,8 @@ class AlphaDynInst : public BaseDynInst<Impl>
|
|||
typedef TheISA::RegIndex RegIndex;
|
||||
/** Integer register index type. */
|
||||
typedef TheISA::IntReg IntReg;
|
||||
/** Misc register index type. */
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
|
||||
enum {
|
||||
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
|
||||
|
@ -75,15 +77,35 @@ class AlphaDynInst : public BaseDynInst<Impl>
|
|||
}
|
||||
|
||||
public:
|
||||
uint64_t readUniq();
|
||||
void setUniq(uint64_t val);
|
||||
MiscReg readMiscReg(int misc_reg)
|
||||
{
|
||||
// Dummy function for now.
|
||||
// @todo: Fix this once reg file gets fixed.
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint64_t readFpcr();
|
||||
void setFpcr(uint64_t val);
|
||||
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
|
||||
{
|
||||
// Dummy function for now.
|
||||
// @todo: Fix this once reg file gets fixed.
|
||||
return 0;
|
||||
}
|
||||
|
||||
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
||||
{
|
||||
// Dummy function for now.
|
||||
// @todo: Fix this once reg file gets fixed.
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
||||
{
|
||||
// Dummy function for now.
|
||||
// @todo: Fix this once reg file gets fixed.
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
uint64_t readIpr(int idx, Fault &fault);
|
||||
Fault setIpr(int idx, uint64_t val);
|
||||
Fault hwrei();
|
||||
int readIntrFlag();
|
||||
void setIntrFlag(int val);
|
||||
|
|
|
@ -67,49 +67,7 @@ AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
|
|||
}
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
uint64_t
|
||||
AlphaDynInst<Impl>::readUniq()
|
||||
{
|
||||
return this->cpu->readUniq();
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
AlphaDynInst<Impl>::setUniq(uint64_t val)
|
||||
{
|
||||
this->cpu->setUniq(val);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
uint64_t
|
||||
AlphaDynInst<Impl>::readFpcr()
|
||||
{
|
||||
return this->cpu->readFpcr();
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
AlphaDynInst<Impl>::setFpcr(uint64_t val)
|
||||
{
|
||||
this->cpu->setFpcr(val);
|
||||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
template <class Impl>
|
||||
uint64_t
|
||||
AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
|
||||
{
|
||||
return this->cpu->readIpr(idx, fault);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
Fault
|
||||
AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
|
||||
{
|
||||
return this->cpu->setIpr(idx, val);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
Fault
|
||||
AlphaDynInst<Impl>::hwrei()
|
||||
|
|
|
@ -264,13 +264,13 @@ FullO3CPU<Impl>::init()
|
|||
regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i];
|
||||
regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i];
|
||||
}
|
||||
|
||||
/*
|
||||
// Then loop through the misc registers.
|
||||
regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr;
|
||||
regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq;
|
||||
regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag;
|
||||
regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr;
|
||||
|
||||
*/
|
||||
// Then finally set the PC and the next PC.
|
||||
regFile.pc = src_xc->regs.pc;
|
||||
regFile.npc = src_xc->regs.npc;
|
||||
|
|
|
@ -152,11 +152,11 @@ class FullO3CPU : public BaseFullCPU
|
|||
|
||||
/** Get instruction asid. */
|
||||
int getInstAsid()
|
||||
{ return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); }
|
||||
{ return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); }
|
||||
|
||||
/** Get data asid. */
|
||||
int getDataAsid()
|
||||
{ return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); }
|
||||
{ return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); }
|
||||
#else
|
||||
bool validInstAddr(Addr addr)
|
||||
{ return thread[0]->validInstAddr(addr); }
|
||||
|
|
|
@ -56,6 +56,8 @@ class PhysRegFile
|
|||
typedef TheISA::IntReg IntReg;
|
||||
typedef TheISA::FloatReg FloatReg;
|
||||
typedef TheISA::MiscRegFile MiscRegFile;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
|
||||
//Note that most of the definitions of the IntReg, FloatReg, etc. exist
|
||||
//within the Impl/ISA class and not within this PhysRegFile class.
|
||||
|
||||
|
@ -194,30 +196,21 @@ class PhysRegFile
|
|||
|
||||
//Consider leaving this stuff and below in some implementation specific
|
||||
//file as opposed to the general register file. Or have a derived class.
|
||||
uint64_t readUniq()
|
||||
MiscReg readMiscReg(int misc_reg)
|
||||
{
|
||||
return miscRegs.uniq;
|
||||
// Dummy function for now.
|
||||
// @todo: Fix this once proxy XC is used.
|
||||
return 0;
|
||||
}
|
||||
|
||||
void setUniq(uint64_t val)
|
||||
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
||||
{
|
||||
miscRegs.uniq = val;
|
||||
}
|
||||
|
||||
uint64_t readFpcr()
|
||||
{
|
||||
return miscRegs.fpcr;
|
||||
}
|
||||
|
||||
void setFpcr(uint64_t val)
|
||||
{
|
||||
miscRegs.fpcr = val;
|
||||
// Dummy function for now.
|
||||
// @todo: Fix this once proxy XC is used.
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
uint64_t readIpr(int idx, Fault &fault);
|
||||
Fault setIpr(int idx, uint64_t val);
|
||||
InternalProcReg *getIpr() { return ipr; }
|
||||
int readIntrFlag() { return intrflag; }
|
||||
void setIntrFlag(int val) { intrflag = val; }
|
||||
#endif
|
||||
|
@ -272,368 +265,4 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
|
|||
memset(floatRegFile, 0, sizeof(*floatRegFile));
|
||||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
|
||||
//Problem: This code doesn't make sense at the RegFile level because it
|
||||
//needs things such as the itb and dtb. Either put it at the CPU level or
|
||||
//the DynInst level.
|
||||
template <class Impl>
|
||||
uint64_t
|
||||
PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
|
||||
{
|
||||
uint64_t retval = 0; // return value, default 0
|
||||
|
||||
switch (idx) {
|
||||
case TheISA::IPR_PALtemp0:
|
||||
case TheISA::IPR_PALtemp1:
|
||||
case TheISA::IPR_PALtemp2:
|
||||
case TheISA::IPR_PALtemp3:
|
||||
case TheISA::IPR_PALtemp4:
|
||||
case TheISA::IPR_PALtemp5:
|
||||
case TheISA::IPR_PALtemp6:
|
||||
case TheISA::IPR_PALtemp7:
|
||||
case TheISA::IPR_PALtemp8:
|
||||
case TheISA::IPR_PALtemp9:
|
||||
case TheISA::IPR_PALtemp10:
|
||||
case TheISA::IPR_PALtemp11:
|
||||
case TheISA::IPR_PALtemp12:
|
||||
case TheISA::IPR_PALtemp13:
|
||||
case TheISA::IPR_PALtemp14:
|
||||
case TheISA::IPR_PALtemp15:
|
||||
case TheISA::IPR_PALtemp16:
|
||||
case TheISA::IPR_PALtemp17:
|
||||
case TheISA::IPR_PALtemp18:
|
||||
case TheISA::IPR_PALtemp19:
|
||||
case TheISA::IPR_PALtemp20:
|
||||
case TheISA::IPR_PALtemp21:
|
||||
case TheISA::IPR_PALtemp22:
|
||||
case TheISA::IPR_PALtemp23:
|
||||
case TheISA::IPR_PAL_BASE:
|
||||
|
||||
case TheISA::IPR_IVPTBR:
|
||||
case TheISA::IPR_DC_MODE:
|
||||
case TheISA::IPR_MAF_MODE:
|
||||
case TheISA::IPR_ISR:
|
||||
case TheISA::IPR_EXC_ADDR:
|
||||
case TheISA::IPR_IC_PERR_STAT:
|
||||
case TheISA::IPR_DC_PERR_STAT:
|
||||
case TheISA::IPR_MCSR:
|
||||
case TheISA::IPR_ASTRR:
|
||||
case TheISA::IPR_ASTER:
|
||||
case TheISA::IPR_SIRR:
|
||||
case TheISA::IPR_ICSR:
|
||||
case TheISA::IPR_ICM:
|
||||
case TheISA::IPR_DTB_CM:
|
||||
case TheISA::IPR_IPLR:
|
||||
case TheISA::IPR_INTID:
|
||||
case TheISA::IPR_PMCTR:
|
||||
// no side-effect
|
||||
retval = ipr[idx];
|
||||
break;
|
||||
|
||||
case TheISA::IPR_CC:
|
||||
retval |= ipr[idx] & ULL(0xffffffff00000000);
|
||||
retval |= curTick & ULL(0x00000000ffffffff);
|
||||
break;
|
||||
|
||||
case TheISA::IPR_VA:
|
||||
retval = ipr[idx];
|
||||
break;
|
||||
|
||||
case TheISA::IPR_VA_FORM:
|
||||
case TheISA::IPR_MM_STAT:
|
||||
case TheISA::IPR_IFAULT_VA_FORM:
|
||||
case TheISA::IPR_EXC_MASK:
|
||||
case TheISA::IPR_EXC_SUM:
|
||||
retval = ipr[idx];
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DTB_PTE:
|
||||
{
|
||||
TheISA::PTE &pte = cpu->dtb->index(1);
|
||||
|
||||
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
|
||||
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
|
||||
retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
|
||||
retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
|
||||
retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
|
||||
retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
|
||||
retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
|
||||
}
|
||||
break;
|
||||
|
||||
// write only registers
|
||||
case TheISA::IPR_HWINT_CLR:
|
||||
case TheISA::IPR_SL_XMIT:
|
||||
case TheISA::IPR_DC_FLUSH:
|
||||
case TheISA::IPR_IC_FLUSH:
|
||||
case TheISA::IPR_ALT_MODE:
|
||||
case TheISA::IPR_DTB_IA:
|
||||
case TheISA::IPR_DTB_IAP:
|
||||
case TheISA::IPR_ITB_IA:
|
||||
case TheISA::IPR_ITB_IAP:
|
||||
fault = UnimplementedOpcodeFault;
|
||||
break;
|
||||
|
||||
default:
|
||||
// invalid IPR
|
||||
fault = UnimplementedOpcodeFault;
|
||||
break;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
extern int break_ipl;
|
||||
|
||||
template <class Impl>
|
||||
Fault
|
||||
PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
|
||||
{
|
||||
uint64_t old;
|
||||
|
||||
switch (idx) {
|
||||
case TheISA::IPR_PALtemp0:
|
||||
case TheISA::IPR_PALtemp1:
|
||||
case TheISA::IPR_PALtemp2:
|
||||
case TheISA::IPR_PALtemp3:
|
||||
case TheISA::IPR_PALtemp4:
|
||||
case TheISA::IPR_PALtemp5:
|
||||
case TheISA::IPR_PALtemp6:
|
||||
case TheISA::IPR_PALtemp7:
|
||||
case TheISA::IPR_PALtemp8:
|
||||
case TheISA::IPR_PALtemp9:
|
||||
case TheISA::IPR_PALtemp10:
|
||||
case TheISA::IPR_PALtemp11:
|
||||
case TheISA::IPR_PALtemp12:
|
||||
case TheISA::IPR_PALtemp13:
|
||||
case TheISA::IPR_PALtemp14:
|
||||
case TheISA::IPR_PALtemp15:
|
||||
case TheISA::IPR_PALtemp16:
|
||||
case TheISA::IPR_PALtemp17:
|
||||
case TheISA::IPR_PALtemp18:
|
||||
case TheISA::IPR_PALtemp19:
|
||||
case TheISA::IPR_PALtemp20:
|
||||
case TheISA::IPR_PALtemp21:
|
||||
case TheISA::IPR_PALtemp22:
|
||||
case TheISA::IPR_PAL_BASE:
|
||||
case TheISA::IPR_IC_PERR_STAT:
|
||||
case TheISA::IPR_DC_PERR_STAT:
|
||||
case TheISA::IPR_PMCTR:
|
||||
// write entire quad w/ no side-effect
|
||||
ipr[idx] = val;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_CC_CTL:
|
||||
// This IPR resets the cycle counter. We assume this only
|
||||
// happens once... let's verify that.
|
||||
assert(ipr[idx] == 0);
|
||||
ipr[idx] = 1;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_CC:
|
||||
// This IPR only writes the upper 64 bits. It's ok to write
|
||||
// all 64 here since we mask out the lower 32 in rpcc (see
|
||||
// isa_desc).
|
||||
ipr[idx] = val;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_PALtemp23:
|
||||
// write entire quad w/ no side-effect
|
||||
old = ipr[idx];
|
||||
ipr[idx] = val;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DTB_PTE:
|
||||
// write entire quad w/ no side-effect, tag is forthcoming
|
||||
ipr[idx] = val;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_EXC_ADDR:
|
||||
// second least significant bit in PC is always zero
|
||||
ipr[idx] = val & ~2;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_ASTRR:
|
||||
case TheISA::IPR_ASTER:
|
||||
// only write least significant four bits - privilege mask
|
||||
ipr[idx] = val & 0xf;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_IPLR:
|
||||
// only write least significant five bits - interrupt level
|
||||
ipr[idx] = val & 0x1f;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DTB_CM:
|
||||
|
||||
case TheISA::IPR_ICM:
|
||||
// only write two mode bits - processor mode
|
||||
ipr[idx] = val & 0x18;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_ALT_MODE:
|
||||
// only write two mode bits - processor mode
|
||||
ipr[idx] = val & 0x18;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_MCSR:
|
||||
// more here after optimization...
|
||||
ipr[idx] = val;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_SIRR:
|
||||
// only write software interrupt mask
|
||||
ipr[idx] = val & 0x7fff0;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_ICSR:
|
||||
ipr[idx] = val & ULL(0xffffff0300);
|
||||
break;
|
||||
|
||||
case TheISA::IPR_IVPTBR:
|
||||
case TheISA::IPR_MVPTBR:
|
||||
ipr[idx] = val & ULL(0xffffffffc0000000);
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DC_TEST_CTL:
|
||||
ipr[idx] = val & 0x1ffb;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DC_MODE:
|
||||
case TheISA::IPR_MAF_MODE:
|
||||
ipr[idx] = val & 0x3f;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_ITB_ASN:
|
||||
ipr[idx] = val & 0x7f0;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DTB_ASN:
|
||||
ipr[idx] = val & ULL(0xfe00000000000000);
|
||||
break;
|
||||
|
||||
case TheISA::IPR_EXC_SUM:
|
||||
case TheISA::IPR_EXC_MASK:
|
||||
// any write to this register clears it
|
||||
ipr[idx] = 0;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_INTID:
|
||||
case TheISA::IPR_SL_RCV:
|
||||
case TheISA::IPR_MM_STAT:
|
||||
case TheISA::IPR_ITB_PTE_TEMP:
|
||||
case TheISA::IPR_DTB_PTE_TEMP:
|
||||
// read-only registers
|
||||
return UnimplementedOpcodeFault;
|
||||
|
||||
case TheISA::IPR_HWINT_CLR:
|
||||
case TheISA::IPR_SL_XMIT:
|
||||
case TheISA::IPR_DC_FLUSH:
|
||||
case TheISA::IPR_IC_FLUSH:
|
||||
// the following are write only
|
||||
ipr[idx] = val;
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DTB_IA:
|
||||
// really a control write
|
||||
ipr[idx] = 0;
|
||||
|
||||
cpu->dtb->flushAll();
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DTB_IAP:
|
||||
// really a control write
|
||||
ipr[idx] = 0;
|
||||
|
||||
cpu->dtb->flushProcesses();
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DTB_IS:
|
||||
// really a control write
|
||||
ipr[idx] = val;
|
||||
|
||||
cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]));
|
||||
break;
|
||||
|
||||
case TheISA::IPR_DTB_TAG: {
|
||||
struct TheISA::PTE pte;
|
||||
|
||||
// FIXME: granularity hints NYI...
|
||||
if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0)
|
||||
panic("PTE GH field != 0");
|
||||
|
||||
// write entire quad
|
||||
ipr[idx] = val;
|
||||
|
||||
// construct PTE for new entry
|
||||
pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]);
|
||||
pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]);
|
||||
pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]);
|
||||
pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]);
|
||||
pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]);
|
||||
pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]);
|
||||
pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]);
|
||||
|
||||
// insert new TAG/PTE value into data TLB
|
||||
cpu->dtb->insert(val, pte);
|
||||
}
|
||||
break;
|
||||
|
||||
case TheISA::IPR_ITB_PTE: {
|
||||
struct TheISA::PTE pte;
|
||||
|
||||
// FIXME: granularity hints NYI...
|
||||
if (ITB_PTE_GH(val) != 0)
|
||||
panic("PTE GH field != 0");
|
||||
|
||||
// write entire quad
|
||||
ipr[idx] = val;
|
||||
|
||||
// construct PTE for new entry
|
||||
pte.ppn = ITB_PTE_PPN(val);
|
||||
pte.xre = ITB_PTE_XRE(val);
|
||||
pte.xwe = 0;
|
||||
pte.fonr = ITB_PTE_FONR(val);
|
||||
pte.fonw = ITB_PTE_FONW(val);
|
||||
pte.asma = ITB_PTE_ASMA(val);
|
||||
pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]);
|
||||
|
||||
// insert new TAG/PTE value into data TLB
|
||||
cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte);
|
||||
}
|
||||
break;
|
||||
|
||||
case TheISA::IPR_ITB_IA:
|
||||
// really a control write
|
||||
ipr[idx] = 0;
|
||||
|
||||
cpu->itb->flushAll();
|
||||
break;
|
||||
|
||||
case TheISA::IPR_ITB_IAP:
|
||||
// really a control write
|
||||
ipr[idx] = 0;
|
||||
|
||||
cpu->itb->flushProcesses();
|
||||
break;
|
||||
|
||||
case TheISA::IPR_ITB_IS:
|
||||
// really a control write
|
||||
ipr[idx] = val;
|
||||
|
||||
cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]));
|
||||
break;
|
||||
|
||||
default:
|
||||
// invalid IPR
|
||||
return UnimplementedOpcodeFault;
|
||||
}
|
||||
|
||||
// no error...
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
#endif // #if FULL_SYSTEM
|
||||
|
||||
#endif // __CPU_O3_CPU_REGFILE_HH__
|
||||
|
|
|
@ -659,12 +659,11 @@ SimpleCPU::tick()
|
|||
int ipl = 0;
|
||||
int summary = 0;
|
||||
checkInterrupts = false;
|
||||
IntReg *ipr = xc->regs.ipr;
|
||||
|
||||
if (xc->regs.ipr[IPR_SIRR]) {
|
||||
if (xc->readMiscReg(IPR_SIRR)) {
|
||||
for (int i = INTLEVEL_SOFTWARE_MIN;
|
||||
i < INTLEVEL_SOFTWARE_MAX; i++) {
|
||||
if (ipr[IPR_SIRR] & (ULL(1) << i)) {
|
||||
if (xc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
|
||||
// See table 4-19 of 21164 hardware reference
|
||||
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
|
||||
summary |= (ULL(1) << i);
|
||||
|
@ -682,16 +681,16 @@ SimpleCPU::tick()
|
|||
}
|
||||
}
|
||||
|
||||
if (ipr[IPR_ASTRR])
|
||||
if (xc->readMiscReg(IPR_ASTRR))
|
||||
panic("asynchronous traps not implemented\n");
|
||||
|
||||
if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
|
||||
ipr[IPR_ISR] = summary;
|
||||
ipr[IPR_INTID] = ipl;
|
||||
if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) {
|
||||
xc->setMiscReg(IPR_ISR, summary);
|
||||
xc->setMiscReg(IPR_INTID, ipl);
|
||||
xc->ev5_trap(InterruptFault);
|
||||
|
||||
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
|
||||
ipr[IPR_IPLR], ipl, summary);
|
||||
xc->readMiscReg(IPR_IPLR), ipl, summary);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
@ -782,7 +781,7 @@ SimpleCPU::tick()
|
|||
}
|
||||
|
||||
if (xc->profile) {
|
||||
bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0;
|
||||
bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
|
||||
xc->profilePC = usermode ? 1 : xc->regs.pc;
|
||||
ProfileNode *node = xc->profile->consume(xc, inst);
|
||||
if (node)
|
||||
|
|
|
@ -65,6 +65,7 @@ class SimpleCPU : public BaseCPU
|
|||
{
|
||||
protected:
|
||||
typedef TheISA::MachInst MachInst;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
public:
|
||||
// main simulation loop (one cycle)
|
||||
void tick();
|
||||
|
@ -321,15 +322,27 @@ class SimpleCPU : public BaseCPU
|
|||
uint64_t readPC() { return xc->readPC(); }
|
||||
void setNextPC(uint64_t val) { xc->setNextPC(val); }
|
||||
|
||||
uint64_t readUniq() { return xc->readUniq(); }
|
||||
void setUniq(uint64_t val) { xc->setUniq(val); }
|
||||
MiscReg readMiscReg(int misc_reg)
|
||||
{
|
||||
return xc->readMiscReg(misc_reg);
|
||||
}
|
||||
|
||||
uint64_t readFpcr() { return xc->readFpcr(); }
|
||||
void setFpcr(uint64_t val) { xc->setFpcr(val); }
|
||||
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
|
||||
{
|
||||
return xc->readMiscRegWithEffect(misc_reg, fault);
|
||||
}
|
||||
|
||||
Fault setMiscReg(int misc_reg, const MiscReg &val)
|
||||
{
|
||||
return xc->setMiscReg(misc_reg, val);
|
||||
}
|
||||
|
||||
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
||||
{
|
||||
return xc->setMiscRegWithEffect(misc_reg, val);
|
||||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
|
||||
Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
|
||||
Fault hwrei() { return xc->hwrei(); }
|
||||
int readIntrFlag() { return xc->readIntrFlag(); }
|
||||
void setIntrFlag(int val) { xc->setIntrFlag(val); }
|
||||
|
|
|
@ -376,7 +376,7 @@ Device::read(MemReqPtr &req, uint8_t *data)
|
|||
Fault
|
||||
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
|
||||
{
|
||||
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
|
||||
int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff;
|
||||
Addr index = daddr >> Regs::VirtualShift;
|
||||
Addr raddr = daddr & Regs::VirtualMask;
|
||||
|
||||
|
@ -472,7 +472,7 @@ Device::write(MemReqPtr &req, const uint8_t *data)
|
|||
Fault
|
||||
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
|
||||
{
|
||||
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
|
||||
int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff;
|
||||
Addr index = daddr >> Regs::VirtualShift;
|
||||
Addr raddr = daddr & Regs::VirtualMask;
|
||||
|
||||
|
|
|
@ -240,7 +240,7 @@ Statistics::swpipl(int ipl)
|
|||
void
|
||||
Statistics::mode(cpu_mode newmode)
|
||||
{
|
||||
Addr pcbb = xc->regs.ipr[AlphaISA::IPR_PALtemp23];
|
||||
Addr pcbb = xc->readMiscReg(AlphaISA::IPR_PALtemp23);
|
||||
|
||||
if ((newmode == kernel || newmode == interrupt) &&
|
||||
pcbb == idleProcess)
|
||||
|
|
|
@ -67,7 +67,7 @@ FnEvent::process(ExecContext *xc)
|
|||
void
|
||||
IdleStartEvent::process(ExecContext *xc)
|
||||
{
|
||||
xc->kernelStats->setIdleProcess(xc->regs.ipr[AlphaISA::IPR_PALtemp23]);
|
||||
xc->kernelStats->setIdleProcess(xc->readMiscReg(AlphaISA::IPR_PALtemp23));
|
||||
remove();
|
||||
}
|
||||
|
||||
|
|
|
@ -729,7 +729,7 @@ class Tru64 {
|
|||
regs->floatRegFile.q[i] = htog(sc->sc_fpregs[i]);
|
||||
}
|
||||
|
||||
regs->miscRegs.fpcr = htog(sc->sc_fpcr);
|
||||
xc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -889,7 +889,7 @@ class Tru64 {
|
|||
ssp->nxm_sysevent = htog(0);
|
||||
|
||||
if (i == 0) {
|
||||
uint64_t uniq = xc->regs.miscRegs.uniq;
|
||||
uint64_t uniq = xc->readMiscReg(TheISA::Uniq_DepTag);
|
||||
ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset));
|
||||
ssp->nxm_u.nxm_active = htog(uniq | 1);
|
||||
}
|
||||
|
@ -924,7 +924,7 @@ class Tru64 {
|
|||
ec->regs.intRegFile[TheISA::ArgumentReg0] = gtoh(attrp->registers.a0);
|
||||
ec->regs.intRegFile[27/*t12*/] = gtoh(attrp->registers.pc);
|
||||
ec->regs.intRegFile[TheISA::StackPointerReg] = gtoh(attrp->registers.sp);
|
||||
ec->regs.miscRegs.uniq = uniq_val;
|
||||
ec->setMiscReg(TheISA::Uniq_DepTag, uniq_val);
|
||||
|
||||
ec->regs.pc = gtoh(attrp->registers.pc);
|
||||
ec->regs.npc = gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst);
|
||||
|
|
Loading…
Reference in a new issue