70b35bab57
They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).
arch/alpha/alpha_memory.cc:
Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes.
The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
Change access to the IPR to go through the XC.
arch/isa_parser.py:
Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
Change accesses to the IPRs to go through the miscRegs.
For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
Remove old misc reg accessors.
cpu/o3/cpu.cc:
Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
Change accesses to the misc regs.
cpu/o3/regfile.hh:
Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
Have accesses to the misc regs use the new access methods.
--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
673 lines
19 KiB
C++
673 lines
19 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/alpha/alpha_memory.hh"
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/osfpal.hh"
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#include "base/kgdb.h"
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#include "base/remote_gdb.hh"
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#include "base/stats/events.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/fast/cpu.hh"
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#include "kern/kernel_stats.hh"
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#include "sim/debug.hh"
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#include "sim/sim_events.hh"
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#if FULL_SYSTEM
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using namespace EV5;
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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void
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AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
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{
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if (regs->pal_shadow == use_shadow)
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panic("swap_palshadow: wrong PAL shadow state");
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regs->pal_shadow = use_shadow;
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for (int i = 0; i < NumIntRegs; i++) {
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if (reg_redir[i]) {
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IntReg temp = regs->intRegFile[i];
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regs->intRegFile[i] = regs->palregs[i];
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regs->palregs[i] = temp;
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}
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}
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}
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////////////////////////////////////////////////////////////////////////
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//
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// Machine dependent functions
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//
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void
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AlphaISA::initCPU(RegFile *regs, int cpuId)
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{
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initIPRs(®s->miscRegs, cpuId);
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// CPU comes up with PAL regs enabled
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swap_palshadow(regs, true);
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regs->intRegFile[16] = cpuId;
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regs->intRegFile[0] = cpuId;
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regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + fault_addr(ResetFault);
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regs->npc = regs->pc + sizeof(MachInst);
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}
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////////////////////////////////////////////////////////////////////////
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//
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// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
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//
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const Addr
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AlphaISA::fault_addr(Fault fault)
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{
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//Check for the system wide faults
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if(fault == NoFault) return 0x0000;
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else if(fault == MachineCheckFault) return 0x0401;
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else if(fault == AlignmentFault) return 0x0301;
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//Deal with the alpha specific faults
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return ((AlphaFault*)fault)->vect;
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};
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const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
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/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
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/* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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void
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AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId)
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{
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miscRegs->clearIprs();
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miscRegs->setReg(IPR_PAL_BASE, PalBase);
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miscRegs->setReg(IPR_MCSR, 0x6);
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miscRegs->setReg(IPR_PALtemp16, cpuId);
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}
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template <class CPU>
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void
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AlphaISA::processInterrupts(CPU *cpu)
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{
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//Check if there are any outstanding interrupts
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//Handle the interrupts
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int ipl = 0;
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int summary = 0;
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cpu->checkInterrupts = false;
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if (cpu->readMiscReg(IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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if (cpu->readMiscReg(IPR_SIRR)) {
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for (int i = INTLEVEL_SOFTWARE_MIN;
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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}
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uint64_t interrupts = cpu->intr_status();
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if (interrupts) {
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for (int i = INTLEVEL_EXTERNAL_MIN;
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i < INTLEVEL_EXTERNAL_MAX; i++) {
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if (interrupts & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = i;
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summary |= (ULL(1) << i);
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}
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}
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}
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if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
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cpu->setMiscReg(IPR_ISR, summary);
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cpu->setMiscReg(IPR_INTID, ipl);
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cpu->trap(InterruptFault);
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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cpu->readMiscReg(IPR_IPLR), ipl, summary);
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}
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}
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template <class CPU>
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void
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AlphaISA::zeroRegisters(CPU *cpu)
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{
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// Insure ISA semantics
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// (no longer very clean due to the change in setIntReg() in the
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// cpu model. Consider changing later.)
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cpu->xc->setIntReg(ZeroReg, 0);
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cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
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}
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void
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ExecContext::ev5_trap(Fault fault)
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{
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DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
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cpu->recordEvent(csprintf("Fault %s", fault->name));
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assert(!misspeculating());
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kernelStats->fault(fault);
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if (fault == ArithmeticFault)
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panic("Arithmetic traps are unimplemented!");
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// exception restart address
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if (fault != InterruptFault || !inPalMode())
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setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
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if (fault == PalFault || fault == ArithmeticFault /* ||
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fault == InterruptFault && !inPalMode() */) {
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// traps... skip faulting instruction
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setMiscReg(AlphaISA::IPR_EXC_ADDR,
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readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
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}
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if (!inPalMode())
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AlphaISA::swap_palshadow(®s, true);
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regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) + AlphaISA::fault_addr(fault);
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regs.npc = regs.pc + sizeof(MachInst);
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}
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void
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AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
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{
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bool use_pc = (fault == NoFault);
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if (fault == ArithmeticFault)
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panic("arithmetic faults NYI...");
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// compute exception restart address
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if (use_pc || fault == PalFault || fault == ArithmeticFault) {
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// traps... skip faulting instruction
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regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
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} else {
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// fault, post fault at excepting instruction
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regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
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}
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// jump to expection address (PAL PC bit set here as well...)
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if (!use_pc)
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regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
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fault_addr(fault);
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else
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regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
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// that's it! (orders of magnitude less painful than x86)
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}
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Fault
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ExecContext::hwrei()
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{
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if (!inPalMode())
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return UnimplementedOpcodeFault;
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setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
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if (!misspeculating()) {
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kernelStats->hwrei();
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if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
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AlphaISA::swap_palshadow(®s, false);
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cpu->checkInterrupts = true;
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}
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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}
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void
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AlphaISA::MiscRegFile::clearIprs()
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{
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bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
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}
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AlphaISA::MiscReg
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AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
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{
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PALtemp23:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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case AlphaISA::IPR_ISR:
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case AlphaISA::IPR_EXC_ADDR:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_MCSR:
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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case AlphaISA::IPR_SIRR:
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case AlphaISA::IPR_ICSR:
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case AlphaISA::IPR_ICM:
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case AlphaISA::IPR_DTB_CM:
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case AlphaISA::IPR_IPLR:
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case AlphaISA::IPR_INTID:
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case AlphaISA::IPR_PMCTR:
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// no side-effect
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= xc->cpu->curCycle() & ULL(0x00000000ffffffff);
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break;
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case AlphaISA::IPR_VA:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_VA_FORM:
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case AlphaISA::IPR_MM_STAT:
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case AlphaISA::IPR_IFAULT_VA_FORM:
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case AlphaISA::IPR_EXC_MASK:
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case AlphaISA::IPR_EXC_SUM:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_DTB_PTE:
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{
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AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating());
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
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}
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break;
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// write only registers
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case AlphaISA::IPR_HWINT_CLR:
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case AlphaISA::IPR_SL_XMIT:
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case AlphaISA::IPR_DC_FLUSH:
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case AlphaISA::IPR_IC_FLUSH:
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case AlphaISA::IPR_ALT_MODE:
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case AlphaISA::IPR_DTB_IA:
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case AlphaISA::IPR_DTB_IAP:
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case AlphaISA::IPR_ITB_IA:
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case AlphaISA::IPR_ITB_IAP:
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fault = UnimplementedOpcodeFault;
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break;
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default:
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// invalid IPR
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fault = UnimplementedOpcodeFault;
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break;
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}
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return retval;
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}
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#ifdef DEBUG
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// Cause the simulator to break when changing to the following IPL
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int break_ipl = -1;
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#endif
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Fault
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AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
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{
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uint64_t old;
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if (xc->misspeculating())
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return NoFault;
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_PMCTR:
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// write entire quad w/ no side-effect
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_CC_CTL:
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// This IPR resets the cycle counter. We assume this only
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// happens once... let's verify that.
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assert(ipr[idx] == 0);
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ipr[idx] = 1;
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break;
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case AlphaISA::IPR_CC:
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// This IPR only writes the upper 64 bits. It's ok to write
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// all 64 here since we mask out the lower 32 in rpcc (see
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// isa_desc).
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_PALtemp23:
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// write entire quad w/ no side-effect
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old = ipr[idx];
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ipr[idx] = val;
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xc->kernelStats->context(old, val);
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break;
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case AlphaISA::IPR_DTB_PTE:
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|
// write entire quad w/ no side-effect, tag is forthcoming
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_EXC_ADDR:
|
|
// second least significant bit in PC is always zero
|
|
ipr[idx] = val & ~2;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ASTRR:
|
|
case AlphaISA::IPR_ASTER:
|
|
// only write least significant four bits - privilege mask
|
|
ipr[idx] = val & 0xf;
|
|
break;
|
|
|
|
case AlphaISA::IPR_IPLR:
|
|
#ifdef DEBUG
|
|
if (break_ipl != -1 && break_ipl == (val & 0x1f))
|
|
debug_break();
|
|
#endif
|
|
|
|
// only write least significant five bits - interrupt level
|
|
ipr[idx] = val & 0x1f;
|
|
xc->kernelStats->swpipl(ipr[idx]);
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_CM:
|
|
if (val & 0x18)
|
|
xc->kernelStats->mode(Kernel::user);
|
|
else
|
|
xc->kernelStats->mode(Kernel::kernel);
|
|
|
|
case AlphaISA::IPR_ICM:
|
|
// only write two mode bits - processor mode
|
|
ipr[idx] = val & 0x18;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ALT_MODE:
|
|
// only write two mode bits - processor mode
|
|
ipr[idx] = val & 0x18;
|
|
break;
|
|
|
|
case AlphaISA::IPR_MCSR:
|
|
// more here after optimization...
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_SIRR:
|
|
// only write software interrupt mask
|
|
ipr[idx] = val & 0x7fff0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ICSR:
|
|
ipr[idx] = val & ULL(0xffffff0300);
|
|
break;
|
|
|
|
case AlphaISA::IPR_IVPTBR:
|
|
case AlphaISA::IPR_MVPTBR:
|
|
ipr[idx] = val & ULL(0xffffffffc0000000);
|
|
break;
|
|
|
|
case AlphaISA::IPR_DC_TEST_CTL:
|
|
ipr[idx] = val & 0x1ffb;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DC_MODE:
|
|
case AlphaISA::IPR_MAF_MODE:
|
|
ipr[idx] = val & 0x3f;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_ASN:
|
|
ipr[idx] = val & 0x7f0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_ASN:
|
|
ipr[idx] = val & ULL(0xfe00000000000000);
|
|
break;
|
|
|
|
case AlphaISA::IPR_EXC_SUM:
|
|
case AlphaISA::IPR_EXC_MASK:
|
|
// any write to this register clears it
|
|
ipr[idx] = 0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_INTID:
|
|
case AlphaISA::IPR_SL_RCV:
|
|
case AlphaISA::IPR_MM_STAT:
|
|
case AlphaISA::IPR_ITB_PTE_TEMP:
|
|
case AlphaISA::IPR_DTB_PTE_TEMP:
|
|
// read-only registers
|
|
return UnimplementedOpcodeFault;
|
|
|
|
case AlphaISA::IPR_HWINT_CLR:
|
|
case AlphaISA::IPR_SL_XMIT:
|
|
case AlphaISA::IPR_DC_FLUSH:
|
|
case AlphaISA::IPR_IC_FLUSH:
|
|
// the following are write only
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
xc->dtb->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
xc->dtb->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_TAG: {
|
|
struct AlphaISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
xc->dtb->insert(val, pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_PTE: {
|
|
struct AlphaISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (ITB_PTE_GH(val) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = ITB_PTE_PPN(val);
|
|
pte.xre = ITB_PTE_XRE(val);
|
|
pte.xwe = 0;
|
|
pte.fonr = ITB_PTE_FONR(val);
|
|
pte.fonw = ITB_PTE_FONW(val);
|
|
pte.asma = ITB_PTE_ASMA(val);
|
|
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
xc->itb->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
xc->itb->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
|
break;
|
|
|
|
default:
|
|
// invalid IPR
|
|
return UnimplementedOpcodeFault;
|
|
}
|
|
|
|
// no error...
|
|
return NoFault;
|
|
}
|
|
|
|
/**
|
|
* Check for special simulator handling of specific PAL calls.
|
|
* If return value is false, actual PAL call will be suppressed.
|
|
*/
|
|
bool
|
|
ExecContext::simPalCheck(int palFunc)
|
|
{
|
|
kernelStats->callpal(palFunc);
|
|
|
|
switch (palFunc) {
|
|
case PAL::halt:
|
|
halt();
|
|
if (--System::numSystemsRunning == 0)
|
|
new SimExitEvent("all cpus halted");
|
|
break;
|
|
|
|
case PAL::bpt:
|
|
case PAL::bugchk:
|
|
if (system->breakpoint())
|
|
return false;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
//Forward instantiation for FastCPU object
|
|
template
|
|
void AlphaISA::processInterrupts(FastCPU *xc);
|
|
|
|
//Forward instantiation for FastCPU object
|
|
template
|
|
void AlphaISA::zeroRegisters(FastCPU *xc);
|
|
|
|
#endif // FULL_SYSTEM
|