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gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

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X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- Begin Simulation Statistics ----------
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
sim_seconds 0.081225 # Number of seconds simulated
sim_ticks 81224844500 # Number of ticks simulated
final_tick 81224844500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
host_inst_rate 72712 # Simulator instruction rate (inst/s)
host_op_rate 121872 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44718419 # Simulator tick rate (ticks/s)
host_mem_usage 340792 # Number of bytes of host memory used
host_seconds 1816.36 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 132071192 # Number of instructions simulated
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
sim_ops 221363384 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125760 # Number of bytes read from this memory
system.physmem.bytes_read::total 350528 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1965 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5477 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 2767232 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1548295 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4315527 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2767232 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2767232 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2767232 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1548295 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4315527 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5477 # Number of read requests accepted
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.readBursts 5477 # Number of DRAM read bursts, including those serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.bytesReadDRAM 350528 # Total number of bytes read from DRAM
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.bytesReadSys 350528 # Total read bytes from the system interface side
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.neitherReadNorWriteReqs 298 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 295 # Per bank write bursts
system.physmem.perBankRdBursts::1 355 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::2 457 # Per bank write bursts
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.perBankRdBursts::3 353 # Per bank write bursts
system.physmem.perBankRdBursts::4 337 # Per bank write bursts
system.physmem.perBankRdBursts::5 331 # Per bank write bursts
system.physmem.perBankRdBursts::6 400 # Per bank write bursts
system.physmem.perBankRdBursts::7 389 # Per bank write bursts
system.physmem.perBankRdBursts::8 346 # Per bank write bursts
system.physmem.perBankRdBursts::9 296 # Per bank write bursts
system.physmem.perBankRdBursts::10 240 # Per bank write bursts
system.physmem.perBankRdBursts::11 297 # Per bank write bursts
system.physmem.perBankRdBursts::12 220 # Per bank write bursts
system.physmem.perBankRdBursts::13 472 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::14 395 # Per bank write bursts
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.perBankRdBursts::15 294 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.totGap 81224754500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.readPktSize::6 5477 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.rdQLenPdf::0 4344 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 189 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.bytesPerActivate::samples 1132 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 308.296820 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 177.870491 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.897635 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 457 40.37% 40.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 236 20.85% 61.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 108 9.54% 70.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 58 5.12% 75.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 52 4.59% 80.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 57 5.04% 85.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 15 1.33% 86.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 18 1.59% 88.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 131 11.57% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1132 # Bytes accessed per row activation
system.physmem.totQLat 39829000 # Total ticks spent queuing
system.physmem.totMemAccLat 142522750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 27385000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7272.05 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.avgMemAccLat 26022.05 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.32 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.readRowHits 4337 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.readRowHitRate 79.19 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem.avgGap 14830154.19 # Average gap between requests
system.physmem.pageHitRate 79.19 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 4944240 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2697750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 22612200 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem_0.refreshEnergy 5304789360 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2574291285 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 46473030000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 54382364835 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.579902 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 77308994750 # Time in different power states
system.physmem_0.memoryStateTime::REF 2712060000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem_0.memoryStateTime::ACT 1198731250 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem_1.actEnergy 3598560 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1963500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 19773000 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem_1.refreshEnergy 5304789360 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2411784000 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 46615580250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 54357488670 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.273616 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 77550451000 # Time in different power states
system.physmem_1.memoryStateTime::REF 2712060000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.physmem_1.memoryStateTime::ACT 960225000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.branchPred.lookups 21757824 # Number of BP lookups
system.cpu.branchPred.condPredicted 21757824 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1548941 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 13682195 # Number of BTB lookups
system.cpu.branchPred.BTBHits 12857487 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.branchPred.BTBHitPct 93.972400 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1522808 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 400 # Number of system calls
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.numCycles 162449690 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.fetch.icacheStallCycles 27167357 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 241462052 # Number of instructions fetch has processed
system.cpu.fetch.Branches 21757824 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 14380295 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 133204520 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3672137 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 11 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 3242 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 32817 # Number of stall cycles due to pending traps
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.fetch.IcacheWaitRetryStallCycles 121 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 26014450 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 320059 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 162244149 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.449323 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.349447 # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.fetch.rateDist::0 96544935 59.51% 59.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4966288 3.06% 62.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3924303 2.42% 64.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4589791 2.83% 67.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4444336 2.74% 70.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5042325 3.11% 73.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5076481 3.13% 76.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3889378 2.40% 79.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 33766312 20.81% 100.00% # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.fetch.rateDist::total 162244149 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.133936 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.486381 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 16503411 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96610290 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 25882430 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 21411950 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1836068 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 352729241 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1836068 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 24442767 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 33233774 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 31009 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 38303751 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 64396780 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 343252745 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1943 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 56953505 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7545423 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 167940 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 397342568 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 949709399 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 627052131 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4618257 # Number of floating rename lookups
stats: Bump x86 stats This patch bumps the x86 stats to reflect the recent fixes.
2013-06-24 20:17:22 +02:00
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.rename.UndoneMaps 137913118 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2151 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2060 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 120010907 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 87039709 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 31137080 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 61853756 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 20927707 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 331596276 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4834 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 264603975 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 77857 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 110237726 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 225639096 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3589 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 162244149 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.630900 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.539803 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.issued_per_cycle::0 42788422 26.37% 26.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 47622129 29.35% 55.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 33320454 20.54% 76.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18328192 11.30% 87.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 11302199 6.97% 94.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4922011 3.03% 97.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2609014 1.61% 99.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 930397 0.57% 99.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 421331 0.26% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.issued_per_cycle::total 162244149 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.fu_full::IntAlu 230632 7.18% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2590896 80.61% 87.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 392432 12.21% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 1211493 0.46% 0.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 165364025 62.49% 62.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 786761 0.30% 63.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7038559 2.66% 65.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1211557 0.46% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 66257169 25.04% 91.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 22734411 8.59% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iq.FU_type_0::total 264603975 # Type of FU issued
system.cpu.iq.rate 1.628836 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3213960 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012146 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 689757647 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 437892717 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 258330357 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4986269 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4261617 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2393080 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 264097165 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2509277 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18796485 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 30390155 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14027 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 322538 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 10621363 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 52082 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.iewSquashCycles 1836068 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 14114838 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 500285 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 331601110 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 108836 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 87039742 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 31137080 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2060 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 401860 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 61208 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 322538 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 680213 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 929259 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1609472 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 262268386 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 65330198 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2335589 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.exec_refs 87858182 # number of memory reference insts executed
system.cpu.iew.exec_branches 14520351 # Number of branches executed
system.cpu.iew.exec_stores 22527984 # Number of stores executed
system.cpu.iew.exec_rate 1.614459 # Inst execution rate
system.cpu.iew.wb_sent 261554043 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 260723437 # cumulative count of insts written-back
system.cpu.iew.wb_producers 208617070 # num instructions producing a value
system.cpu.iew.wb_consumers 375029707 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.iew.wb_rate 1.604949 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.556268 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.commitSquashedInsts 110244875 # The number of squashed insts skipped by commit
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.branchMispredicts 1552031 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 147195030 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.503878 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.943897 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.committed_per_cycle::0 47434016 32.23% 32.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 57618157 39.14% 71.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14262797 9.69% 81.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 11889308 8.08% 89.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4213027 2.86% 92.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2877009 1.95% 93.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 914800 0.62% 94.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1061572 0.72% 95.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6924344 4.70% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.committed_per_cycle::total 147195030 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 77165304 # Number of memory references committed
system.cpu.commit.loads 56649587 # Number of loads committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 12326938 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 797818 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.commit.bw_lim_events 6924344 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 471878945 # The number of ROB reads
system.cpu.rob.rob_writes 678308439 # The number of ROB writes
system.cpu.timesIdled 2694 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 205541 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.cpi 1.230016 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.230016 # CPI: Total CPI of All Threads
system.cpu.ipc 0.812998 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.812998 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 454025160 # number of integer regfile reads
system.cpu.int_regfile_writes 236935746 # number of integer regfile writes
system.cpu.fp_regfile_reads 3267968 # number of floating regfile reads
system.cpu.fp_regfile_writes 2053127 # number of floating regfile writes
system.cpu.cc_regfile_reads 102766500 # number of cc regfile reads
system.cpu.cc_regfile_writes 60037026 # number of cc regfile writes
system.cpu.misc_regfile_reads 135494920 # number of misc regfile reads
stats: Bump x86 stats This patch bumps the x86 stats to reflect the recent fixes.
2013-06-24 20:17:22 +02:00
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.tags.replacements 56 # number of replacements
system.cpu.dcache.tags.tagsinuse 1448.236298 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 66889390 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2008 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 33311.449203 # Average number of references to valid blocks.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 1448.236298 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.353573 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.353573 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1952 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 484 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1414 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.476562 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 133785736 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 133785736 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 46375033 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 46375033 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20513891 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20513891 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 66888924 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 66888924 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 66888924 # number of overall hits
system.cpu.dcache.overall_hits::total 66888924 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1100 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1100 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1840 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1840 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2940 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2940 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2940 # number of overall misses
system.cpu.dcache.overall_misses::total 2940 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 68941167 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 68941167 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 128874548 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 128874548 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 197815715 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 197815715 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 197815715 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 197815715 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 46376133 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 46376133 # number of ReadReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.demand_accesses::cpu.data 66891864 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 66891864 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 66891864 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 66891864 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62673.788182 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62673.788182 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70040.515217 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 70040.515217 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67284.256803 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67284.256803 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67284.256803 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67284.256803 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 82 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
system.cpu.dcache.writebacks::total 13 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1839 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1839 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2307 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2307 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2307 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2307 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36256250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36256250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125371702 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 125371702 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161627952 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 161627952 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161627952 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 161627952 # number of overall MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77470.619658 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77470.619658 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68173.845568 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68173.845568 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70059.797139 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70059.797139 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70059.797139 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70059.797139 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.tags.replacements 5865 # number of replacements
system.cpu.icache.tags.tagsinuse 1646.159130 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 26003921 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 7839 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3317.249777 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1646.159130 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.803789 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.803789 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1974 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 898 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 773 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.963867 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 52037036 # Number of tag accesses
system.cpu.icache.tags.data_accesses 52037036 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 26003921 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 26003921 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 26003921 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 26003921 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 26003921 # number of overall hits
system.cpu.icache.overall_hits::total 26003921 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 10528 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 10528 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 10528 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 10528 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 10528 # number of overall misses
system.cpu.icache.overall_misses::total 10528 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 430452747 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 430452747 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 430452747 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 430452747 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 430452747 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 430452747 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 26014449 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 26014449 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 26014449 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 26014449 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 26014449 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 26014449 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000405 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000405 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000405 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000405 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000405 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000405 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40886.469130 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 40886.469130 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 40886.469130 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 40886.469130 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 40886.469130 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 40886.469130 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1891 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 67.535714 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2389 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2389 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2389 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2389 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2389 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2389 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8139 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 8139 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 8139 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 8139 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 8139 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 8139 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322188751 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 322188751 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322188751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 322188751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322188751 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 322188751 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39585.790761 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39585.790761 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39585.790761 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 39585.790761 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39585.790761 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39585.790761 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.l2cache.tags.tagsinuse 2629.714027 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4366 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3947 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.106157 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 2.821104 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2311.277195 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 315.615728 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000086 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.070535 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.009632 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.080253 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3947 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1031 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2655 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120453 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 86769 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 86769 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 4327 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 35 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 4362 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 4327 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 43 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 4370 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 4327 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 43 # number of overall hits
system.cpu.l2cache.overall_hits::total 4370 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3513 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 432 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3945 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 298 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 298 # number of UpgradeReq misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 3513 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1965 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5478 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3513 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1965 # number of overall misses
system.cpu.l2cache.overall_misses::total 5478 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 268162500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35336500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 303499000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114204250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 114204250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 268162500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 149540750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 417703250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 268162500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 149540750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 417703250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 7840 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 467 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 8307 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 299 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 299 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 7840 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2008 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9848 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 7840 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2008 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9848 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448087 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.925054 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.474901 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996656 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996656 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994809 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994809 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.448087 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.978586 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.556255 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.448087 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.978586 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.556255 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76334.329633 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81797.453704 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76932.572877 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74497.227658 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74497.227658 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76334.329633 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76102.162850 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76251.049653 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76334.329633 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76102.162850 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76251.049653 # average overall miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3513 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 432 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3945 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 298 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 298 # number of UpgradeReq MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3513 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1965 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5478 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3513 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1965 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5478 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 224321500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29932000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 254253500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5280798 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5280798 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95023750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95023750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 224321500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124955750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 349277250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 224321500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124955750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 349277250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448087 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.925054 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.474901 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996656 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996656 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994809 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994809 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448087 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978586 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.556255 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448087 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978586 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.556255 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63854.682607 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69287.037037 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64449.556401 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17720.798658 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17720.798658 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61985.485975 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61985.485975 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63854.682607 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.712468 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63759.994524 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63854.682607 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.712468 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63759.994524 # average overall mshr miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 8606 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 8605 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15978 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4627 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 20605 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501696 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 631040 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 299 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 10459 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.toL2Bus.snoop_fanout::3 10459 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.toL2Bus.snoop_fanout::total 10459 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5242500 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 12871748 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 3552548 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.trans_dist::ReadReq 3944 # Transaction distribution
system.membus.trans_dist::ReadResp 3944 # Transaction distribution
system.membus.trans_dist::UpgradeReq 298 # Transaction distribution
system.membus.trans_dist::UpgradeResp 298 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 1533 # Transaction distribution
system.membus.trans_dist::ReadExResp 1533 # Transaction distribution
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11550 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11550 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11550 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350528 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350528 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 350528 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.snoop_fanout::samples 5775 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.snoop_fanout::0 5775 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.snoop_fanout::total 5775 # Request fanout histogram
system.membus.reqLayer0.occupancy 6990000 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: x86: updates due to change in div latency
2015-04-30 05:35:23 +02:00
system.membus.respLayer1.occupancy 29627952 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
X86: Add o3 regressions in SE mode. Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 09:16:09 +01:00
---------- End Simulation Statistics ----------
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