2008-11-10 06:57:15 +01:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 0.250987 # Number of seconds simulated
sim_ticks 250987138500 # Number of ticks simulated
final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-01-10 16:59:01 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-12-12 23:27:38 +01:00
host_inst_rate 309334 # Simulator instruction rate (inst/s)
host_op_rate 518472 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 587856087 # Simulator tick rate (ticks/s)
host_mem_usage 279244 # Number of bytes of host memory used
host_seconds 426.95 # Real time elapsed on the host
2012-08-15 16:38:05 +02:00
sim_insts 132071193 # Number of instructions simulated
2013-10-02 11:03:38 +02:00
sim_ops 221363385 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s)
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2012-01-10 16:59:01 +01:00
system.cpu.workload.num_syscalls 400 # Number of system calls
2015-11-06 09:26:50 +01:00
system.cpu.numCycles 501974277 # number of cpu cycles simulated
2012-01-10 16:59:01 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 132071193 # Number of instructions committed
2013-10-02 11:03:38 +02:00
system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
2013-10-16 16:44:12 +02:00
system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
2012-01-10 16:59:01 +01:00
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
2013-05-21 18:41:27 +02:00
system.cpu.num_func_calls 1595632 # number of times a function call or return occured
2012-08-15 16:38:05 +02:00
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
2013-10-16 16:44:12 +02:00
system.cpu.num_int_insts 219019986 # number of integer instructions
2012-01-10 16:59:01 +01:00
system.cpu.num_fp_insts 2162459 # number of float instructions
2013-10-16 16:44:12 +02:00
system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
2012-01-10 16:59:01 +01:00
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
2013-10-16 16:44:12 +02:00
system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
2013-03-11 23:45:09 +01:00
system.cpu.num_mem_refs 77165304 # number of memory refs
system.cpu.num_load_insts 56649587 # Number of load instructions
2012-12-30 19:45:52 +01:00
system.cpu.num_store_insts 20515717 # Number of store instructions
2014-10-20 23:48:19 +02:00
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
2015-11-06 09:26:50 +01:00
system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles
2014-10-20 23:48:19 +02:00
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
2014-02-16 18:40:34 +01:00
system.cpu.Branches 12326938 # Number of branches fetched
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
2014-09-01 23:55:52 +02:00
system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 221363385 # Class of executed instruction
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.replacements 41 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits
system.cpu.dcache.overall_hits::total 77195831 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
system.cpu.dcache.overall_misses::total 1905 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
system.cpu.dcache.writebacks::total 7 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles
2015-03-02 11:04:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
2015-03-02 11:04:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 2836 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use
2014-10-20 23:48:19 +02:00
system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
2014-10-20 23:48:19 +02:00
system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
2014-10-20 23:48:19 +02:00
system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits
system.cpu.icache.overall_hits::total 173489673 # number of overall hits
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
system.cpu.icache.overall_misses::total 4694 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles
2014-10-20 23:48:19 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency
2012-01-10 16:59:01 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-10 16:59:01 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 2836 # number of writebacks
system.cpu.icache.writebacks::total 2836 # number of writebacks
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
2012-01-10 16:59:01 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
system.cpu.l2cache.overall_hits::total 1864 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses)
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses)
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2012-01-10 16:59:01 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-10 16:59:01 +01:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
2008-11-10 06:57:15 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency
2012-01-10 16:59:01 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes)
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes)
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadResp 3160 # Transaction distribution
system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 4735 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 4735 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
2008-11-10 06:57:15 +01:00
---------- End Simulation Statistics ----------
