2009-04-18 16:42:29 +02:00
---------- Begin Simulation Statistics ----------
2016-04-08 18:01:45 +02:00
sim_seconds 0.000023 # Number of seconds simulated
sim_ticks 22532000 # Number of ticks simulated
final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-06-21 00:57:14 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-04-09 18:13:40 +02:00
host_inst_rate 106399 # Simulator instruction rate (inst/s)
host_op_rate 106364 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 479269632 # Simulator tick rate (ticks/s)
host_mem_usage 251364 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
2016-03-17 18:32:53 +01:00
sim_insts 4999 # Number of instructions simulated
sim_ops 4999 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-04-08 18:01:45 +02:00
system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory
2016-03-17 18:32:53 +01:00
system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory
2016-04-08 18:01:45 +02:00
system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory
2016-03-17 18:32:53 +01:00
system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory
2016-04-08 18:01:45 +02:00
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 934493165 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 397656666 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1332149831 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 934493165 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 934493165 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 934493165 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 397656666 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1332149831 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 469 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2016-04-08 18:01:45 +02:00
system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2016-04-08 18:01:45 +02:00
system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2016-04-08 18:01:45 +02:00
system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2014-10-20 23:48:19 +02:00
system.physmem.perBankRdBursts::0 29 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::1 0 # Per bank write bursts
system.physmem.perBankRdBursts::2 1 # Per bank write bursts
system.physmem.perBankRdBursts::3 0 # Per bank write bursts
system.physmem.perBankRdBursts::4 7 # Per bank write bursts
system.physmem.perBankRdBursts::5 3 # Per bank write bursts
system.physmem.perBankRdBursts::6 13 # Per bank write bursts
2014-10-20 23:48:19 +02:00
system.physmem.perBankRdBursts::7 53 # Per bank write bursts
system.physmem.perBankRdBursts::8 59 # Per bank write bursts
system.physmem.perBankRdBursts::9 76 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::10 43 # Per bank write bursts
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::11 21 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 51 # Per bank write bursts
system.physmem.perBankRdBursts::13 29 # Per bank write bursts
2016-03-17 18:32:53 +01:00
system.physmem.perBankRdBursts::14 77 # Per bank write bursts
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::15 7 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-04-08 18:01:45 +02:00
system.physmem.totGap 22446500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-04-08 18:01:45 +02:00
system.physmem.readPktSize::6 469 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2016-04-08 18:01:45 +02:00
system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2016-04-08 18:01:45 +02:00
system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 257.207547 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 176.154447 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 250.139569 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 32 30.19% 30.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 32 30.19% 60.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 19 17.92% 78.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 9 8.49% 86.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4 3.77% 90.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 1.89% 94.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6 5.66% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation
system.physmem.totQLat 4611250 # Total ticks spent queuing
system.physmem.totMemAccLat 13405000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9832.09 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-04-08 18:01:45 +02:00
system.physmem.avgMemAccLat 28582.09 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1332.15 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2016-04-08 18:01:45 +02:00
system.physmem.avgRdBWSys 1332.15 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-04-08 18:01:45 +02:00
system.physmem.busUtil 10.41 # Data bus utilization in percentage
system.physmem.busUtilRead 10.41 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2016-04-08 18:01:45 +02:00
system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2016-04-08 18:01:45 +02:00
system.physmem.readRowHits 353 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2016-04-08 18:01:45 +02:00
system.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2016-04-08 18:01:45 +02:00
system.physmem.avgGap 47860.34 # Average gap between requests
system.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined
2015-03-02 11:04:20 +01:00
system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_0.actBackEnergy 9591390 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1086000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 12431355 # Total energy per rank (pJ)
system.physmem_0.averagePower 785.179536 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2005750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-04-08 18:01:45 +02:00
system.physmem_0.memoryStateTime::ACT 13559250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-04-08 18:01:45 +02:00
system.physmem_1.actEnergy 529200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 288750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2176200 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ)
2015-07-03 16:15:03 +02:00
system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
2016-04-08 18:01:45 +02:00
system.physmem_1.totalEnergy 14828520 # Total energy per rank (pJ)
system.physmem_1.averagePower 936.587399 # Core power per rank (mW)
2015-07-03 16:15:03 +02:00
system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.lookups 2183 # Number of BP lookups
system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups
system.cpu.branchPred.BTBHits 587 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.BTBHitPct 32.996065 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 250 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 269 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 2 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 267 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2009-04-18 16:42:29 +02:00
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
2011-06-21 00:57:14 +02:00
system.cpu.dtb.read_accesses 0 # DTB read accesses
2009-04-18 16:42:29 +02:00
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
2011-06-21 00:57:14 +02:00
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
2014-10-20 23:48:19 +02:00
system.cpu.workload.num_syscalls 7 # Number of system calls
2016-04-08 18:01:45 +02:00
system.cpu.numCycles 45065 # number of cpu cycles simulated
2011-06-21 00:57:14 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-04-08 18:01:45 +02:00
system.cpu.fetch.icacheStallCycles 9068 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12986 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2183 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 4746 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing
2016-03-17 18:32:53 +01:00
system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps
2016-04-08 18:01:45 +02:00
system.cpu.fetch.CacheLines 2047 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 14454 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.898436 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.187928 # Number of instructions fetched each cycle (Total)
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-04-08 18:01:45 +02:00
system.cpu.fetch.rateDist::0 11097 76.77% 76.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1507 10.43% 87.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 110 0.76% 87.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 162 1.12% 89.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 279 1.93% 91.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 99 0.68% 91.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 140 0.97% 92.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 158 1.09% 93.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 902 6.24% 100.00% # Number of instructions fetched each cycle (Total)
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-04-08 18:01:45 +02:00
system.cpu.fetch.rateDist::total 14454 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.048441 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.288162 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8443 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 2703 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2773 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 182 # Number of times decode resolved a branch
2016-03-17 18:32:53 +01:00
system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction
2016-04-08 18:01:45 +02:00
system.cpu.decode.DecodedInsts 12006 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8593 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 592 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2745 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1156 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11571 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
2015-09-15 15:14:09 +02:00
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
2016-04-08 18:01:45 +02:00
system.cpu.rename.LQFullEvents 175 # Number of times rename has blocked due to LQ full
2015-07-03 16:15:03 +02:00
system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full
2016-04-08 18:01:45 +02:00
system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 13573 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13340 # Number of integer rename lookups
2013-10-16 16:44:12 +02:00
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
2016-03-17 18:32:53 +01:00
system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed
2016-04-08 18:01:45 +02:00
system.cpu.rename.UndoneMaps 3648 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 13 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2471 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads.
2014-10-20 23:48:19 +02:00
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
2016-04-08 18:01:45 +02:00
system.cpu.iq.iqInstsAdded 9030 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8122 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4040 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2024 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 14454 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.561921 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.290505 # Number of insts issued each cycle
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::0 11129 77.00% 77.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1334 9.23% 86.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 725 5.02% 91.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 461 3.19% 94.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 340 2.35% 96.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 284 1.96% 98.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 111 0.77% 99.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 51 0.35% 99.87% # Number of insts issued each cycle
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::total 14454 # Number of insts issued each cycle
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-04-08 18:01:45 +02:00
system.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 117 64.64% 68.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # attempts to use FU when none available
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.FU_type_0::IntAlu 4782 58.88% 58.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2272 27.97% 86.94% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.FU_type_0::total 8122 # Type of FU issued
system.cpu.iq.rate 0.180229 # Inst issue rate
system.cpu.iq.fu_busy_cnt 181 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.022285 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30894 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 13087 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7350 # Number of integer instruction queue wakeup accesses
2011-06-21 00:57:14 +02:00
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
2016-04-08 18:01:45 +02:00
system.cpu.iq.int_alu_accesses 8301 # Number of integer alu accesses
2011-06-21 00:57:14 +02:00
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1336 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
2014-06-22 23:33:09 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
2011-06-21 00:57:14 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10642 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2471 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewLSQFullEvents 57 # Number of times the LSQ has become full, causing a stall
2014-06-22 23:33:09 +02:00
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
2016-04-08 18:01:45 +02:00
system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 7800 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2128 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute
2011-06-21 00:57:14 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-04-08 18:01:45 +02:00
system.cpu.iew.exec_nop 1602 # number of nop insts executed
system.cpu.iew.exec_refs 3177 # number of memory reference insts executed
system.cpu.iew.exec_branches 1369 # Number of branches executed
system.cpu.iew.exec_stores 1049 # Number of stores executed
system.cpu.iew.exec_rate 0.173083 # Inst execution rate
system.cpu.iew.wb_sent 7447 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7352 # cumulative count of insts written-back
system.cpu.iew.wb_producers 2874 # num instructions producing a value
system.cpu.iew.wb_consumers 4285 # num instructions consuming a value
system.cpu.iew.wb_rate 0.163142 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.670712 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 4995 # The number of squashed insts skipped by commit
2014-10-20 23:48:19 +02:00
system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
2016-04-08 18:01:45 +02:00
system.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 13572 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.415561 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.228101 # Number of insts commited each cycle
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-04-08 18:01:45 +02:00
system.cpu.commit.committed_per_cycle::0 11381 83.86% 83.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 886 6.53% 90.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 519 3.82% 94.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 254 1.87% 96.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 162 1.19% 97.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 163 1.20% 98.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 62 0.46% 98.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 41 0.30% 99.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 104 0.77% 100.00% # Number of insts commited each cycle
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-04-08 18:01:45 +02:00
system.cpu.commit.committed_per_cycle::total 13572 # Number of insts commited each cycle
2016-03-17 18:32:53 +01:00
system.cpu.commit.committedInsts 5640 # Number of instructions committed
system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed
2011-06-21 00:57:14 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2016-03-17 18:32:53 +01:00
system.cpu.commit.refs 2036 # Number of memory references committed
system.cpu.commit.loads 1135 # Number of loads committed
2011-06-21 00:57:14 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2016-03-17 18:32:53 +01:00
system.cpu.commit.branches 886 # Number of branches committed
2011-06-21 00:57:14 +02:00
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
2016-03-17 18:32:53 +01:00
system.cpu.commit.int_insts 4955 # Number of committed integer instructions.
2014-10-20 23:48:19 +02:00
system.cpu.commit.function_calls 85 # Number of function calls committed.
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::No_OpClass 641 11.37% 11.37% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 2959 52.46% 63.83% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2 0.04% 63.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::total 5640 # Class of committed instruction
2016-04-08 18:01:45 +02:00
system.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 24090 # The number of ROB reads
system.cpu.rob.rob_writes 22160 # The number of ROB writes
system.cpu.timesIdled 263 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30611 # Total number of cycles that the CPU has spent unscheduled due to idling
2016-03-17 18:32:53 +01:00
system.cpu.committedInsts 4999 # Number of Instructions Simulated
system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated
2016-04-08 18:01:45 +02:00
system.cpu.cpi 9.014803 # CPI: Cycles Per Instruction
system.cpu.cpi_total 9.014803 # CPI: Total CPI of All Threads
system.cpu.ipc 0.110929 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.110929 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 10573 # number of integer regfile reads
system.cpu.int_regfile_writes 5151 # number of integer regfile writes
2011-06-21 00:57:14 +02:00
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
2016-03-17 18:32:53 +01:00
system.cpu.misc_regfile_reads 160 # number of misc regfile reads
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks.
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks.
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.avg_refs 17.092857 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 90.625823 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.022125 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.022125 # Average percentage of cache occupancy
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits
system.cpu.dcache.overall_hits::total 2393 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses
system.cpu.dcache.overall_misses::total 512 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11867500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11867500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24012499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 24012499 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35879999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35879999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35879999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35879999 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2004 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083333 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.083333 # miss rate for ReadReq accesses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.176248 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.176248 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.176248 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.176248 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71062.874251 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 71062.874251 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69601.446377 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69601.446377 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 70078.123047 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 70078.123047 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
2015-03-02 11:04:20 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 372 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 372 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 372 # number of overall MSHR hits
2016-03-17 18:32:53 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
2016-03-17 18:32:53 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7550000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7550000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4082999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4082999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11632999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11632999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11632999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11632999 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044910 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044910 # mshr miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.048193 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.048193 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 17 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.077529 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4426 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits
system.cpu.icache.overall_hits::total 1610 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
system.cpu.icache.overall_misses::total 437 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32774000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 32774000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 32774000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 32774000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 32774000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 32774000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2047 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2047 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2047 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2047 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2047 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2047 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213483 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.213483 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.213483 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.213483 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.213483 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.213483 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74997.711670 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 74997.711670 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 74997.711670 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 74997.711670 # average overall miss latency
2014-10-20 23:48:19 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014-10-20 23:48:19 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2014-10-20 23:48:19 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 17 # number of writebacks
system.cpu.icache.writebacks::total 17 # number of writebacks
2016-04-08 18:01:45 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26055500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 26055500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26055500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 26055500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26055500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 26055500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162189 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.162189 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
2011-06-21 00:57:14 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004905 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001748 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006653 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 329 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 329 # number of ReadCleanReq misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4007000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25524500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25524500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7412000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7412000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 25524500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11419000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 36943500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 25524500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11419000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 36943500 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses)
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses)
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990964 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990964 # miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80140 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80140 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77582.066869 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77582.066869 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82355.555556 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82355.555556 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78770.788913 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78770.788913 # average overall miss latency
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2014-10-20 23:48:19 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22234500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22234500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6512000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6512000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22234500 # number of demand (read+write) MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::total 32253500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22234500 # number of overall MSHR miss cycles
2016-04-09 18:13:40 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::total 32253500 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70140 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70140 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67582.066869 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67582.066869 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72355.555556 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72355.555556 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes)
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.membus.trans_dist::ReadResp 419 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::samples 469 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::total 469 # Request fanout histogram
system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.membus.respLayer1.occupancy 2494000 # Layer occupancy (ticks)
2015-09-15 15:14:09 +02:00
system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
2009-04-18 16:42:29 +02:00
---------- End Simulation Statistics ----------
