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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

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Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_seconds 2.903468 # Number of seconds simulated
sim_ticks 2903467553500 # Number of ticks simulated
final_tick 2903467553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
host_inst_rate 455888 # Simulator instruction rate (inst/s)
host_op_rate 549660 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 11767164312 # Simulator tick rate (ticks/s)
host_mem_usage 571472 # Number of bytes of host memory used
host_seconds 246.74 # Real time elapsed on the host
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_insts 112487279 # Number of instructions simulated
sim_ops 135624752 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu.inst 1189412 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9042916 # Number of bytes read from this memory
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::total 10233864 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1189412 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1189412 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7647616 # Number of bytes written to this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_written::total 7665140 # Number of bytes written to this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::cpu.inst 27038 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141815 # Number of read requests responded to by this memory
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::total 168877 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 119494 # Number of write requests responded to by this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_writes::total 123875 # Number of write requests responded to by this memory
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_read::cpu.inst 409652 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3114523 # Total read bandwidth from this memory (bytes/s)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_read::total 3524704 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 409652 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 409652 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2633960 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6036 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2639995 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2633960 # Total bandwidth to/from this memory (bytes/s)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_total::cpu.inst 409652 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3120558 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bw_total::total 6164699 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 168877 # Number of read requests accepted
system.physmem.writeReqs 123875 # Number of write requests accepted
system.physmem.readBursts 168877 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 123875 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10799552 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue
system.physmem.bytesWritten 7677760 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10233864 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7665140 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10018 # Per bank write bursts
system.physmem.perBankRdBursts::1 9658 # Per bank write bursts
system.physmem.perBankRdBursts::2 10300 # Per bank write bursts
system.physmem.perBankRdBursts::3 9945 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::4 18863 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.perBankRdBursts::5 10091 # Per bank write bursts
system.physmem.perBankRdBursts::6 10302 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::7 10601 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.perBankRdBursts::8 9921 # Per bank write bursts
system.physmem.perBankRdBursts::9 10207 # Per bank write bursts
system.physmem.perBankRdBursts::10 9962 # Per bank write bursts
system.physmem.perBankRdBursts::11 9026 # Per bank write bursts
system.physmem.perBankRdBursts::12 9868 # Per bank write bursts
system.physmem.perBankRdBursts::13 10473 # Per bank write bursts
system.physmem.perBankRdBursts::14 9981 # Per bank write bursts
system.physmem.perBankRdBursts::15 9527 # Per bank write bursts
system.physmem.perBankWrBursts::0 7412 # Per bank write bursts
system.physmem.perBankWrBursts::1 7255 # Per bank write bursts
system.physmem.perBankWrBursts::2 8123 # Per bank write bursts
system.physmem.perBankWrBursts::3 7537 # Per bank write bursts
system.physmem.perBankWrBursts::4 7355 # Per bank write bursts
system.physmem.perBankWrBursts::5 7348 # Per bank write bursts
system.physmem.perBankWrBursts::6 7577 # Per bank write bursts
system.physmem.perBankWrBursts::7 7905 # Per bank write bursts
system.physmem.perBankWrBursts::8 7603 # Per bank write bursts
system.physmem.perBankWrBursts::9 7853 # Per bank write bursts
system.physmem.perBankWrBursts::10 7551 # Per bank write bursts
system.physmem.perBankWrBursts::11 6940 # Per bank write bursts
system.physmem.perBankWrBursts::12 7397 # Per bank write bursts
system.physmem.perBankWrBursts::13 7831 # Per bank write bursts
system.physmem.perBankWrBursts::14 7359 # Per bank write bursts
system.physmem.perBankWrBursts::15 6919 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
system.physmem.totGap 2903467231500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readPktSize::6 159305 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.writePktSize::6 119494 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 167939 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::15 2082 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6509 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6471 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7455 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7725 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8939 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 7789 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6945 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 59281 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 311.689209 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 183.095727 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 332.740944 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 21592 36.42% 36.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 15113 25.49% 61.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5696 9.61% 71.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3272 5.52% 77.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2400 4.05% 81.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1627 2.74% 83.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1059 1.79% 85.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 986 1.66% 87.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7536 12.71% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 59281 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5916 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.520960 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 582.774923 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 5915 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5916 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5916 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.278059 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.578317 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.228760 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5122 86.58% 86.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 35 0.59% 87.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 194 3.28% 90.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 61 1.03% 91.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 61 1.03% 92.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 181 3.06% 95.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 14 0.24% 95.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 5 0.08% 95.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 7 0.12% 96.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 5 0.08% 96.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 5 0.08% 96.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 7 0.12% 96.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 163 2.76% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 2 0.03% 99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 7 0.12% 99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 6 0.10% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 4 0.07% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.03% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.03% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 17 0.29% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 3 0.05% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 3 0.05% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5916 # Writes before turning the bus around for reads
system.physmem.totQLat 1515248250 # Total ticks spent queuing
system.physmem.totMemAccLat 4679179500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 843715000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8979.62 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgMemAccLat 27729.62 # Average memory access latency per DRAM burst
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgWrQLen 27.93 # Average write queue length when enqueuing
system.physmem.readRowHits 138696 # Number of row buffer hits during reads
system.physmem.writeRowHits 90730 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.62 # Row buffer hit rate for writes
system.physmem.avgGap 9917839.10 # Average gap between requests
system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 229068000 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 124987500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 700268400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 392117760 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 87025634640 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1665738759750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1943850825810 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.494214 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2770947478500 # Time in different power states
system.physmem_0.memoryStateTime::REF 96952960000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_0.memoryStateTime::ACT 35561301500 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.actEnergy 219096360 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 119546625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 615919200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 385255440 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 85786607970 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1666825625250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1943592040605 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.405084 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2772773591250 # Time in different power states
system.physmem_1.memoryStateTime::REF 96952960000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.memoryStateTime::ACT 33740904250 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
tests: Update stats no match. Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-11-03 17:14:42 +01:00
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.walker.walks 9548 # Table walker walks requested
system.cpu.dtb.walker.walksShort 9548 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1269 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8279 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples 9548 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0 9548 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 9548 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 7384 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 11763.949079 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 9756.046308 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 7392.958780 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383 5809 78.67% 78.67% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767 1570 21.26% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 7384 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 925393500 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 925393500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 925393500 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6162 83.45% 83.45% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1222 16.55% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7384 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9548 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9548 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7384 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7384 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 16932 # Table walker requests started/completed, data/inst
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.read_hits 24527083 # DTB read hits
system.cpu.dtb.read_misses 8134 # DTB read misses
system.cpu.dtb.write_hits 19611642 # DTB write hits
system.cpu.dtb.write_misses 1414 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.prefetch_faults 1680 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.read_accesses 24535217 # DTB read accesses
system.cpu.dtb.write_accesses 19613056 # DTB write accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.hits 44138725 # DTB hits
system.cpu.dtb.misses 9548 # DTB misses
system.cpu.dtb.accesses 44148273 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 4762 # Table walker walks requested
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.walker.walkCompletionTime::mean 11752.816221 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 9620.437143 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 7446.323545 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191 1417 45.61% 45.61% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383 1012 32.57% 78.18% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575 676 21.76% 99.94% # Table walker service (enqueue to completion) latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.inst_hits 115585268 # ITB inst hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.itb.inst_misses 4762 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.inst_accesses 115590030 # ITB inst accesses
system.cpu.itb.hits 115585268 # DTB hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.itb.misses 4762 # DTB misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.accesses 115590030 # DTB accesses
system.cpu.numCycles 5806935107 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.committedInsts 112487279 # Number of instructions committed
system.cpu.committedOps 135624752 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 119926396 # Number of integer alu accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.num_func_calls 9895067 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15234125 # number of instructions that are conditional controls
system.cpu.num_int_insts 119926396 # number of integer instructions
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.num_fp_insts 11161 # number of float instructions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.num_int_register_reads 218121828 # number of times the integer registers were read
system.cpu.num_int_register_writes 82669566 # number of times the integer registers were written
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.num_cc_register_reads 489877250 # number of times the CC registers were read
system.cpu.num_cc_register_writes 51907763 # number of times the CC registers were written
system.cpu.num_mem_refs 45420046 # number of memory refs
system.cpu.num_load_insts 24850080 # Number of load instructions
system.cpu.num_store_insts 20569966 # Number of store instructions
system.cpu.num_idle_cycles 5385437399.888144 # Number of idle cycles
system.cpu.num_busy_cycles 421497707.111855 # Number of busy cycles
system.cpu.not_idle_fraction 0.072585 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.927415 # Percentage of idle cycles
system.cpu.Branches 25923230 # Number of branches fetched
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.op_class::IntAlu 93200379 67.17% 67.18% # Class of executed instruction
system.cpu.op_class::IntMult 114573 0.08% 67.26% # Class of executed instruction
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Class of executed instruction
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.op_class::MemRead 24850080 17.91% 85.17% # Class of executed instruction
system.cpu.op_class::MemWrite 20569966 14.83% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.op_class::total 138745790 # Class of executed instruction
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.kern.inst.quiesce 3030 # number of quiesce instructions executed
system.cpu.dcache.tags.replacements 820821 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.829842 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 43246183 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 821333 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 52.653653 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.829842 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999668 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.tag_accesses 177159261 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 177159261 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23117842 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23117842 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18828857 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18828857 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 392869 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 392869 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443457 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 443457 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460420 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460420 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 41946699 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41946699 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42339568 # number of overall hits
system.cpu.dcache.overall_hits::total 42339568 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 401262 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 401262 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 298702 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 298702 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 118314 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 118314 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22748 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22748 # number of LoadLockedReq misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_misses::cpu.data 699964 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 699964 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 818278 # number of overall misses
system.cpu.dcache.overall_misses::total 818278 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5968529500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5968529500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12574790000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12574790000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 282012000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 282012000 # number of LoadLockedReq miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 18543319500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18543319500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18543319500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18543319500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23519104 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23519104 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19127559 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19127559 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511183 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511183 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466205 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 466205 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460422 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460422 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42646663 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42646663 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43157846 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43157846 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.017061 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015616 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015616 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231451 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.231451 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048794 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048794 # miss rate for LoadLockedReq accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.016413 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016413 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.018960 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.018960 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14874.395034 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14874.395034 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42098.111161 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42098.111161 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12397.221734 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12397.221734 # average LoadLockedReq miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26491.818865 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26491.818865 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22661.393194 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22661.393194 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.writebacks::writebacks 682374 # number of writebacks
system.cpu.dcache.writebacks::total 682374 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14211 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14211 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400582 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 400582 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298702 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 298702 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116284 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 116284 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8537 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8537 # number of LoadLockedReq MSHR misses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 699284 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 699284 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 815568 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 815568 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31142 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31142 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27594 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58736 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58736 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5554957000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5554957000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12276088000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12276088000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1529661500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1529661500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110084000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110084000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17831045000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 17831045000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19360706500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 19360706500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5907914500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5907914500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4572592500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4572592500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10480507000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10480507000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017032 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017032 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015616 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015616 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227480 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227480 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018312 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018312 # mshr miss rate for LoadLockedReq accesses
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016397 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016397 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018897 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.018897 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13867.215701 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13867.215701 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41098.111161 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41098.111161 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13154.531148 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13154.531148 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12894.927961 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12894.927961 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25499.003266 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25499.003266 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23738.923670 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23738.923670 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189708.897951 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189708.897951 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165709.665145 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165709.665145 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178434.128984 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178434.128984 # average overall mshr uncacheable latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.replacements 1698833 # number of replacements
system.cpu.icache.tags.tagsinuse 510.737457 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 113885917 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1699345 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 67.017537 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 25666177500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.737457 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997534 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997534 # Average percentage of cache occupancy
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.tag_accesses 117284619 # Number of tag accesses
system.cpu.icache.tags.data_accesses 117284619 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 113885917 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 113885917 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 113885917 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 113885917 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 113885917 # number of overall hits
system.cpu.icache.overall_hits::total 113885917 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1699351 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1699351 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1699351 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1699351 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1699351 # number of overall misses
system.cpu.icache.overall_misses::total 1699351 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23351891000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 23351891000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 23351891000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 23351891000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 23351891000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 23351891000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 115585268 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 115585268 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 115585268 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 115585268 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 115585268 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 115585268 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014702 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014702 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014702 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014702 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014702 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014702 # miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.652549 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13741.652549 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.652549 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13741.652549 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.652549 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13741.652549 # average overall miss latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699351 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1699351 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1699351 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1699351 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1699351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1699351 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21652540000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 21652540000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21652540000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 21652540000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21652540000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 21652540000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 676974000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 676974000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 676974000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 676974000 # number of overall MSHR uncacheable cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12741.652549 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12741.652549 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12741.652549 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12741.652549 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12741.652549 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12741.652549 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75035.912215 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75035.912215 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.replacements 89784 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64924.949267 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4551273 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 155017 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 29.359832 # Average number of references to valid blocks.
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 50366.375395 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.807733 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012270 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9623.804573 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 4930.949297 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.768530 # Average percentage of cache occupancy
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146848 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.075240 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.990676 # Average percentage of cache occupancy
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65228 # Occupied blocks per task id
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2130 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56095 # Occupied blocks per task id
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.tag_accesses 40578005 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40578005 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6930 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3595 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 10525 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 682374 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 682374 # number of Writeback hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 164955 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 164955 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681308 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1681308 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513083 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 513083 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6930 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3595 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1681308 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 678038 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2369871 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6930 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3595 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1681308 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 678038 # number of overall hits
system.cpu.l2cache.overall_hits::total 2369871 # number of overall hits
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2713 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2713 # number of UpgradeReq misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 131011 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 131011 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18023 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 18023 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12320 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 12320 # number of ReadSharedReq misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 18023 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143331 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 161363 # number of demand (read+write) misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 18023 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143331 # number of overall misses
system.cpu.l2cache.overall_misses::total 161363 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 592500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 166000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 758500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 523000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 523000 # number of UpgradeReq miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10012178500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 10012178500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1443290000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1443290000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1018929500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1018929500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 592500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 166000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1443290000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11031108000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 12475156500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 592500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 166000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1443290000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11031108000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 12475156500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6937 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3597 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 10534 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 682374 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 682374 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2736 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2736 # number of UpgradeReq accesses(hits+misses)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 295966 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 295966 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699331 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1699331 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525403 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 525403 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6937 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3597 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1699331 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 821369 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2531234 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6937 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3597 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1699331 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 821369 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2531234 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001009 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000854 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991594 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991594 # miss rate for UpgradeReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442656 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.442656 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010606 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010606 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023449 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023449 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001009 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010606 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.174503 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063749 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001009 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010606 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.174503 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063749 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84642.857143 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84277.777778 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 192.775525 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 192.775525 # average UpgradeReq miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76422.426361 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76422.426361 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80080.452755 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80080.452755 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82705.316558 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82705.316558 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84642.857143 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80080.452755 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76962.471482 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77311.133903 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84642.857143 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80080.452755 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76962.471482 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77311.133903 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.writebacks::writebacks 83304 # number of writebacks
system.cpu.l2cache.writebacks::total 83304 # number of writebacks
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2713 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2713 # number of UpgradeReq MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131011 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 131011 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 18023 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 18023 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12320 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12320 # number of ReadSharedReq MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 18023 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143331 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 161363 # number of demand (read+write) MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 18023 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143331 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 161363 # number of overall MSHR misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31142 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40164 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27594 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58736 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67758 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 522500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 146000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 668500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 56418000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 56418000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8702068500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8702068500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1263060000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1263060000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 895729500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 895729500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 522500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 146000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1263060000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9597798000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 10861526500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 522500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 146000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1263060000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9597798000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 10861526500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 564199000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5518638500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6082837500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4255261500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4255261500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 564199000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9773900000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10338099000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000854 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991594 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991594 # mshr miss rate for UpgradeReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442656 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442656 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010606 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023449 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023449 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063749 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063749 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74277.777778 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20795.429414 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20795.429414 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66422.426361 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66422.426361 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70080.452755 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70080.452755 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72705.316558 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72705.316558 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177208.865840 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 151449.992531 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154209.665145 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154209.665145 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166403.909017 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 152573.851058 # average overall mshr uncacheable latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 67206 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2292179 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 801878 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 1805693 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2736 # Transaction distribution
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 2738 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 295966 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 295966 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699351 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 525637 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084414 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2579570 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12812 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24764 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7701560 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108793272 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96436737 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14388 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27748 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 205272145 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 179423 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 5300588 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.035792 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.185771 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::1 5110870 96.42% 96.42% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 189718 3.58% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::total 5300588 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3265127000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 2558048500 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 1278361999 # Layer occupancy (ticks)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 17827000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer27.occupancy 187438974 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.replacements 36424 # number of replacements
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.tagsinuse 1.134160 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.warmup_cycle 299040065000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.134160 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.070885 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.070885 # Average percentage of cache occupancy
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
system.iocache.tags.data_accesses 328122 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 234 # number of overall misses
system.iocache.overall_misses::total 234 # number of overall misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4271537097 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4271537097 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117920.083287 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 117920.083287 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460337097 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2460337097 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
tests: Update regressions for the new kernels and various preceeding fixes.
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67920.083287 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67920.083287 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadReq 40164 # Transaction distribution
system.membus.trans_dist::ReadResp 70750 # Transaction distribution
system.membus.trans_dist::WriteReq 27594 # Transaction distribution
system.membus.trans_dist::WriteResp 27594 # Transaction distribution
system.membus.trans_dist::Writeback 119494 # Transaction distribution
system.membus.trans_dist::CleanEvict 6493 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution
system.membus.trans_dist::ReadExReq 129215 # Transaction distribution
system.membus.trans_dist::ReadExResp 129215 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 30586 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445567 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553177 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 662077 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15581884 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15745273 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 18062393 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoops 498 # Total snoops (count)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::samples 394512 # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::1 394512 100.00% 100.00% # Request fanout histogram
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::total 394512 # Request fanout histogram
system.membus.reqLayer0.occupancy 90495000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.reqLayer5.occupancy 834776313 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer2.occupancy 964479239 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer3.occupancy 64484992 # Layer occupancy (ticks)
stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- End Simulation Statistics ----------
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