2011-04-25 23:18:08 +02:00
---------- Begin Simulation Statistics ----------
2016-03-17 18:32:53 +01:00
sim_seconds 0.404912 # Number of seconds simulated
sim_ticks 404911731500 # Number of ticks simulated
final_tick 404911731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-04-25 23:18:08 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-03-17 18:32:53 +01:00
host_inst_rate 59948 # Simulator instruction rate (inst/s)
host_op_rate 110933 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29356650 # Simulator tick rate (ticks/s)
host_mem_usage 419644 # Number of bytes of host memory used
host_seconds 13792.85 # Real time elapsed on the host
sim_insts 826847303 # Number of instructions simulated
sim_ops 1530082520 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-03-17 18:32:53 +01:00
system.physmem.bytes_read::cpu.inst 162176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24538048 # Number of bytes read from this memory
system.physmem.bytes_read::total 24700224 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 162176 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 162176 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18887104 # Number of bytes written to this memory
system.physmem.bytes_written::total 18887104 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2534 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 383407 # Number of read requests responded to by this memory
system.physmem.num_reads::total 385941 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 295111 # Number of write requests responded to by this memory
system.physmem.num_writes::total 295111 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 400522 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 60600981 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 61001502 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 400522 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 400522 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 46644991 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 46644991 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 46644991 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 400522 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 60600981 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 107646493 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 385941 # Number of read requests accepted
system.physmem.writeReqs 295111 # Number of write requests accepted
system.physmem.readBursts 385941 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 295111 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 24680320 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue
system.physmem.bytesWritten 18885056 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 24700224 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18887104 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-03-17 18:32:53 +01:00
system.physmem.perBankRdBursts::0 24031 # Per bank write bursts
system.physmem.perBankRdBursts::1 26423 # Per bank write bursts
system.physmem.perBankRdBursts::2 24936 # Per bank write bursts
system.physmem.perBankRdBursts::3 24514 # Per bank write bursts
system.physmem.perBankRdBursts::4 23470 # Per bank write bursts
system.physmem.perBankRdBursts::5 23659 # Per bank write bursts
system.physmem.perBankRdBursts::6 24566 # Per bank write bursts
system.physmem.perBankRdBursts::7 24334 # Per bank write bursts
system.physmem.perBankRdBursts::8 23673 # Per bank write bursts
system.physmem.perBankRdBursts::9 23472 # Per bank write bursts
system.physmem.perBankRdBursts::10 24737 # Per bank write bursts
system.physmem.perBankRdBursts::11 23939 # Per bank write bursts
system.physmem.perBankRdBursts::12 23178 # Per bank write bursts
system.physmem.perBankRdBursts::13 22917 # Per bank write bursts
system.physmem.perBankRdBursts::14 23861 # Per bank write bursts
system.physmem.perBankRdBursts::15 23920 # Per bank write bursts
system.physmem.perBankWrBursts::0 18617 # Per bank write bursts
system.physmem.perBankWrBursts::1 19947 # Per bank write bursts
system.physmem.perBankWrBursts::2 19213 # Per bank write bursts
system.physmem.perBankWrBursts::3 19024 # Per bank write bursts
system.physmem.perBankWrBursts::4 18187 # Per bank write bursts
system.physmem.perBankWrBursts::5 18473 # Per bank write bursts
system.physmem.perBankWrBursts::6 19133 # Per bank write bursts
system.physmem.perBankWrBursts::7 19079 # Per bank write bursts
system.physmem.perBankWrBursts::8 18679 # Per bank write bursts
system.physmem.perBankWrBursts::9 17947 # Per bank write bursts
system.physmem.perBankWrBursts::10 18901 # Per bank write bursts
system.physmem.perBankWrBursts::11 17752 # Per bank write bursts
system.physmem.perBankWrBursts::12 17391 # Per bank write bursts
system.physmem.perBankWrBursts::13 17019 # Per bank write bursts
system.physmem.perBankWrBursts::14 17841 # Per bank write bursts
system.physmem.perBankWrBursts::15 17876 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2013-11-27 00:05:25 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-03-17 18:32:53 +01:00
system.physmem.totGap 404911622500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-03-17 18:32:53 +01:00
system.physmem.readPktSize::6 385941 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-03-17 18:32:53 +01:00
system.physmem.writePktSize::6 295111 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 380814 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4468 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 307 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
2013-03-28 00:36:21 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-03-17 18:32:53 +01:00
system.physmem.wrQLenPdf::15 6167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6528 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 16966 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 17552 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 17613 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 17658 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17689 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17680 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 17711 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17661 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 17715 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 17693 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17771 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 17868 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17615 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 17553 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
2016-03-17 18:32:53 +01:00
system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see
2015-12-02 15:58:24 +01:00
system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
2016-03-17 18:32:53 +01:00
system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 3 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
2016-03-17 18:32:53 +01:00
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2016-03-17 18:32:53 +01:00
system.physmem.bytesPerActivate::samples 147028 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 296.294039 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 174.908610 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 323.351914 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 54375 36.98% 36.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 40100 27.27% 64.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 13677 9.30% 73.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7439 5.06% 78.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5510 3.75% 82.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3768 2.56% 84.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3010 2.05% 86.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2924 1.99% 88.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16225 11.04% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 147028 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17521 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 22.008789 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 217.166856 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 17511 99.94% 99.94% # Reads before turning the bus around for writes
2015-11-16 12:08:57 +01:00
system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes
2016-03-17 18:32:53 +01:00
system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes
2014-06-22 23:33:09 +02:00
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
2016-03-17 18:32:53 +01:00
system.physmem.rdPerTurnAround::total 17521 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17521 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.841447 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.770042 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.569197 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 17331 98.92% 98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 134 0.76% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 31 0.18% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 4 0.02% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 4 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 2 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads
2015-09-25 13:27:03 +02:00
system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads
2016-03-17 18:32:53 +01:00
system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 17521 # Writes before turning the bus around for reads
system.physmem.totQLat 4288044250 # Total ticks spent queuing
system.physmem.totMemAccLat 11518606750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1928150000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11119.58 # Average queueing delay per DRAM burst
2015-04-30 05:35:23 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-03-17 18:32:53 +01:00
system.physmem.avgMemAccLat 29869.58 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 60.95 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 46.64 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 61.00 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 46.64 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-09-15 15:14:09 +02:00
system.physmem.busUtil 0.84 # Data bus utilization in percentage
system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads
2016-03-17 18:32:53 +01:00
system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
2015-09-15 15:14:09 +02:00
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
2016-03-17 18:32:53 +01:00
system.physmem.avgWrQLen 21.53 # Average write queue length when enqueuing
system.physmem.readRowHits 317942 # Number of row buffer hits during reads
system.physmem.writeRowHits 215725 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.10 # Row buffer hit rate for writes
system.physmem.avgGap 594538.48 # Average gap between requests
system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 570719520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 311404500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1528168200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 982685520 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 26446645680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 62100381375 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 188471152500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 280411157295 # Total energy per rank (pJ)
system.physmem_0.averagePower 692.529485 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 312985847250 # Time in different power states
system.physmem_0.memoryStateTime::REF 13520780000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-03-17 18:32:53 +01:00
system.physmem_0.memoryStateTime::ACT 78402005250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-03-17 18:32:53 +01:00
system.physmem_1.actEnergy 540562680 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 294949875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1479324600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 929082960 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 26446645680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 59763827970 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 190520760750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 279975154515 # Total energy per rank (pJ)
system.physmem_1.averagePower 691.452692 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 316410940750 # Time in different power states
system.physmem_1.memoryStateTime::REF 13520780000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-03-17 18:32:53 +01:00
system.physmem_1.memoryStateTime::ACT 74976935500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-03-17 18:32:53 +01:00
system.cpu.branchPred.lookups 219859048 # Number of BP lookups
system.cpu.branchPred.condPredicted 219859048 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 8758546 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 124148256 # Number of BTB lookups
system.cpu.branchPred.BTBHits 121897688 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-03-17 18:32:53 +01:00
system.cpu.branchPred.BTBHitPct 98.187193 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 27156156 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1403906 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 551 # Number of system calls
2016-03-17 18:32:53 +01:00
system.cpu.numCycles 809823464 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-03-17 18:32:53 +01:00
system.cpu.fetch.icacheStallCycles 176591288 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1214997993 # Number of instructions fetch has processed
system.cpu.fetch.Branches 219859048 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 149053844 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 622702021 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 18219345 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 230 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 91157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 715943 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 449274 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 171574494 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2309765 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 809659613 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.796039 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.371227 # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-03-17 18:32:53 +01:00
system.cpu.fetch.rateDist::0 417404830 51.55% 51.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 32671589 4.04% 55.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 32039233 3.96% 59.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 32726753 4.04% 63.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 26705475 3.30% 66.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 26911183 3.32% 70.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 35262840 4.36% 74.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 31547344 3.90% 78.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 174390366 21.54% 100.00% # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-03-17 18:32:53 +01:00
system.cpu.fetch.rateDist::total 809659613 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.271490 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.500325 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 121391489 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 370091708 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 226645475 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 82421269 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 9109672 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2145160206 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 9109672 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 153539670 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 151301355 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 41989 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 272974154 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 222692773 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2099917751 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 135565 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 138360760 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 24932221 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 49265464 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 2208208417 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5316744595 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3383996279 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 60226 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 591246845 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3675 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 3497 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 423124310 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 508481889 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 201115971 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 229749012 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 68249944 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2031398692 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 54143 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1792547451 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 420919 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 501370315 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 849083500 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 53591 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 809659613 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.213952 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.069729 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-03-17 18:32:53 +01:00
system.cpu.iq.issued_per_cycle::0 239429764 29.57% 29.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 124356019 15.36% 44.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 119082530 14.71% 59.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 108043901 13.34% 72.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 89929088 11.11% 84.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 60282735 7.45% 91.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 42261465 5.22% 96.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 18997036 2.35% 99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 7277075 0.90% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-03-17 18:32:53 +01:00
system.cpu.iq.issued_per_cycle::total 809659613 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-03-17 18:32:53 +01:00
system.cpu.iq.fu_full::IntAlu 11520020 42.79% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 12317290 45.76% 88.55% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 3082634 11.45% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-03-17 18:32:53 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2934339 0.16% 0.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1185141409 66.11% 66.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 369471 0.02% 66.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 4797462 0.27% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 190 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 20 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 21 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 479 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 428879813 23.93% 90.49% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170424247 9.51% 100.00% # Type of FU issued
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-03-17 18:32:53 +01:00
system.cpu.iq.FU_type_0::total 1792547451 # Type of FU issued
system.cpu.iq.rate 2.213504 # Inst issue rate
system.cpu.iq.fu_busy_cnt 26919944 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.015018 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4422066274 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2533070112 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1765468749 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 29104 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 69216 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 5504 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1816520301 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 12755 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 185916260 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-03-17 18:32:53 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 124400743 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 210576 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 369684 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 51957776 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-03-17 18:32:53 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 22915 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1100 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-03-17 18:32:53 +01:00
system.cpu.iew.iewSquashCycles 9109672 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 98354510 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 6118608 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2031452835 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 404669 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 508484056 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 201115971 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 41229 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1818362 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3401419 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 369684 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4846207 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4373880 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 9220087 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1773318465 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 423351838 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 19228986 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
2016-03-17 18:32:53 +01:00
system.cpu.iew.exec_refs 590572450 # number of memory reference insts executed
system.cpu.iew.exec_branches 169222012 # Number of branches executed
system.cpu.iew.exec_stores 167220612 # Number of stores executed
system.cpu.iew.exec_rate 2.189759 # Inst execution rate
system.cpu.iew.wb_sent 1769957940 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1765474253 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1342270213 # num instructions producing a value
system.cpu.iew.wb_consumers 2056372436 # num instructions consuming a value
system.cpu.iew.wb_rate 2.180073 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.652737 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 501430525 # The number of squashed insts skipped by commit
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
2016-03-17 18:32:53 +01:00
system.cpu.commit.branchMispredicts 8839580 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 741419902 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.063719 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.574359 # Number of insts commited each cycle
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-03-17 18:32:53 +01:00
system.cpu.commit.committed_per_cycle::0 276552385 37.30% 37.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 172772725 23.30% 60.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 55960386 7.55% 68.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 86390933 11.65% 79.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 25906280 3.49% 83.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 26508569 3.58% 86.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 9812132 1.32% 88.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 8956469 1.21% 89.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 78560023 10.60% 100.00% # Number of insts commited each cycle
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-03-17 18:32:53 +01:00
system.cpu.commit.committed_per_cycle::total 741419902 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826847303 # Number of instructions committed
system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2016-03-17 18:32:53 +01:00
system.cpu.commit.refs 533241508 # Number of memory references committed
system.cpu.commit.loads 384083313 # Number of loads committed
2011-04-25 23:18:08 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2016-03-17 18:32:53 +01:00
system.cpu.commit.branches 149981740 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
2016-03-17 18:32:53 +01:00
system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction
system.cpu.commit.bw_lim_events 78560023 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 2694372924 # The number of ROB reads
system.cpu.rob.rob_writes 4131439321 # The number of ROB writes
system.cpu.timesIdled 2207 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 163851 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826847303 # Number of Instructions Simulated
system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.979411 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.979411 # CPI: Total CPI of All Threads
system.cpu.ipc 1.021022 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.021022 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2730823256 # number of integer regfile reads
system.cpu.int_regfile_writes 1440512155 # number of integer regfile writes
system.cpu.fp_regfile_reads 5926 # number of floating regfile reads
system.cpu.fp_regfile_writes 463 # number of floating regfile writes
system.cpu.cc_regfile_reads 599968810 # number of cc regfile reads
system.cpu.cc_regfile_writes 405913106 # number of cc regfile writes
system.cpu.misc_regfile_reads 971975039 # number of misc regfile reads
2013-03-11 23:45:09 +01:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.replacements 2532888 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.837732 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 382237058 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2536984 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 150.665932 # Average number of references to valid blocks.
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit.
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.837732 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.998007 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998007 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
2016-03-16 21:03:49 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.tag_accesses 773578930 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 773578930 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 233596304 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 233596304 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148199808 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148199808 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 381796112 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 381796112 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 381796112 # number of overall hits
system.cpu.dcache.overall_hits::total 381796112 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2766458 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2766458 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 958403 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 958403 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3724861 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3724861 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3724861 # number of overall misses
system.cpu.dcache.overall_misses::total 3724861 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 58572979000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 58572979000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 29883028996 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 29883028996 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 88456007996 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 88456007996 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 88456007996 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 88456007996 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 236362762 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 236362762 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 385520973 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 385520973 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 385520973 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 385520973 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011704 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.011704 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006425 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006425 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009662 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009662 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009662 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009662 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21172.553135 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21172.553135 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31180.024474 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31180.024474 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23747.465475 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23747.465475 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23747.465475 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23747.465475 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 9959 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1047 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.511939 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2016-03-17 18:32:53 +01:00
system.cpu.dcache.writebacks::writebacks 2332013 # number of writebacks
system.cpu.dcache.writebacks::total 2332013 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999668 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 999668 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19404 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 19404 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1019072 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1019072 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1019072 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1019072 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766790 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1766790 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 938999 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 938999 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2705789 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2705789 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2705789 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2705789 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33605058000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33605058000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 28689647497 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 28689647497 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62294705497 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 62294705497 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62294705497 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 62294705497 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007475 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007475 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006295 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006295 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007019 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.007019 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007019 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.007019 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19020.403104 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19020.403104 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30553.437753 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30553.437753 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23022.750664 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23022.750664 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23022.750664 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23022.750664 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-17 18:32:53 +01:00
system.cpu.icache.tags.replacements 6016 # number of replacements
system.cpu.icache.tags.tagsinuse 1043.380208 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 171393952 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 7637 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22442.575881 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-03-17 18:32:53 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1043.380208 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.509463 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.509463 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1621 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1224 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.791504 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 343325473 # Number of tag accesses
system.cpu.icache.tags.data_accesses 343325473 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 171395976 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 171395976 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 171395976 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 171395976 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 171395976 # number of overall hits
system.cpu.icache.overall_hits::total 171395976 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 178518 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 178518 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 178518 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 178518 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 178518 # number of overall misses
system.cpu.icache.overall_misses::total 178518 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1062576000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1062576000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1062576000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1062576000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1062576000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1062576000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 171574494 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 171574494 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 171574494 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 171574494 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 171574494 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 171574494 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001040 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001040 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001040 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001040 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001040 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001040 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5952.206500 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 5952.206500 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 5952.206500 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 5952.206500 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 5952.206500 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 5952.206500 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked
2015-07-18 22:07:35 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-03-17 18:32:53 +01:00
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
2015-07-18 22:07:35 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-03-17 18:32:53 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 68.111111 # average number of cycles each access was blocked
2015-07-18 22:07:35 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2016-03-17 18:32:53 +01:00
system.cpu.icache.writebacks::writebacks 6016 # number of writebacks
system.cpu.icache.writebacks::total 6016 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2032 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2032 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2032 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2032 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2032 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2032 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 176486 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 176486 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 176486 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 176486 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 176486 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 176486 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 805089500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 805089500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 805089500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 805089500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 805089500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 805089500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4561.775438 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4561.775438 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4561.775438 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 4561.775438 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4561.775438 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 4561.775438 # average overall mshr miss latency
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.tags.replacements 355100 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29624.391257 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3897105 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 387449 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.058369 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 189360575500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21018.110892 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 185.534699 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8420.745667 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.641422 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005662 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.256981 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.904065 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32349 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
2016-03-16 21:03:49 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13364 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18670 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987213 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 43097417 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 43097417 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2332013 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2332013 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 5708 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 5708 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1488 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1488 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 563712 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 563712 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5057 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 5057 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1589822 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1589822 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 5057 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2153534 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2158591 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 5057 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2153534 # number of overall hits
system.cpu.l2cache.overall_hits::total 2158591 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 167317 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 167317 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 206886 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206886 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2535 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2535 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176564 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 176564 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2535 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 383450 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 385985 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2535 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 383450 # number of overall misses
system.cpu.l2cache.overall_misses::total 385985 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 8361500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 8361500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16391900500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16391900500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 208226000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 208226000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14213856500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 14213856500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 208226000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 30605757000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 30813983000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 208226000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 30605757000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 30813983000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2332013 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2332013 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 5708 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 5708 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 168805 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 168805 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 770598 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 770598 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 7592 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 7592 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766386 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1766386 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 7592 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2536984 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2544576 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 7592 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2536984 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2544576 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991185 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991185 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268475 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.268475 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.333904 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.333904 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099958 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099958 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.333904 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.151144 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.151689 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.333904 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.151144 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151689 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.974001 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.974001 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79231.559893 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79231.559893 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82140.433925 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82140.433925 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80502.574137 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80502.574137 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82140.433925 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79816.813144 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79832.073785 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82140.433925 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79816.813144 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79832.073785 # average overall miss latency
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.writebacks::writebacks 295111 # number of writebacks
system.cpu.l2cache.writebacks::total 295111 # number of writebacks
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 167317 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 167317 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206886 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206886 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2535 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2535 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176564 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176564 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2535 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 383450 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 385985 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2535 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 383450 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 385985 # number of overall MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3236471489 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3236471489 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14323040500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14323040500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182885002 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182885002 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12448203030 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12448203030 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182885002 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26771243530 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26954128532 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182885002 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26771243530 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26954128532 # number of overall MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991185 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991185 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268475 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268475 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.333904 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.333904 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099958 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099958 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.333904 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151144 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151689 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.333904 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151144 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151689 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19343.351178 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19343.351178 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69231.559893 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69231.559893 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72143.985010 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72143.985010 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70502.497848 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70502.497848 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72143.985010 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69816.778015 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.062210 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72143.985010 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69816.778015 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.062210 # average overall mshr miss latency
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 5421179 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2705952 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 181282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3493 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3493 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 1942871 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2627124 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 6016 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 260864 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 168805 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 168805 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 770598 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 770598 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 176486 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766386 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 190093 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7944466 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8134559 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 870848 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311615808 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 312486656 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 523994 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3237375 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.108652 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.311202 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2885627 89.13% 89.13% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 351748 10.87% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.snoop_fanout::total 3237375 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5077578963 # Layer occupancy (ticks)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 264736482 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3889880082 # Layer occupancy (ticks)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
2016-03-17 18:32:53 +01:00
system.membus.trans_dist::ReadResp 179098 # Transaction distribution
system.membus.trans_dist::WritebackDirty 295111 # Transaction distribution
system.membus.trans_dist::CleanEvict 56587 # Transaction distribution
system.membus.trans_dist::UpgradeReq 167360 # Transaction distribution
system.membus.trans_dist::ReadExReq 206843 # Transaction distribution
system.membus.trans_dist::ReadExResp 206843 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 179098 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1290940 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1290940 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1290940 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43587328 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43587328 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43587328 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-03-17 18:32:53 +01:00
system.membus.snoop_fanout::samples 904999 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-17 18:32:53 +01:00
system.membus.snoop_fanout::0 904999 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-03-17 18:32:53 +01:00
system.membus.snoop_fanout::total 904999 # Request fanout histogram
system.membus.reqLayer0.occupancy 2207449441 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 2041679000 # Layer occupancy (ticks)
2016-02-10 10:08:27 +01:00
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
2011-04-25 23:18:08 +02:00
---------- End Simulation Statistics ----------
