2011-02-05 09:16:09 +01:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 0.079230 # Number of seconds simulated
sim_ticks 79229645000 # Number of ticks simulated
final_tick 79229645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-02-05 09:16:09 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-11-06 09:26:50 +01:00
host_inst_rate 90742 # Simulator instruction rate (inst/s)
host_op_rate 152092 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 54436376 # Simulator tick rate (ticks/s)
host_mem_usage 350016 # Number of bytes of host memory used
host_seconds 1455.45 # Real time elapsed on the host
2012-08-15 16:38:05 +02:00
sim_insts 132071192 # Number of instructions simulated
2013-10-02 11:03:38 +02:00
sim_ops 221363384 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::total 345920 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::cpu.inst 2789259 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1576784 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4366043 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2789259 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2789259 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2789259 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1576784 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4366043 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.readReqs 5405 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2015-09-25 13:27:03 +02:00
system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2015-09-25 13:27:03 +02:00
system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2015-09-25 13:27:03 +02:00
system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2015-11-06 09:26:50 +01:00
system.physmem.neitherReadNorWriteReqs 261 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 295 # Per bank write bursts
system.physmem.perBankRdBursts::1 347 # Per bank write bursts
system.physmem.perBankRdBursts::2 460 # Per bank write bursts
2015-09-25 13:27:03 +02:00
system.physmem.perBankRdBursts::3 350 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::4 341 # Per bank write bursts
system.physmem.perBankRdBursts::5 328 # Per bank write bursts
system.physmem.perBankRdBursts::6 402 # Per bank write bursts
system.physmem.perBankRdBursts::7 383 # Per bank write bursts
system.physmem.perBankRdBursts::8 339 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::9 281 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::10 240 # Per bank write bursts
2015-09-25 13:27:03 +02:00
system.physmem.perBankRdBursts::11 284 # Per bank write bursts
system.physmem.perBankRdBursts::12 217 # Per bank write bursts
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::13 468 # Per bank write bursts
system.physmem.perBankRdBursts::14 388 # Per bank write bursts
system.physmem.perBankRdBursts::15 282 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-11-06 09:26:50 +01:00
system.physmem.totGap 79229612500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::6 5405 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::0 4295 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 313.361237 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 181.828976 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.670559 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 436 39.67% 39.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 230 20.93% 60.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 99 9.01% 69.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 58 5.28% 74.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 55 5.00% 79.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 56 5.10% 84.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 23 2.09% 87.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 18 1.64% 88.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 124 11.28% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation
system.physmem.totQLat 41940250 # Total ticks spent queuing
system.physmem.totMemAccLat 143284000 # Total ticks spent from burst creation until serviced by the DRAM
2015-09-25 13:27:03 +02:00
system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers
2015-11-06 09:26:50 +01:00
system.physmem.avgQLat 7759.53 # Average queueing delay per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-11-06 09:26:50 +01:00
system.physmem.avgMemAccLat 26509.53 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-04-30 05:35:23 +02:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2015-11-06 09:26:50 +01:00
system.physmem.readRowHits 4297 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2015-11-06 09:26:50 +01:00
system.physmem.readRowHitRate 79.50 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgGap 14658577.71 # Average gap between requests
system.physmem.pageHitRate 79.50 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 22526400 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2444474070 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 45390936750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 53040118785 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.484152 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 75508317500 # Time in different power states
system.physmem_0.memoryStateTime::REF 2645500000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::ACT 1071550000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.actEnergy 3386880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1848000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 19312800 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2297025045 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 45520269750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 53016440475 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.185395 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 75726888000 # Time in different power states
system.physmem_1.memoryStateTime::REF 2645500000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::ACT 855243500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.lookups 20592907 # Number of BP lookups
system.cpu.branchPred.condPredicted 20592907 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1327799 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 12698364 # Number of BTB lookups
system.cpu.branchPred.BTBHits 12013605 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.BTBHitPct 94.607502 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1441126 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16761 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 400 # Number of system calls
2015-11-06 09:26:50 +01:00
system.cpu.numCycles 158459291 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu.fetch.icacheStallCycles 25251668 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 227436303 # Number of instructions fetch has processed
system.cpu.fetch.Branches 20592907 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 13454731 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 131379126 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3193881 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 2041 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 21671 # Number of stall cycles due to pending traps
2014-09-03 13:42:59 +02:00
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
2015-09-15 15:14:09 +02:00
system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR
2015-11-06 09:26:50 +01:00
system.cpu.fetch.CacheLines 24259483 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 266288 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 158251507 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.376692 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.323734 # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::0 95931722 60.62% 60.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4757646 3.01% 63.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3806394 2.41% 66.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4363208 2.76% 68.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4227713 2.67% 71.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4814821 3.04% 74.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4714702 2.98% 77.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3700525 2.34% 79.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 31934776 20.18% 100.00% # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::total 158251507 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.129957 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.435298 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 15405673 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96363491 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 23242332 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 21643071 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1596940 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 336546765 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1596940 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 23300664 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 31883477 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 30445 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 35976653 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 65463328 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 328193711 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1319 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 57856617 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7708627 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 165863 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 380358715 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 909771649 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 600461611 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4182617 # Number of floating rename lookups
2013-06-24 20:17:22 +02:00
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
2015-11-06 09:26:50 +01:00
system.cpu.rename.UndoneMaps 120929265 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2085 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 121166066 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 82747977 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 29791267 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 59612118 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 20405352 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 317780620 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4165 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 259339471 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 71881 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 96421401 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 197095861 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2920 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 158251507 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.638780 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.522654 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::0 40084558 25.33% 25.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 47634072 30.10% 55.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 33122012 20.93% 76.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18013851 11.38% 87.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10936157 6.91% 94.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4740478 3.00% 97.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2457312 1.55% 99.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 875604 0.55% 99.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 387463 0.24% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::total 158251507 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::IntAlu 234483 7.38% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.38% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2555698 80.47% 87.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 385880 12.15% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::No_OpClass 1212784 0.47% 0.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 161792342 62.39% 62.85% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 789140 0.30% 63.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7038106 2.71% 65.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1186493 0.46% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 64866325 25.01% 91.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 22454281 8.66% 100.00% # Type of FU issued
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::total 259339471 # Type of FU issued
system.cpu.iq.rate 1.636632 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3176061 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012247 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 675323210 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 410805836 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 253605894 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4855181 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 3696441 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2340510 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 258858304 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2444444 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18689568 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 26098390 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 12338 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 302582 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 9275550 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewSquashCycles 1596940 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 12493200 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 494306 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 317784785 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 94743 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 82747977 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 29791267 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1931 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 389039 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 63652 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 302582 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 551479 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 825731 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1377210 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 257282682 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 64058012 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2056789 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
2015-11-06 09:26:50 +01:00
system.cpu.iew.exec_refs 86333641 # number of memory reference insts executed
system.cpu.iew.exec_branches 14326229 # Number of branches executed
system.cpu.iew.exec_stores 22275629 # Number of stores executed
system.cpu.iew.exec_rate 1.623652 # Inst execution rate
system.cpu.iew.wb_sent 256637538 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 255946404 # cumulative count of insts written-back
system.cpu.iew.wb_producers 204333247 # num instructions producing a value
system.cpu.iew.wb_consumers 369622334 # num instructions consuming a value
system.cpu.iew.wb_rate 1.615219 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.552816 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 96429188 # The number of squashed insts skipped by commit
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
2015-11-06 09:26:50 +01:00
system.cpu.commit.branchMispredicts 1329692 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 145106129 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.525527 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.953873 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::0 45566766 31.40% 31.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 57414676 39.57% 70.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14193363 9.78% 80.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12012309 8.28% 89.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4072580 2.81% 91.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2869750 1.98% 93.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 928162 0.64% 94.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1071171 0.74% 95.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6977352 4.81% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::total 145106129 # Number of insts commited each cycle
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
2013-10-02 11:03:38 +02:00
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 77165304 # Number of memory references committed
system.cpu.commit.loads 56649587 # Number of loads committed
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 12326938 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 797818 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction
2014-09-01 23:55:52 +02:00
system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.bw_lim_events 6977352 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 455921349 # The number of ROB reads
system.cpu.rob.rob_writes 648768029 # The number of ROB writes
system.cpu.timesIdled 2647 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 207784 # Total number of cycles that the CPU has spent unscheduled due to idling
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
2013-10-02 11:03:38 +02:00
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
2015-11-06 09:26:50 +01:00
system.cpu.cpi 1.199802 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.199802 # CPI: Total CPI of All Threads
system.cpu.ipc 0.833471 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.833471 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 448461429 # number of integer regfile reads
system.cpu.int_regfile_writes 232562681 # number of integer regfile writes
system.cpu.fp_regfile_reads 3213153 # number of floating regfile reads
system.cpu.fp_regfile_writes 1998427 # number of floating regfile writes
system.cpu.cc_regfile_reads 102530427 # number of cc regfile reads
system.cpu.cc_regfile_writes 59507422 # number of cc regfile writes
system.cpu.misc_regfile_reads 132428508 # number of misc regfile reads
2013-06-24 20:17:22 +02:00
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.replacements 51 # number of replacements
system.cpu.dcache.tags.tagsinuse 1429.692139 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 65755137 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1993 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 32993.044155 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 1429.692139 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.349046 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.349046 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 131517093 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 131517093 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 45240855 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 45240855 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20513928 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20513928 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 65754783 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 65754783 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 65754783 # number of overall hits
system.cpu.dcache.overall_hits::total 65754783 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 964 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 964 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1803 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1803 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2767 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2767 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2767 # number of overall misses
system.cpu.dcache.overall_misses::total 2767 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65032500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 65032500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 127862500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 127862500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 192895000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 192895000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 192895000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 192895000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 45241819 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 45241819 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_accesses::cpu.data 65757550 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 65757550 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 65757550 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 65757550 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000088 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000088 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67461.099585 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 67461.099585 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70916.528009 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 70916.528009 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 69712.685219 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 69712.685219 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu.dcache.writebacks::writebacks 10 # number of writebacks
system.cpu.dcache.writebacks::total 10 # number of writebacks
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 511 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 513 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 513 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 513 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 513 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 453 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 453 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1801 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1801 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2254 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2254 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2254 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2254 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36207500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36207500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125915500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 125915500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162123000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 162123000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162123000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 162123000 # number of overall MSHR miss cycles
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79928.256071 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79928.256071 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69914.214325 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69914.214325 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71926.796806 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71926.796806 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71926.796806 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71926.796806 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.replacements 4974 # number of replacements
system.cpu.icache.tags.tagsinuse 1637.723048 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 24250086 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6949 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3489.723126 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1637.723048 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.799669 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.799669 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1975 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.964355 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 48526174 # Number of tag accesses
system.cpu.icache.tags.data_accesses 48526174 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 24250086 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 24250086 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 24250086 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 24250086 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 24250086 # number of overall hits
system.cpu.icache.overall_hits::total 24250086 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 9396 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 9396 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 9396 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 9396 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 9396 # number of overall misses
system.cpu.icache.overall_misses::total 9396 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 410761999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 410761999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 410761999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 410761999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 410761999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 410761999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24259482 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24259482 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 24259482 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 24259482 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 24259482 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 24259482 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000387 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000387 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000387 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000387 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000387 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000387 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43716.687846 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 43716.687846 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 43716.687846 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 43716.687846 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 69.230769 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 4974 # number of writebacks
system.cpu.icache.writebacks::total 4974 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2184 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2184 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2184 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2184 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2184 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2184 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7212 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 7212 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 7212 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 7212 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 7212 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 7212 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312005999 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 312005999 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312005999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 312005999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312005999 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 312005999 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000297 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43262.063089 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43262.063089 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.tagsinuse 2583.684571 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8457 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3872 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.184143 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 1.785192 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2278.815860 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 303.083519 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069544 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.009249 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.078848 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3872 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2610 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118164 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 118500 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 118500 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 10 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 10 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4883 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 4883 # number of WritebackClean hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3495 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 3495 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 35 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3495 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 41 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 3536 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3495 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits
system.cpu.l2cache.overall_hits::total 3536 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 261 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 261 # number of UpgradeReq misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 1534 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1534 # number of ReadExReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3454 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3454 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 418 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 418 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3454 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1952 # number of demand (read+write) misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_misses::total 5406 # number of demand (read+write) misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 3454 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1952 # number of overall misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_misses::total 5406 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114869500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 114869500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 263804000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 263804000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35120500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35120500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 263804000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 149990000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 413794000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 263804000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 149990000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 413794000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 10 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 10 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 4883 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 4883 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 261 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 261 # number of UpgradeReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1540 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1540 # number of ReadExReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6949 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 6949 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 453 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 453 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 6949 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1993 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 8942 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6949 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1993 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8942 # number of overall (read+write) accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996104 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.996104 # miss rate for ReadExReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.497050 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.497050 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.922737 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.922737 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497050 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.979428 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.604563 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497050 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.979428 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.604563 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74882.333768 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.333768 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76376.375217 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76376.375217 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84020.334928 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84020.334928 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76376.375217 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76839.139344 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76543.470218 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76376.375217 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76839.139344 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76543.470218 # average overall miss latency
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 261 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 261 # number of UpgradeReq MSHR misses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1534 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1534 # number of ReadExReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3454 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3454 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 418 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 418 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3454 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1952 # number of demand (read+write) MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_mshr_misses::total 5406 # number of demand (read+write) MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3454 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1952 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_misses::total 5406 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5671500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5671500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99529500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99529500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 229284000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 229284000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30940500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30940500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229284000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130470000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 359754000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229284000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130470000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 359754000 # number of overall MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996104 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996104 # mshr miss rate for ReadExReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.497050 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.497050 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.922737 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.922737 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.497050 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979428 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.604563 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.497050 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979428 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.604563 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21729.885057 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21729.885057 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64882.333768 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64882.333768 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66382.165605 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66382.165605 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74020.334928 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74020.334928 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 14491 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 5309 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 353 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 7663 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4883 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 40 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 261 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 261 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 7212 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 453 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19042 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4558 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 23600 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 757120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128192 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 885312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 263 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 9466 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.067293 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.250543 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::0 8829 93.27% 93.27% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 637 6.73% 100.00% # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::total 9466 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12229500 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 10815000 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3120998 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadResp 3870 # Transaction distribution
system.membus.trans_dist::UpgradeReq 261 # Transaction distribution
system.membus.trans_dist::UpgradeResp 261 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadExReq 1534 # Transaction distribution
system.membus.trans_dist::ReadExResp 1534 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11331 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11331 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11331 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 345856 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::samples 5666 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::0 5666 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 5666 # Request fanout histogram
system.membus.reqLayer0.occupancy 6923000 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.respLayer1.occupancy 29158989 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
2011-02-05 09:16:09 +01:00
---------- End Simulation Statistics ----------
