Commit graph

697 commits

Author SHA1 Message Date
Gabe Black
d29979b043 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : dba3542ab73cc8ae46347a14ae4c133f1276011c
2007-04-08 01:54:08 +00:00
Gabe Black
3bb5fd8c44 Get the "hard" SPARC instructions working in o3. I don't like that the IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
--HG--
extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
2007-04-08 01:42:42 +00:00
Gabe Black
5d52cd6409 Move the instruction specialization stuff out of the microassembler file, and added some comments to main.isa
--HG--
extra : convert_revision : 1534ae7d5a9e95bf662d79a04f9286c227541c6c
2007-04-06 16:55:56 +00:00
Gabe Black
59df95c7e6 Consolidated the microcode assembler to help separate it from more x86-centric stuff.
--HG--
extra : convert_revision : 5e7e8026e24ce44a3dac4a358e0c3e5560685958
2007-04-06 16:39:25 +00:00
Gabe Black
2a1c102f25 Refactored the x86 isa description some more. There should be more seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
--HG--
rename : src/arch/x86/isa/formats/macroop.isa => src/arch/x86/isa/macroop.isa
extra : convert_revision : 5ab40eedf574fce438d9fe90e00a496dc95c8bcf
2007-04-06 16:00:56 +00:00
Gabe Black
75e8838ba4 Clean up the code a little, fix (I think) a perceived problem with immediate sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
--HG--
extra : convert_revision : e59b747198cc79d50045bd2dc45b2e2b97bbffcc
2007-04-06 15:19:23 +00:00
Gabe Black
e633e23a3a Add in a stub merging function
--HG--
extra : convert_revision : 15e3cdb4ebcd31bc44204687ba59dde00c56c6be
2007-04-06 15:16:36 +00:00
Gabe Black
47c24ff07a Clean up the macroop code.
--HG--
extra : convert_revision : 3cf83c3e038fece6190dbb91f56deb0498c9a70d
2007-04-06 15:15:36 +00:00
Gabe Black
ff7b89beee The process of going from an instruction definition to an instruction to be returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.
1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter.
2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number.
3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM.
4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s.
5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it.

In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/base.isa:
    Implemented polymorphic microops and changed around the microcode assembler syntax.

--HG--
extra : convert_revision : e341f7b8ea9350a31e586a3d33250137e5954f43
2007-04-04 23:35:20 +00:00
Gabe Black
ab2bed349b Fix a regular expression problem when recognizing labels for string substitution.
--HG--
extra : convert_revision : ba398e1b434efda28882f159d5a4419302276371
2007-04-04 23:19:32 +00:00
Gabe Black
4285990a96 Reworking how x86's isa description works. I'm adopting the following definitions to make figuring out what's what a little easier:
MicroOp: A single operation actually implemented in hardware.
MacroOp: A collection of microops which are executed as a unit.
Instruction: An architected instruction which can be implemented with a macroop or a microop.

--HG--
extra : convert_revision : 1cfc8409cc686c75220767839f55a30551aa6f13
2007-04-04 14:31:59 +00:00
Gabe Black
7f5409f2ba Make "Name" really be the same as "name" with only the first letter capitalized. Before, it had the first letter capitalized but all the others lower case
--HG--
extra : convert_revision : bcbb28f2bf268765c1d37075a4417a4a6c1b9588
2007-04-04 14:28:43 +00:00
Gabe Black
65fedeb5a7 Made x86 ExtMachInsts distinguishable from each other by defining a real == and a real hash function.
--HG--
extra : convert_revision : 30f29a36f6ab44e67e62aaf81b685fbe1267c746
2007-04-04 14:27:00 +00:00
Gabe Black
6010c6ded4 Added all the different variations of the register names.
--HG--
extra : convert_revision : ff06bdca556a5e1a0dfe7978575c2277c30c002a
2007-04-04 14:25:36 +00:00
Gabe Black
93d4c624c5 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 7be8ebe55a7b11552d78701520f93aa86db1e501
2007-04-03 15:01:36 +00:00
Gabe Black
61c56ffeaf A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
--HG--
extra : convert_revision : 518059f47e11df50aa450d4a322ef2ac069c99c9
2007-04-03 15:01:09 +00:00
Gabe Black
0ce6936e7d Zero out ModRM if the byte isn't there, and fix some displacement size stuff.
--HG--
extra : convert_revision : f43abf33a223a665b30098c63011fb162200d5e6
2007-04-03 14:56:24 +00:00
Ali Saidi
c46e946c94 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 2f7f50f4ad31f741c0c67db96e49d30ca078fc94
2007-03-29 22:01:34 -04:00
Ali Saidi
8ca218cab5 get rid of CWP bounds warning...
--HG--
extra : convert_revision : 74df09341c091c2d6ca9b46c6a3521f22b48acf4
2007-03-29 15:57:11 -04:00
Gabe Black
7fcc9d2106 Made the MultiOp format do a little more. It now sets up single microop instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support.
--HG--
extra : convert_revision : 1a0a4b36afce8255e23e3cdd7a85c1392dda5f72
2007-03-29 17:57:19 +00:00
Gabe Black
e67a207ad3 Add a microcode assembler. A microcode "program" is a series of statements. Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself.
--HG--
extra : convert_revision : 8e5cfdd1a3c9a7e3731fdf6acd615ee82ac2b9b7
2007-03-29 17:57:18 +00:00
Gabe Black
77ce05f478 Fidget with the syntax of the MultiOp format in anticipation of making it actually work.
--HG--
extra : convert_revision : f62a1f035cc11677df8eb5a839ca1247d819fab3
2007-03-29 00:50:54 -07:00
Gabe Black
fd77212b72 Add code to generate register and immediate based integer op microop classes.
--HG--
extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
2007-03-29 00:49:53 -07:00
Gabe Black
0d5f6167ff Allow "let" blocks to add code to the output files.
--HG--
extra : convert_revision : 0ffddb2b40dccbf2a3790464c843cfc1b43eaa02
2007-03-29 00:47:46 -07:00
Kevin Lim
4bad33ce9d Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

--HG--
extra : convert_revision : f3d193dd1e0b82c496d8224f014123b7cb028c02
2007-03-24 14:00:16 -04:00
Gabe Black
e7bbd85ae6 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : 6b1c8025d29f3e8f90906805dd51a5d523d56004
2007-03-23 21:47:03 -04:00
Kevin Lim
047f77102b Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

src/cpu/base_dyn_inst.hh:
    Hand merge.  Line is no longer needed because it's handled in the ISA.

--HG--
extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
2007-03-23 13:20:19 -04:00
Kevin Lim
2330adfa28 Make hardware loads/stores serializing; they need to avoid certain out-of-order interactions in the 21264.
--HG--
extra : convert_revision : d83940af7d0e8efe891d574ac42c6d70d179e2b1
2007-03-23 13:14:05 -04:00
Gabe Black
e3d3ab4513 Add structure based bitfield syntax to the isa_parser. This is primarily useful for x86.
--HG--
extra : convert_revision : dfe6df160d00adec1830d9b88520ba20834d1209
2007-03-22 04:10:57 +00:00
Gabe Black
39182808bc Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : 79c337f18d635acc176f0ca8d6e71fbc429cb258
2007-03-22 04:10:56 +00:00
Gabe Black
276f6d794d Add a junk operand. With no operands, the parser breaks.
--HG--
extra : convert_revision : 7410fd3681ed3d9b1293d982ed5f3553a6c75f3f
2007-03-21 21:09:24 +00:00
Gabe Black
bbffaa8ee0 Start implementing groups of instructions which do the same thing on different sets of inputs.
--HG--
extra : convert_revision : 6a5be61831588f801965dd4e80cb52f28911c320
2007-03-21 21:07:43 +00:00
Gabe Black
1707aa750f put the int register count in intregs.hh
--HG--
extra : convert_revision : c48c13d9c4606c8cb7c60d18cd0f4dac9103a501
2007-03-21 21:04:54 +00:00
Gabe Black
0a80d06dea Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are.
--HG--
extra : convert_revision : 8768676eac25e6a4f0dc50ce2dc576bdcdd6e025
2007-03-21 19:19:53 +00:00
Gabe Black
3efec59fc5 Missed a const
--HG--
rename : src/arch/x86/isa/decoder.isa => src/arch/x86/isa/decoder/decoder.isa
extra : convert_revision : a60e7495da6fe99fa2375a3f801f2962c3e41adb
2007-03-21 19:15:40 +00:00
Gabe Black
63e2d3dcbf Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : 41214c71e7fa11d47395975a141793337d020463
2007-03-21 01:18:55 -04:00
Gabe Black
475d36ee93 Ignore "time" and "times" syscalls.
--HG--
extra : convert_revision : 3ff55e35877c0fd74823ce5e52ed16c38da92068
2007-03-20 23:53:52 -04:00
Gabe Black
e7b015cee1 Added syntax for structure oriented extMachInsts.
--HG--
extra : convert_revision : 4a30c58019ad8e3dd8dffb4c4c08eb6914e5c5be
2007-03-20 06:08:52 +00:00
Gabe Black
7c0825ccf9 Compile fixes for SPARC_FS.
src/arch/alpha/predecoder.hh:
src/arch/sparc/predecoder.hh:
    Put in a missing include
src/cpu/exetrace.cc:
    Convert the legion lockstep stuff from makeExtMI to the predecoder object.

--HG--
extra : convert_revision : 91bad4466f8db1447fff8608fa46a5f236dc3a89
2007-03-18 23:09:51 -04:00
Gabe Black
a1f92af0fb The syntax used for twin stores was confusing the parser so it's now broken down farther.
--HG--
extra : convert_revision : d36bef2d15bc013b3c6199901f57855dfb9dab76
2007-03-17 21:23:03 -04:00
Gabe Black
3ccaee976a Make the SPARC branch instructions use ExtMachInsts in their constructors. This isn't necessary since they don't use the extended fields, but it's more consistent and more correct.
--HG--
extra : convert_revision : afd4f408122ad5e497012eb9744d6bce66a1de37
2007-03-16 10:55:50 +00:00
Gabe Black
9ad3f1e479 Refactor things a little.
--HG--
extra : convert_revision : 8167455ffc05130d4afcc68466879c7c439bee57
2007-03-15 19:16:39 +00:00
Gabe Black
f4eee4fb81 File with the predecoder in it.
src/arch/x86/predecoder.cc:
    File for the x86 predecoder process function.

--HG--
extra : convert_revision : f7b53c38ff152cb2677d641074218ffd8434457b
2007-03-15 19:16:38 +00:00
Gabe Black
ae9bed4f8f Split the x86 "process" predecoder method into it's own file.
--HG--
extra : convert_revision : 88185e592df2a7527d36efcce7376fb05f469cbc
2007-03-15 19:16:37 +00:00
Gabe Black
6cdd434f7f Changed warns to DPRINTFs and multiply by 8 where needed.
--HG--
extra : convert_revision : 9db0bc2420ceb5828a79881fa0b420a2d5e5f358
2007-03-15 16:13:40 +00:00
Gabe Black
075df1469f Added immediate value support, and fixed alot of bugs. This won't support 3 byte opcodes.
--HG--
extra : convert_revision : 4c79bff2592a668e1154916875f019ecafe67022
2007-03-15 15:29:39 +00:00
Gabe Black
4379e54b52 Compile fix
--HG--
extra : convert_revision : 4a66d04404beee9656e3e33089afcec10d7ee5ff
2007-03-15 03:17:00 +00:00
Gabe Black
32368a2bd6 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/arch/mips/utility.hh:
src/arch/x86/SConscript:
    Hand merge

--HG--
extra : convert_revision : 0ba457aab52bf6ffc9191fd1fe1006ca7704b5b0
2007-03-15 02:52:51 +00:00
Gabe Black
a2b56088fb Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.
src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
    Make the predecoder an object with it's own switched header file.

--HG--
extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
2007-03-15 02:47:42 +00:00
Gabe Black
ff90b8c1aa Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : 61eca737296a5ce839d3b97f047b4fda062cb899
2007-03-13 15:03:34 -04:00
Gabe Black
ce18d900a1 Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.

--HG--
extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
2007-03-13 16:13:21 +00:00
Ali Saidi
a068d6db0f fix interrupting during a quisce on sparc
src/arch/sparc/ua2005.cc:
    fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to
    check if were suspended and interrupt at the guess time
src/base/traceflags.py:
    add trace flag for Iob
src/cpu/simple/base.cc:
    Use Quisce instead of IPI trace flag
src/dev/sparc/iob.cc:
    add some Dprintfs

--HG--
extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
2007-03-13 00:05:52 -04:00
Gabe Black
1f3c3aa234 Fix mulscc.
--HG--
extra : convert_revision : 405f10f14f2f6666a7bef01bfb0cf90ff14cef24
2007-03-12 17:07:10 -04:00
Ali Saidi
1356fb953d Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c6fbe09348b606b94bbb35f911dea94353f076f9
2007-03-12 13:56:30 -04:00
Ali Saidi
9ad24e2248 move hver code to ua2005.cc
src/arch/sparc/miscregfile.cc:
    this code should be in readFSreg
src/arch/sparc/ua2005.cc:
    move code froh miscregfile to ua2005.cc

--HG--
extra : convert_revision : fa450b04ad73ab6f6e25d66fa0368054263f09f9
2007-03-12 13:56:09 -04:00
Gabe Black
b3bdce81fd Add the rename syscall.
--HG--
extra : convert_revision : 67e92b166599bd20b7ce90d073f2fd7502f810ec
2007-03-12 01:54:15 -04:00
Gabe Black
57650a201e Fix the mnemonic and the branch displacement field size of the branch on floating point condition codes with prediction.
--HG--
extra : convert_revision : 812950e92b7e0f34f370a1472c20f52e3ef214b1
2007-03-12 01:47:49 -04:00
Gabe Black
6a7e4a5904 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : 725999a0a5bde6e065bad87b42e973c5c627c69f
2007-03-11 18:19:38 -04:00
Gabe Black
26c0426e44 Make sttw and sttwa use the twin memory operations.
--HG--
extra : convert_revision : 368d1c57a46fd5ca15461cb5ee8e05fd1e080daa
2007-03-11 18:12:33 -04:00
Nathan Binkert
1aef5c06a3 Rework the way SCons recurses into subdirectories, making it
automatic.  The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes.  On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory.  On the second pass,
all subdirs of the src directory are searched for SConscript
files.  These files describe how to build any given subdirectory.
I have added a Source() function.  Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build.  Clean up everything to take
advantage of Source().
function is added to the list of files to be built.

--HG--
extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-10 23:00:54 -08:00
Gabe Black
52ec0fe3d9 Merge zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace-test

--HG--
extra : convert_revision : dc02bb6b4e5cc7f0260da80a71b9713f75566a29
2007-03-10 20:52:55 -05:00
Gabe Black
7e363e14f7 Fix bounds check for the cwp
--HG--
extra : convert_revision : 097e6b0c80d71417329b2a4cd118046aa5ed777a
2007-03-10 19:29:31 -05:00
Gabe Black
91e8729c28 Added implementations of the fpop2 instructions.
--HG--
extra : convert_revision : 1fc88b499334bb4ba44375347d0062843587b6cf
2007-03-10 19:26:54 -05:00
Gabe Black
df1ea2cf05 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : 82a956ffc1bedb2c0d05c4ea3469f843f559a475
2007-03-09 18:32:13 -05:00
Gabe Black
03ff1c3167 Split the syscall table, SPARC specific syscall implementations, and the 32 bit syscall table into it's own file. Corrected problems with the stat structure. These should be tested on 64 bit x86 and SPARC machines.
--HG--
extra : convert_revision : 5d9fe19e031b92e111069c6b89c3dbeb29975b8a
2007-03-09 17:14:24 -05:00
Ali Saidi
58f69391ca implement ipi stufff for SPARC
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/arch/x86/utility.hh:
    add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi
src/arch/sparc/isa/decoder.isa:
    handle writable bits of strandstatus register in miscregfile
src/arch/sparc/miscregfile.hh:
    some constants for the strand status register
src/arch/sparc/ua2005.cc:
    properly implement the strand status register
src/dev/sparc/iob.cc:
    implement ipi generation properly
src/sim/system.cc:
    call into the ISA to start the CPU (or not)

--HG--
extra : convert_revision : 0003b2032337d8a031a9fc044da726dbb2a9e36f
2007-03-09 16:56:39 -05:00
Ali Saidi
1158da37fb Panic if any CMT registers are accessed
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add CMT ASI registers
src/arch/sparc/tlb.cc:
    Panic if any of the CMT registers are being accessed

--HG--
extra : convert_revision : b9a94281e2074a576ac21d042b756950d509e758
2007-03-08 21:49:13 -05:00
Gabe Black
c40d95e4c4 Fixed an off-by-one error.
--HG--
extra : convert_revision : 498fef18cf339cabc2c00e4758bc8a0da857daca
2007-03-08 00:55:16 -05:00
Gabe Black
46051c5f65 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace

--HG--
extra : convert_revision : becba8537b11ee4ef33bbf129bef2ca047403df5
2007-03-08 00:42:30 -05:00
Gabe Black
5caf721074 Fix up the SPARC initial stack frame to match an actual 32 bit process.
--HG--
extra : convert_revision : 3995744c3bf955a370b18f6e88de1bfb82f79843
2007-03-08 00:29:37 -05:00
Ali Saidi
87fb0eb8de I missed a couple of WithEffects, this should do it
--HG--
extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
2007-03-07 21:51:44 -05:00
Gabe Black
54fc750924 Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.
--HG--
extra : convert_revision : 18d441eb7ac44df4df41771bfe3dec69f7fa70ec
2007-03-07 20:04:46 +00:00
Ali Saidi
49527ab553 Merge zizzer:/bk/newmem
into  zeep.pool:/tmp/newmem

--HG--
extra : convert_revision : f078a05729b5fe464a06a58bc4adcb374f560572
2007-03-07 15:04:44 -05:00
Ali Saidi
689cab36c9 *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
2007-03-07 15:04:31 -05:00
Gabe Black
05c86ec0d7 Get X86 to load an elf and start a process for it.
src/arch/x86/SConscript:
    Add in process source files.
src/arch/x86/isa_traits.hh:
    Replace magic constant numbers with the x86 register names.
src/arch/x86/miscregfile.cc:
    Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy.
src/arch/x86/process.hh:
    An X86 process class.
src/base/loader/elf_object.cc:
    Add in code to recognize x86 as an architecture.
src/base/traceflags.py:
    Add an x86 traceflag
src/sim/process.cc:
    Add in code to create an x86 process.
src/arch/x86/intregs.hh:
    A file which declares names for the integer register indices.
src/arch/x86/linux/linux.cc:
src/arch/x86/linux/linux.hh:
    A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either.
src/arch/x86/linux/process.cc:
src/arch/x86/linux/process.hh:
    An x86 linux process. The syscall table is split out into it's own file.
src/arch/x86/linux/syscalls.cc:
    The x86 Linux syscall table and the uname function.
src/arch/x86/process.cc:
    The x86 process base class.
tests/test-progs/hello/bin/x86/linux/hello:
    An x86 hello world test binary.

--HG--
extra : convert_revision : f22919e010c07aeaf5757dca054d9877a537fd08
2007-03-06 15:42:30 +00:00
Gabe Black
992fda55f9 Fill out a stub version of the vtophys header file.
--HG--
extra : convert_revision : 2c10a80a2f73207539e3f98b4a3b864d431f5035
2007-03-05 17:59:04 +00:00
Gabe Black
296891b1c5 Add in NumGDBRegs so the constructor to the base class can get all it's arguments.
--HG--
extra : convert_revision : fcec1ad134b53a419a952e556ed75cb1559a1127
2007-03-05 17:58:15 +00:00
Gabe Black
a473d50e4c Reorganize the floating point register file a little.
--HG--
extra : convert_revision : 643c147b77e931d49ac559681d4bbda737f6e1c7
2007-03-05 17:57:26 +00:00
Gabe Black
a46e100bd9 Add some new source files.
--HG--
extra : convert_revision : 94f3f19eb91b7f54918640b7605008eb1fe75fc7
2007-03-05 17:56:26 +00:00
Gabe Black
a41b86ba01 Stub decoder. This is probably even farther from finished than it looks...
--HG--
extra : convert_revision : a39a158fec4560f6eb7a6987592c473677c0b1ba
2007-03-05 16:16:28 +00:00
Gabe Black
a0294c10cd Added missing include.
--HG--
extra : convert_revision : 9d00209e5c0ae8aa5ac37f9558627ee212a72c9b
2007-03-05 16:11:07 +00:00
Gabe Black
ecfc622451 Added LargestRead type for x86. I might have picked the wrong type.
--HG--
extra : convert_revision : 5570a595b9adbe9c35f9b4f8dd3b50533b5beb97
2007-03-05 16:10:11 +00:00
Gabe Black
78e5406f19 Stub implementation for x86.
--HG--
extra : convert_revision : 3eccbf699bb62139a06a9b249e56bd205bc316ed
2007-03-05 16:09:09 +00:00
Gabe Black
05ba90b726 Stub implementation for x86
--HG--
extra : convert_revision : dd6b4d14070a2e99c179c5f780c9935847da8eda
2007-03-05 16:08:18 +00:00
Gabe Black
58d30df676 Added fault generation functions. I would still like to see these go away. The page table fault should be moved into sim/faults.hh because it's a "fake" m5 fault for se mode and shouldn't vary between architectures.
--HG--
extra : convert_revision : cafe25befd64f83a424c1a09f5e62a16df5408ad
2007-03-05 16:07:01 +00:00
Gabe Black
7730af9503 Added stub implementations or prototypes for all the functions in this file.
--HG--
extra : convert_revision : c0170eae8aeae130f81618ae49a60f879c2b523f
2007-03-05 14:55:09 +00:00
Gabe Black
b2d356a6b2 Added in a missing include.
--HG--
extra : convert_revision : 712480fef36bf7a34c2c0b8d19dd82689eb78a1d
2007-03-05 14:53:51 +00:00
Gabe Black
7ed7d6e80d Filled in a stub header file for setting the result of a syscall.
--HG--
extra : convert_revision : f0a2cdf7d669834b90444fc390b0aceede474737
2007-03-05 14:53:15 +00:00
Gabe Black
43b8f51bb8 Filled in a stub header file for a stacktrace object. I'm still not sure what this is for, and it probably doesn't work on anything but Alpha.
--HG--
extra : convert_revision : 9bc3833628d31799a7b578c450dac096a19aead3
2007-03-05 14:52:28 +00:00
Gabe Black
2e6cf12963 Filled in a stub header file for remote gdb
--HG--
extra : convert_revision : 6289181697142f672548a4d4cf6e010171cb98e1
2007-03-05 14:51:21 +00:00
Gabe Black
aa5f42b10d Correct a typo
--HG--
extra : convert_revision : 1e8ef87ddb28873045a08bd104afc8ce129c4299
2007-03-05 14:50:33 +00:00
Gabe Black
0e9db1a2e5 Make the constructor (and all the other functions) public
--HG--
extra : convert_revision : 9d572651fc1722b15ae7dbc59c108d680c911f04
2007-03-05 14:49:52 +00:00
Gabe Black
b832e6740f Various touch ups
--HG--
extra : convert_revision : 19ff30d969a46adbd256f674582a9e7d398b56ed
2007-03-05 14:49:07 +00:00
Gabe Black
ecc1066f43 Added a missing include.
--HG--
extra : convert_revision : 15a1b49ff9e0a1a15bd2500bec9ec9bc95ee5898
2007-03-05 14:48:18 +00:00
Gabe Black
ec8b49cc5f Added a missing include.
--HG--
extra : convert_revision : 62583e5a5647913fb36e1aae265e8ac52a165829
2007-03-05 14:47:42 +00:00
Gabe Black
8a33c8dce4 Fix up the remote gdb include gaurds so it doesn't use the same symbol as Alpha does.
--HG--
extra : convert_revision : b75dbdd95ceb4ec71275588a5cf8e6b614cf4539
2007-03-05 14:46:49 +00:00
Gabe Black
30e700600c x86 register file includes.
--HG--
extra : convert_revision : c00a077dd7ae8f6b48c6939034be244bcf48d715
2007-03-05 12:23:14 +00:00
Gabe Black
b9b29525a6 Include the x86 specific traits file.
--HG--
extra : convert_revision : bcf448aedd832022527cc972f7a1f0433987c564
2007-03-05 12:21:20 +00:00
Gabe Black
9e93feea10 Stub x86 Fault class which just panics.
--HG--
extra : convert_revision : abfcf4005ec636b1e6c085515b63c1d8e69e3370
2007-03-05 12:20:34 +00:00
Gabe Black
385eb586ce A new file for x86 specific parameters. This could be implemented as a sim object?
--HG--
extra : convert_revision : 51757435bb0b20132f3ec5782db31382bb2cca18
2007-03-05 12:19:54 +00:00
Gabe Black
be29612fbe Add in a declaration of class Checkpoint rather than expecting it to come from some other include.
--HG--
extra : convert_revision : adbd4899508e3d30959a504a48402f01d1187099
2007-03-05 12:19:11 +00:00
Gabe Black
6a19b64de2 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : b585cea2221377eb2fceea8976c46a17c0034f51
2007-03-05 11:00:44 +00:00
Nathan Binkert
ba042842c6 Don't use the exact same name as a system header #define
--HG--
extra : convert_revision : 099e380395fc1fdaef993b019d3d4e596e8076c2
2007-03-04 19:26:49 -08:00
Ali Saidi
82874eefca Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
2007-03-03 19:03:22 -05:00
Ali Saidi
36f43ff6a5 Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-03-03 17:22:47 -05:00
Gabe Black
5498d52985 Filled in with basic x86 stuff. Some things are missing, wrong, or nonsensical for x86.
--HG--
extra : convert_revision : 2f7845db6d65b353985b474f7012cfbbaece6a39
2007-03-03 17:19:52 +00:00
Gabe Black
0150515ac3 Filled in with basic x86 information. Some things are missing, wrong, or non-sensical in x86.
--HG--
extra : convert_revision : bba78db3667e214c95bb127872d3fdf546619703
2007-03-03 17:18:29 +00:00
Gabe Black
10871b7342 Add build hooks for x86.
--HG--
extra : convert_revision : 438eb74f14e6ea60bab5012110f3946c9213786e
2007-03-03 16:01:48 +00:00
Gabe Black
23dc5099a4 Implement the _llseek syscall. It's Linux only, so we'll actually use the lseek syscall.
--HG--
extra : convert_revision : cccfd5efddbba527c6fb4e07ad2ab235a2670918
2007-03-03 03:34:55 +00:00
Gabe Black
477afcaf5b Fix some issues with 32 bit processes.
--HG--
extra : convert_revision : b01b38bbf185f2279134db4976a9bdb3e381a670
2007-03-03 03:34:54 +00:00
Ali Saidi
4e8d2d1593 make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads
src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
    make ldtw(a) Twin 32 bit load work correctly

--HG--
extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
2007-03-02 22:34:51 -05:00
Gabe Black
d8ada247f4 Forgot to commit this new file last earlier.
--HG--
extra : convert_revision : f2d80ae551b7e29426141d5c9fe355b43a0b9c7d
2007-03-02 14:43:27 +00:00
Gabe Black
ececf101c7 Make the m5 psuedo instructions use the BasicOperate format
--HG--
extra : convert_revision : f02da702ab9b99da124fac7e10a07386b04f3a0f
2007-02-28 16:49:17 +00:00
Gabe Black
eb57b4f214 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32

--HG--
extra : convert_revision : 88d1401f6e6b7c82344abef2c81b3c22bf6a0499
2007-02-28 16:39:42 +00:00
Gabe Black
29e5df890d Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running.
--HG--
extra : convert_revision : ea873f01c62234c0542f310cc143c6a7c76ade94
2007-02-28 16:36:38 +00:00
Gabe Black
99948060b2 The "hostname" variable isn't used in the process classes. It should be removed from the other ones as well.
--HG--
extra : convert_revision : 0c07534de42d6c32ac26d9e43709111e3ab30d57
2007-02-28 16:29:25 +00:00
Ali Saidi
f892608ff7 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : a4f80ce975a23ba9858e6bf2dbbfed8897dd1810
2007-02-24 22:10:06 -05:00
Ali Saidi
cf0e202cba make m5 readfile work on solaris... we can have a solaris regression soon!
src/arch/sparc/isa/decoder.isa:
    add readfile and break to sparc decoder
src/arch/sparc/isa/operands.isa:
    fix O0-O5 operands registers
util/m5/Makefile.sparc:
    Make sparc makefile compile a 64bit binary
util/m5/m5.c:
    readfile was in here twice, once will be sufficient I think
util/m5/m5op_sparc.S:
    implement readfile and debugbreak

--HG--
extra : convert_revision : 139b3f480ee6342b37b5642e072c8486d91a3944
2007-02-24 22:05:01 -05:00
Gabe Black
6ae4cae971 Ali and I both made the same change and we only need it once. I liked mine a little better.
--HG--
extra : convert_revision : 3a1b7856e6143ca089fd6e36492608377dfede19
2007-02-23 01:05:34 +00:00
Gabe Black
187cc99e4e Merge zizzer.eecs.umich.edu:/bk/newmem
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32

--HG--
extra : convert_revision : a7697ea8457a03318e3fcf34775bf3ecc4786e8a
2007-02-23 01:05:33 +00:00
Gabe Black
34b4722aee Make the m5 pseudo instructions only work in FS. Also, make sure any undefined opcodes in impdep2 (which in SE is all of them) trap with an illegal_instruction exception.
--HG--
extra : convert_revision : dd7848d0685e4cc6f5fd5e3b846a3f70b62ee30a
2007-02-22 13:17:51 +00:00
Ali Saidi
63fef6b011 fix se compiling oops
--HG--
extra : convert_revision : ce7ac94da0ed6bad457a8a9e4c949b0c3b09c2ae
2007-02-22 01:11:04 -05:00
Ali Saidi
f01f8f1be6 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 4105ebbeca59206bece27f229ee810d594fb4310
2007-02-21 21:06:29 -05:00
Ali Saidi
7a2ecf9e26 add pseduo instruction support for sparc
util/m5/Makefile.alpha:
    Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
    Make the makefile more reasonable
util/m5/Makefile.alpha:
    Remove authors from copyright.
util/m5/Makefile.alpha:
    Updated Authors from bk prs info
util/m5/Makefile.alpha:
    bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
    Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
    Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
    split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
    ivle and ivlb aren't used anymore
util/m5/m5op.h:
    stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
    move the op ids into their own header file since we can share them between sparc and alpha

--HG--
rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
2007-02-21 21:06:17 -05:00
Nathan Binkert
06ae2d0445 Fix compile issues on gcc 4.1.x related to namespaces.
This basically involves moving the builder code outside of any
namespace.  While we're at it, move a few braces outside of
a couple #if/#else/#endif blocks so it's easier to match up
the braces.

--HG--
extra : convert_revision : a7834532aadc63b0e0ff988dd5745049e02e6312
2007-02-21 16:42:16 -08:00
Nathan Binkert
5000c4d878 #include needed for compile
--HG--
extra : convert_revision : fda9ab0d04f77f27810018a8639d6ea8abb59326
2007-02-21 10:13:10 -08:00
Ali Saidi
bd367d4825 implement vtophys and 32bit gdb support
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/sparc/arguments.hh:
    move Copy* to vport since it's generic for all the ISAs
src/arch/sparc/isa_traits.hh:
    the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase
src/arch/sparc/pagetable.hh:
    add a class for getting bits out of the TteTag
src/arch/sparc/remote_gdb.cc:
    add 32bit support kinda.... If its 32 bit
src/arch/sparc/remote_gdb.hh:
    Add 32bit register offsets too.
src/arch/sparc/tlb.cc:
    cleanup generation of tsb pointers
src/arch/sparc/tlb.hh:
    add function to return tsb pointers for an address
    make lookup public so vtophys can use it
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
    write vtophys for sparc
src/base/bitfield.hh:
    return a mask of bits first->last
src/mem/vport.cc:
src/mem/vport.hh:
    move Copy* here since it's ISA generic

--HG--
extra : convert_revision : c42c331e396c0d51a2789029d8e232fe66995d0f
2007-02-18 19:57:46 -05:00
Ali Saidi
e8cd54e805 fixup remote gdb support for sparc fs
--HG--
extra : convert_revision : 5edf0ad492fe438d66bcf0ae469ef841cd71e157
2007-02-15 15:24:08 -05:00
Steve Reinhardt
f55fd68f88 Update MIPS ISA description to work with new write result interface
for store conditional.

--HG--
extra : convert_revision : 73efd2ca17994e0e19c08746441874a2ac8183af
2007-02-13 08:09:09 -08:00
Ali Saidi
ca5cd68df4 fix compiling problems
--HG--
extra : convert_revision : 9ecfd5a0a151c03503e42faf98240da12fd719b1
2007-02-13 10:07:50 -05:00
Ali Saidi
49a9378718 make hver match legion
--HG--
extra : convert_revision : 5bfe4b943ca5b3e30a7097a46cab4f93dadd714f
2007-02-12 13:58:03 -05:00
Ali Saidi
b9005f3562 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

src/cpu/simple/atomic.cc:
    merge steve's changes in.

--HG--
extra : convert_revision : a17eda37cd63c9380af6fe68b0aef4b1e1974231
2007-02-12 13:22:36 -05:00
Ali Saidi
b5a4d95811 rename store conditional stuff as extra data so it can be used for conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
    add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
    Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
    Make atomic memory ops atomic
    Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
    add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
    remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
    swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
    add a post access code block
src/arch/sparc/isa/includes.isa:
    need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
    add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    add support for twinloads
    add support for swap and conditional swap instructions
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
    Add support for atomic swap memory commands
src/mem/packet_access.hh:
    Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
    Add support for atomic swap memory commands
    Rename sc code to extradata

--HG--
extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
2007-02-12 13:06:30 -05:00
Steve Reinhardt
ad17b32651 Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 496428e23050122a8a0029e5fddea261bef5729e
2007-02-12 09:27:32 -08:00
Steve Reinhardt
f78bc80bd7 Move store conditional result checking from SimpleAtomicCpu write
function into Alpha ISA description.  write now just generically
returns a result value if the res pointer is non-null (which means
we can only provide a res pointer if we expect a valid result
value).

--HG--
extra : convert_revision : fb1c315515787f5fbbf7d1af7e428bdbfe8148b8
2007-02-12 09:26:47 -08:00
Ali Saidi
8ffd12e807 merge my index fix and lisa's fix
--HG--
extra : convert_revision : 5f2c7d46c96fa061bbfb66edf188d405ca600020
2007-02-06 18:47:42 -05:00
Ali Saidi
ebb6972dd3 more fp fixes
fix unaligned accesses in mmaped disk device

src/arch/sparc/isa/decoder.isa:
    get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
    move the cexec into the aexec field
src/cpu/exetrace.cc:
    copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
    fix unaligned accesses in the memory mapped disk device

--HG--
extra : convert_revision : aaa33096b08cf0563fe291d984a87493a117e528
2007-02-06 15:52:33 -05:00
Ali Saidi
ecef27f172 more sparc fixes
src/arch/sparc/isa/decoder.isa:
    fix rdgsr fault check
src/arch/sparc/tlb.cc:
    block asis are now supported

--HG--
extra : convert_revision : cf55d648d2c5184fab03b6fe057d0e33c1dfc393
2007-02-02 19:02:27 -05:00
Ali Saidi
665ddde57a make interrupt code serialize itself and fix indenting
--HG--
extra : convert_revision : d0bb23c7922568586b640084ac719e809cc8422f
2007-02-02 18:05:21 -05:00
Ali Saidi
592f35ac0f fix mostly floating point related
src/arch/sparc/floatregfile.cc:
    fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
    fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
    add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
    include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
    print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
    fix printing of float registers

--HG--
extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
2007-02-02 18:04:42 -05:00
Lisa Hsu
17cbfe55fd Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 62a0017a1147631513db7878f4e4d08fca776bc1
2007-02-01 15:35:26 -05:00
Lisa Hsu
1e8bbb81cb only increment numPosted if an interrupt of that type hasn't been posted before.
--HG--
extra : convert_revision : 6671c594b78d2e38449069157f39af96b81340f2
2007-02-01 15:34:52 -05:00
Ali Saidi
5c7192daed make sparc fs less chatty
src/SConscript:
    strip doesn't take a src and dest in solaris

--HG--
extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
2007-01-31 18:32:27 -05:00
Ali Saidi
36a1912bf0 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 276b640c5c5a51e88e9bd630960ad462d9f0cb8d
2007-01-30 18:27:16 -05:00
Ali Saidi
fc79ace502 Make SPARC checkpointing work
src/arch/sparc/floatregfile.cc:
    Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
    fix serialization for intreg
src/arch/sparc/miscregfile.cc:
    fix serialization from miscreg
src/arch/sparc/pagetable.cc:
    fix serialization for page table
src/arch/sparc/regfile.cc:
    need to serialize nnpc
src/arch/sparc/tlb.cc:
    write serialization code for tlb
src/cpu/base.cc:
    provide a way to find the thread number a context is
    serialize the instruction counter
src/cpu/base.hh:
    provide a way to find the thread number a context is
    and given a thread number find a context pointer
src/cpu/cpuevent.hh:
    provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
    nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
    Make findObj() work (it hasn't since we did the python conversion stuff)

--HG--
extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
2007-01-30 18:25:39 -05:00
Gabe Black
cf0ba1dfb0 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 7b332ee4c737206511d26db391117eb1fe5ea290
2007-01-30 16:12:47 -05:00
Gabe Black
efb14c585b Implemented fbfss and fbpfcc instructions, and cleaned up branch code a little.
src/arch/sparc/isa/base.isa:
    Added passesFpCondition function to help with fbfcc and fbpfcc instructions.
src/arch/sparc/isa/decoder.isa:
    Added fbfcc and fbpfcc instructions, and cleaned up branch code slightly.
src/arch/sparc/isa/formats/branch.isa:
    Minor cleanup.

--HG--
extra : convert_revision : 6586b46418f1f70bace41407f267fee30c657714
2007-01-30 16:12:38 -05:00
Ali Saidi
8bc4925775 change std::isnan() to a using namespace std and isnan(). We need a better way to do this.
--HG--
extra : convert_revision : 4f59ca8e6425db23f57a1f3f65a4874e483d0ecc
2007-01-30 14:43:25 -05:00
Ali Saidi
e82e5b5084 use std:: for isnan() and fix decoding of fcmpe*
--HG--
extra : convert_revision : 06be0f8572e26c3c7e761b482248304ce1afa038
2007-01-30 11:22:22 -05:00
Gabe Black
a4a87daad1 Make clearSingleStep in SPARC a warning, and rephrase the panic for setSingleStep
--HG--
extra : convert_revision : fde27a1faa6c03a24a4321a153dfa89a438f9a32
2007-01-30 02:44:24 -05:00
Gabe Black
e3fad2dcea Make the FpUnimpl format actually write the Fsr.
--HG--
extra : convert_revision : 84717cd3a8fa9fb85bd0693304e05ef475b05d07
2007-01-30 00:21:18 -05:00
Gabe Black
230fc0a0d1 Added FpUnimpl format for quad precision and other purposefully unimplemented floating point ops.
--HG--
extra : convert_revision : 356fec86c35560b20ea8eee80844602bbcec145f
2007-01-30 00:08:42 -05:00
Gabe Black
a8b8962a4d Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 0e4a54c21f32fec13deaf00b5d61c258007f172b
2007-01-29 22:57:18 -05:00
Gabe Black
4a16ea95c1 Fix the Frs?s operands to use single width by default, rather than double width.
--HG--
extra : convert_revision : 36137ee025dc5c79665b041b43bd89505715ca70
2007-01-29 22:54:28 -05:00
Gabe Black
1f7db14dd4 Add implementation for the fcmp instructions. These don't behave -quite- right with respect to quite NaNs, but hopefully we don't need to worry about the distinction.
--HG--
extra : convert_revision : 67b6583a20530b7a393aa04d0b71031d3c72ecdd
2007-01-29 22:52:54 -05:00
Gabe Black
a5cb9b51be Fix the FCMPCC bitfield.
--HG--
extra : convert_revision : d2c538e7f469bd12a80eb8585c78d5325d6e6141
2007-01-29 22:46:01 -05:00
Ali Saidi
7545b2b650 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 7b8b791815d1fb51cc7ad085307a640b2ee51642
2007-01-29 14:44:45 -05:00
Gabe Black
fc7e36553b Cleaned up disassembly a little.
--HG--
extra : convert_revision : 4665ac7760c9b78a1d7699ceeb541b694211a947
2007-01-29 10:49:59 -05:00
Gabe Black
44c6ca84c6 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 7bea2cb13e2de527134d98d4ee21a55dc4a7d1ad
2007-01-28 18:28:34 -05:00
Ali Saidi
b37b6e1708 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : e302dc4d7a20646bb0ea363127b2658a6d6e810c
2007-01-28 16:18:44 -05:00
Ali Saidi
7494aa8a14 make unimplemented ops fail
return correct traps for ua2005 fpops that aren't implemented in hw

--HG--
extra : convert_revision : 998fd43f77c5de7078bac1c6caab296b18c9366d
2007-01-28 15:42:01 -05:00
Ali Saidi
a729e4d4b8 fix comparing fp registers between legion and m5
make fp writes also chatty with the Sparc traceflag

src/arch/sparc/floatregfile.cc:
    make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
    fix comparing fp registers between legion and m5

--HG--
extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714
2007-01-28 15:30:14 -05:00
Gabe Black
0358ccee23 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
    Hand Merge

--HG--
extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c
2007-01-27 01:59:20 -05:00
Gabe Black
e41f54f97f Got rid of some DPRINTFs that were printing raw pointers.
--HG--
extra : convert_revision : a79f5ee225208338594e7c4ecf0a71fef941918c
2007-01-27 01:49:21 -05:00
Gabe Black
f48b22f986 Fixed up printReg so that control registers are printed by name. This is possible now becauase Ctrl_Base_DepTag gets added into control register numbers.
--HG--
extra : convert_revision : d6de3be277127547cd942769cd34a54a4ec8db32
2007-01-27 01:47:07 -05:00
Ali Saidi
5f51fe20de Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 53ee81b099930d4d827db99e2d944ffb8645c706
2007-01-26 18:57:35 -05:00
Ali Saidi
2939d7d061 Make Sparc traceflag even more chatty
some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct

src/arch/sparc/floatregfile.cc:
    Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
    add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
    some fixes to fp instructions to use the single precision registers
    fix smul again
    fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
    if this is an fp op emit fp check code
src/cpu/exetrace.cc:
    check fp regs as well as int regs
src/cpu/m5legion_interface.h:
    add fpregs to m5legion struct

--HG--
extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
2007-01-26 18:57:16 -05:00
Ali Saidi
6d9d0c68b5 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.suncc

--HG--
extra : convert_revision : 1706f6218abec7eb575dcff3ad4aef83894f64ab
2007-01-26 18:50:28 -05:00
Ali Saidi
fd8a4ff5a8 Merge zeep.pool:/z/saidi/work/m5.newmem
into  zeep.pool:/z/saidi/work/m5.suncc

--HG--
extra : convert_revision : 20f61a524a3b53fc0afcf53a24b5a1fe1d96f579
2007-01-26 18:49:40 -05:00
Ali Saidi
63fdabf191 make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
    Add code to detect compiler and choose cflags based on detected compiler
    Fix zlib check to work with suncc
src/SConscript:
    split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
    use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
    add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
    use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
    include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
    remove dangling comma
src/arch/sparc/system.cc:
    dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
    use std namespace for string ops
src/arch/sparc/utility.hh:
    no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
    dummy returns to for suncc front end
src/base/cprintf.hh:
    use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
    don't need to define hash for suncc
src/base/hostinfo.cc:
    need stdio.h for sprintf
src/base/loader/object_file.cc:
    munmap is in std namespace not null
src/base/misc.hh:
    use M5 generic noreturn macros
    use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
    we need file.h for file flags
src/base/random.cc:
    mess with include files to make suncc happy
src/base/remote_gdb.cc:
    malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
    use std namespace for floor
src/base/stats/text.cc:
    include math.h for rint (cmath won't work)
src/base/time.cc:
    use suncc version of ctime_r
src/base/time.hh:
    change macro to work with both gcc and suncc
src/base/timebuf.hh:
    include cstring from memset and use std::
src/base/trace.hh:
    change variadic macros to be normal format
src/cpu/SConscript:
    add dummy returns where appropriate
src/cpu/activity.cc:
    include cstring for memset
src/cpu/exetrace.hh:
    include cstring fro memcpy
src/cpu/simple/base.hh:
    add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
    add dummy return where appropriate
src/dev/ide_atareg.h:
    make define work for both gnuc and suncc
src/dev/io_device.hh:
    add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
    include cstring for string ops
src/dev/sparc/mm_disk.cc:
    add dummy return where appropriate
    include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
    Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
    cast hastSets to double for log() call
src/mem/physical.cc:
    cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
    make define work for suncc and gnuc

--HG--
extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-26 18:48:51 -05:00
Gabe Black
47b2aa6346 Fixed the number of integer registers. There are MaxGL+1 sets of globals, not just MaxGL.
--HG--
extra : convert_revision : 6fd090f112611db1e72a1f129dff03687d52930a
2007-01-26 16:38:29 -05:00
Lisa Hsu
c215d54aac Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 1b854ec7caa33d3009383754206b643494c4c42d
2007-01-26 12:51:24 -05:00
Lisa Hsu
202d7f62b9 eliminate cpu checkInterrupts bool, it is redundant and unnecessary.
--HG--
extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
2007-01-26 12:51:07 -05:00
Ali Saidi
8561c8366c fix smul and sdiv to sign extend, and handle overflow/underflow corretly
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start  on the first part of it when we come back

src/arch/sparc/isa/decoder.isa:
    fix smul and sdiv to sign extend, and handle overflow/underflow corretly
    Only allow writing/reading of 32 bits of Y
    Only allow writing/reading 32 bits of pc when pstate.am
    Put any loaded data on the first half of a micro-op in uReg0 so it can't
    overwrite the register we are using for address calculation
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Put any loaded data on the first half of a micro-op in uReg0 so it can't
    overwrite the register we are using for address calculation
src/arch/sparc/isa/includes.isa:
    Use limits for 32bit underflow/overflow detection
src/arch/sparc/tlb.cc:
    only erase a entry from the lookup table if it's valid
    Put in a temporary check to make sure that lookup table and tlb array stay in sync
src/arch/sparc/tlb_map.hh:
    add a print function to dump the tlb lookup table
src/cpu/simple/base.cc:
    if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
    so we start  on the first part of it when we come back

--HG--
extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4
2007-01-25 13:43:46 -05:00
Gabe Black
5407a6bc32 Fixed a warning that was breaking compilation.
--HG--
extra : convert_revision : 007e83ab452849ce527fe252148e7a1dc423c850
2007-01-25 01:13:56 -05:00
Gabe Black
5f50dfa5d0 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 2d7ae62a59b91d735bbac093f8a4ab542ea75eee
2007-01-24 19:57:36 -05:00
Ali Saidi
4301e4cd08 use pstate.am to mask off PC/NPC where it needs to +be
check writability of tlb cache entry before using
update tagaccess in places I forgot to
move the tlb privileged test up since it is higher priority

src/arch/sparc/faults.cc:
    save only 32 bits of PC/NPC if Pstate.am is set
src/arch/sparc/isa/decoder.isa:
    return only 32 bits of PC/NPC if Pstate.am is set
    increment cleanwin correctly
src/arch/sparc/tlb.cc:
    check writability of cache entry
    update tagaccess in a few more places
    move the privileged test up since it is higher priority
src/cpu/exetrace.cc:
    mask off upper bits of pc if pstate.am is set before comparing to legion

--HG--
extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c
2007-01-23 15:50:03 -05:00
Gabe Black
1352e55ceb Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmemo3

src/sim/byteswap.hh:
    Hand Merge

--HG--
extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8
2007-01-22 22:31:48 -08:00
Ali Saidi
5f662d451e clean up fault code a little bit
simplify and make complete some asi checks
implement all the twin asis and remove panic checks on their use
soft int is supported, so we don't need to print writes to it

src/arch/sparc/asi.cc:
    make AsiIsLittle() be all the little asis.
    Speed up AsiIsTwin() a bit
src/arch/sparc/faults.cc:
    clean up the do*Fault code.... Make it work like legion, in particular
    pstate.priv is left alone, not set to 0 like the spec says
src/arch/sparc/isa/decoder.isa:
    implement some more twin ASIs
src/arch/sparc/tlb.cc:
    All the twin asis are implemented, no need to say their not supported anymore
src/arch/sparc/ua2005.cc:
    softint is supported now, no more need to

--HG--
extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b
2007-01-22 21:55:43 -05:00
Ali Saidi
ddab4d756a Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 21e1bfa49a933f3b39bd2e7bcd873428f9d01a1b
2007-01-22 16:17:11 -05:00
Ali Saidi
e347b49a4e use writeTagAccess() function to unify writing of Tag access registers
Fix extracting of secondary context to shove into tag access register
properly sign extend va from 59 bits to 63 (SPARC VA hole)

--HG--
extra : convert_revision : 5d0c2b4db63338c31b2d29b4bb68f39e1d4f4c7b
2007-01-22 16:11:49 -05:00
Ali Saidi
a7072c19db make sure that page bits of VA on tlb insert are 0
--HG--
extra : convert_revision : f04af884687e9b8631e910cf62cd4a58d035c744
2007-01-21 20:02:41 -05:00
Ali Saidi
d8eeb2e0ff fix InterruptLevel code to return the correct level
(the bit positition that is set in softint)

--HG--
extra : convert_revision : ba0e1f4ec1f74aac64c3f9bb7eb1b771e17b013a
2007-01-20 23:12:32 -05:00
Ali Saidi
57d11578cf atually set all 64 bits of the retun value to 0
--HG--
extra : convert_revision : 77bfdf07a49d41a2392f429fdc632c1461ac504c
2007-01-20 23:10:43 -05:00
Ali Saidi
95e4a51c6c fix flushw implementation
--HG--
extra : convert_revision : 136b2bddc7cb70cde30e930ad3a13bd56c7162e1
2007-01-20 23:09:28 -05:00
Ali Saidi
ccd67ce44f Rearange tlb code to remove some duplicate
Sparc error register should return ull(0) since it's 64 bits
Fix PS1 pointer creation to use the ps1 page size rather than ps0

--HG--
extra : convert_revision : fb4ef4b90270c8db676ffe53578acfa3c244526e
2007-01-20 12:37:02 -05:00
Ali Saidi
6e0f1c6062 Spill and Fill handlers are actually n*4 + the start address
--HG--
extra : convert_revision : a42f01a84e4b7ba9e6029df50e1612d410a8ba22
2007-01-20 12:34:00 -05:00
Lisa Hsu
01c959aeaf Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
2007-01-19 21:34:21 -05:00
Lisa Hsu
f1aeaf7ceb some hstick and hintp changes.
src/arch/sparc/interrupts.hh:
    condition hstick matches on HINTP
src/arch/sparc/miscregfile.cc:
    implement HINTP
src/arch/sparc/ua2005.cc:
    don't post interrupt unless it is enabled.

--HG--
extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
2007-01-19 21:33:36 -05:00
Ali Saidi
ae0d8d1681 Allow ASI_LDTX_REAL
--HG--
extra : convert_revision : ba1af012ab8ac61a25058977cb7ec511eb2cf3cb
2007-01-17 18:36:12 -05:00
Ali Saidi
c8a2d602b1 do a linear search for matching tlb entries instead of using map because you could be mapping a larger page that intersects many
fix for lookup table to keep it consistant with tlb on a replace of a specific entry

--HG--
extra : convert_revision : 5a14fbcdcfc13156c63fa41ddeca474660143b32
2007-01-17 17:59:22 -05:00
Ali Saidi
8173a05eaf Implement reading writing of sync fault status register and address register
--HG--
extra : convert_revision : c2f60e49683446bcc3afdf911da172de0422b8ad
2007-01-17 13:09:26 -05:00
Ali Saidi
0584d5bd6c In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks
--HG--
extra : convert_revision : e7b21c56eadf4603ab03364741b00c9689492423
2007-01-16 19:06:33 -05:00
Ali Saidi
ecfd628ecd Modify ISA and staticInst to support a IsFirstMicroOp flag
Increment instruction count on first micro-op instead of last

src/arch/sparc/isa/decoder.isa:
    Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
    set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
    Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
    Add IsFirstMicroop flag to static insts

--HG--
extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
2007-01-16 19:06:05 -05:00
Lisa Hsu
5c9cbdbb45 Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge between ali and me.

--HG--
extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
2007-01-11 09:48:15 -05:00
Lisa Hsu
42535f5f53 ua2005.cc:
formatting/indentation for case statements

src/arch/sparc/ua2005.cc:
    formatting/indentation for case statements

--HG--
extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
2007-01-11 09:41:34 -05:00
Lisa Hsu
9f75c1c58f ua2005.cc:
i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

src/arch/sparc/ua2005.cc:
    i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

--HG--
extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
2007-01-11 09:29:03 -05:00
Lisa Hsu
d939060ec6 Add Trap Level Zero to interrupts, remove some unreachable code that I forgot to remove last time.
--HG--
extra : convert_revision : 74c4c4591be5a66c21077a6fc5f3f60b0ee9bcc1
2007-01-11 09:18:31 -05:00
Ali Saidi
9d04510869 bug fixes to get us to 145m instructions
src/arch/sparc/intregfile.cc:
    some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
    fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
    legion always returns du and dl set, so we need to emulate that for now at least

--HG--
extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8
2007-01-10 22:19:13 -05:00
Ali Saidi
28a83c6d1c quiet/remove some warnings
fix implementation of cwp manipulation
implement PS0 and PS1 IMMU asis

src/arch/sparc/miscregfile.cc:
    get rid of some warnings
    fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are
src/arch/sparc/tlb.cc:
    implement PS0 and PS1 IMMU access ASIs
src/arch/sparc/ua2005.cc:
    make warning less verbose

--HG--
extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
2007-01-09 22:20:38 -05:00