fix mostly floating point related
src/arch/sparc/floatregfile.cc:
fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
fix printing of float registers
--HG--
extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
This commit is contained in:
Ali Saidi
parent
5c7192daed
commit
592f35ac0f
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@ -69,22 +69,25 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
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switch(width)
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{
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case SingleWidth:
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float32_t result32;
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uint32_t result32;
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float32_t fresult32;
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memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
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result = htog(result32);
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DPRINTF(Sparc, "Read FP32 register %d = 0x%x\n", floatReg, result);
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result32 = htog(result32);
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memcpy(&fresult32, &result32, sizeof(result32));
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result = fresult32;
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DPRINTF(Sparc, "Read FP32 register %d = [%f]0x%x\n", floatReg, result, result32);
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break;
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case DoubleWidth:
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float64_t result64;
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uint64_t result64;
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float64_t fresult64;
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memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
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result = htog(result64);
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DPRINTF(Sparc, "Read FP64 register %d = 0x%x\n", floatReg, result);
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result64 = htog(result64);
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memcpy(&fresult64, &result64, sizeof(result64));
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result = fresult64;
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DPRINTF(Sparc, "Read FP64 register %d = [%f]0x%x\n", floatReg, result, result64);
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break;
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case QuadWidth:
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float128_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
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result = htog(result128);
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DPRINTF(Sparc, "Read FP128 register %d = 0x%x\n", floatReg, result);
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panic("Quad width FP not implemented.");
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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@ -113,10 +116,7 @@ FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
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DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result);
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break;
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case QuadWidth:
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uint64_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
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result = htog(result128);
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DPRINTF(Sparc, "Read FP128 bits register %d = 0x%x\n", floatReg, result);
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panic("Quad width FP not implemented.");
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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@ -132,15 +132,21 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
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uint32_t result32;
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uint64_t result64;
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float32_t fresult32;
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float64_t fresult64;
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switch(width)
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{
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case SingleWidth:
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result32 = gtoh((uint32_t)val);
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fresult32 = val;
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memcpy(&result32, &fresult32, sizeof(result32));
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result32 = gtoh(result32);
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memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
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DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32);
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break;
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case DoubleWidth:
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result64 = gtoh((uint64_t)val);
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fresult64 = val;
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memcpy(&result64, &fresult64, sizeof(result64));
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result64 = gtoh(result64);
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memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
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DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64);
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break;
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@ -718,7 +718,7 @@ decode OP default Unknown::unknown()
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0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
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}
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0x34: decode OPF{
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format BasicOperate{
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format FpBasic{
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0x01: fmovs({{
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Frds.uw = Frs2s.uw;
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//fsr.ftt = fsr.cexc = 0
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@ -765,7 +765,7 @@ decode OP default Unknown::unknown()
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0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
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0x43: FpUnimpl::faddq();
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0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
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0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
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0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }});
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0x47: FpUnimpl::fsubq();
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0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
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0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
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@ -776,26 +776,26 @@ decode OP default Unknown::unknown()
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0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
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0x6E: FpUnimpl::fdmulq();
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0x81: fstox({{
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Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
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Frd.sdw = static_cast<int64_t>(Frs2s.sf);
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}});
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0x82: fdtox({{
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Frd.df = (double)static_cast<int64_t>(Frs2.df);
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Frd.sdw = static_cast<int64_t>(Frs2.df);
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}});
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0x83: FpUnimpl::fqtox();
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0x84: fxtos({{
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Frds.sf = static_cast<float>((int64_t)Frs2.df);
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Frds.sf = static_cast<float>(Frs2.sdw);
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}});
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0x88: fxtod({{
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Frd.df = static_cast<double>((int64_t)Frs2.df);
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Frd.df = static_cast<double>(Frs2.sdw);
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}});
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0x8C: FpUnimpl::fxtoq();
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0xC4: fitos({{
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Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
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Frds.sf = static_cast<float>(Frs2s.sw);
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}});
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0xC6: fdtos({{Frds.sf = Frs2.df;}});
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0xC7: FpUnimpl::fqtos();
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0xC8: fitod({{
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Frd.df = static_cast<double>((int32_t)Frs2s.sf);
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Frd.df = static_cast<double>(Frs2s.sw);
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}});
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0xC9: fstod({{Frd.df = Frs2s.sf;}});
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0xCB: FpUnimpl::fqtod();
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@ -803,17 +803,25 @@ decode OP default Unknown::unknown()
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0xCD: FpUnimpl::fstoq();
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0xCE: FpUnimpl::fdtoq();
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0xD1: fstoi({{
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Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
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Frds.sw = static_cast<int32_t>(Frs2s.sf);
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float t = Frds.sw;
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if (t != Frs2s.sf)
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Fsr = insertBits(Fsr, 4,0, 0x01);
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Fsr |= Fsr<4:0> << 5;
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}});
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0xD2: fdtoi({{
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Frds.sf = (float)static_cast<int32_t>(Frs2.df);
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Frds.sw = static_cast<int32_t>(Frs2.df);
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double t = Frds.sw;
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if (t != Frs2.df)
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Fsr = insertBits(Fsr, 4,0, 0x01);
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Fsr |= Fsr<4:0> << 5;
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}});
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0xD3: FpUnimpl::fqtoi();
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default: FailUnimpl::fpop1();
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}
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}
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0x35: decode OPF{
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format BasicOperate{
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format FpBasic{
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0x51: fcmps({{
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uint8_t fcc;
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if(isnan(Frs1s) || isnan(Frs2s))
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@ -831,11 +839,11 @@ decode OP default Unknown::unknown()
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}});
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0x52: fcmpd({{
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uint8_t fcc;
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if(isnan(Frs1s) || isnan(Frs2s))
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if(isnan(Frs1) || isnan(Frs2))
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fcc = 3;
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else if(Frs1s < Frs2s)
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else if(Frs1 < Frs2)
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fcc = 1;
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else if(Frs1s > Frs2s)
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else if(Frs1 > Frs2)
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fcc = 2;
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else
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fcc = 0;
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@ -860,11 +868,11 @@ decode OP default Unknown::unknown()
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}});
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0x56: fcmped({{
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uint8_t fcc = 0;
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if(isnan(Frs1s) || isnan(Frs2s))
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if(isnan(Frs1) || isnan(Frs2))
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fault = new FpExceptionIEEE754;
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if(Frs1s < Frs2s)
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if(Frs1 < Frs2)
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fcc = 1;
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else if(Frs1s > Frs2s)
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else if(Frs1 > Frs2)
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fcc = 2;
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uint8_t firstbit = 10;
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if(FCMPCC)
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@ -960,24 +968,24 @@ decode OP default Unknown::unknown()
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0x55: FailUnimpl::fpsub16s();
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0x56: FailUnimpl::fpsub32();
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0x57: FailUnimpl::fpsub32s();
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0x60: BasicOperate::fzero({{Frd.df = 0;}});
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0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
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0x60: FpBasic::fzero({{Frd.df = 0;}});
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0x61: FpBasic::fzeros({{Frds.sf = 0;}});
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0x62: FailUnimpl::fnor();
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0x63: FailUnimpl::fnors();
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0x64: FailUnimpl::fandnot2();
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0x65: FailUnimpl::fandnot2s();
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0x66: BasicOperate::fnot2({{
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0x66: FpBasic::fnot2({{
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Frd.df = (double)(~((uint64_t)Frs2.df));
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}});
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0x67: BasicOperate::fnot2s({{
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0x67: FpBasic::fnot2s({{
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Frds.sf = (float)(~((uint32_t)Frs2s.sf));
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}});
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0x68: FailUnimpl::fandnot1();
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0x69: FailUnimpl::fandnot1s();
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0x6A: BasicOperate::fnot1({{
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0x6A: FpBasic::fnot1({{
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Frd.df = (double)(~((uint64_t)Frs1.df));
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}});
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0x6B: BasicOperate::fnot1s({{
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0x6B: FpBasic::fnot1s({{
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Frds.sf = (float)(~((uint32_t)Frs1s.sf));
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}});
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0x6C: FailUnimpl::fxor();
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@ -988,18 +996,18 @@ decode OP default Unknown::unknown()
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0x71: FailUnimpl::fands();
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0x72: FailUnimpl::fxnor();
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0x73: FailUnimpl::fxnors();
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0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
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0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
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0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}});
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0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}});
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0x76: FailUnimpl::fornot2();
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0x77: FailUnimpl::fornot2s();
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0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
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0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
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0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}});
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0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}});
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0x7A: FailUnimpl::fornot1();
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0x7B: FailUnimpl::fornot1s();
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0x7C: FailUnimpl::for();
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0x7D: FailUnimpl::fors();
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0x7E: BasicOperate::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
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0x7F: BasicOperate::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
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0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
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0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
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0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
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0x81: FailUnimpl::siam();
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}
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@ -1236,16 +1244,20 @@ decode OP default Unknown::unknown()
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Rd.uw = uReg0;}}, {{EXT_ASI}});
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format Trap {
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0x20: Load::ldf({{Frds.uw = Mem.uw;}});
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0x21: decode X {
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0x21: decode RD {
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0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
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0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
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default: FailUnimpl::ldfsrOther();
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}
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0x22: ldqf({{fault = new FpDisabled;}});
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0x23: Load::lddf({{Frd.udw = Mem.udw;}});
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0x24: Store::stf({{Mem.uw = Frds.uw;}});
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0x25: decode X {
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0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
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0x1: Store::stxfsr({{Mem.udw = Fsr;}});
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0x25: decode RD {
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0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;
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Fsr = insertBits(Fsr,16,14,0);}});
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0x1: Store::stxfsr({{Mem.udw = Fsr;
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Fsr = insertBits(Fsr,16,14,0);}});
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default: FailUnimpl::stfsrOther();
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}
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0x26: stqf({{fault = new FpDisabled;}});
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0x27: Store::stdf({{Mem.udw = Frd.udw;}});
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@ -103,3 +103,42 @@ def format BasicOperate(code, *flags) {{
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format FpBasic(code, *flags) {{
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fp_code = """
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Fsr = insertBits(Fsr,4,0,0);
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#if defined(__sun) || defined (__OpenBSD__)
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fp_rnd newrnd = FP_RN;
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switch (Fsr<31:30>) {
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case 0: newrnd = FP_RN; break;
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case 1: newrnd = FP_RZ; break;
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case 2: newrnd = FP_RP; break;
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case 3: newrnd = FP_RM; break;
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}
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fp_rnd oldrnd = fpsetround(newrnd);
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#else
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int newrnd = FE_TONEAREST;
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switch (Fsr<31:30>) {
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case 0: newrnd = FE_TONEAREST; break;
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case 1: newrnd = FE_TOWARDZERO; break;
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case 2: newrnd = FE_UPWARD; break;
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case 3: newrnd = FE_DOWNWARD; break;
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}
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int oldrnd = fegetround();
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fesetround(newrnd);
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#endif
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"""
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fp_code += code
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fp_code += """
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#if defined(__sun) || defined (__OpenBSD__)
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fpsetround(oldrnd);
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#else
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fesetround(oldrnd);
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#endif
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"""
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iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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@ -53,7 +53,7 @@ output decoder {{
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#include "cpu/thread_context.hh" // for Jump::branchTarget()
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#include "mem/packet.hh"
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#if defined(linux)
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#if defined(linux) || defined(__APPLE__)
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#include <fenv.h>
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#endif
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#include <algorithm>
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@ -62,9 +62,14 @@ using namespace SparcISA;
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}};
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output exec {{
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#if defined(linux)
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#if defined(linux) || defined(__APPLE__)
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#include <fenv.h>
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#endif
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#if defined(__sun) || defined (__OpenBSD__)
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#include <ieeefp.h>
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#endif
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#include <limits>
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#include <cmath>
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@ -232,6 +232,7 @@ MiscReg MiscRegFile::readReg(int miscReg)
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/** Floating Point Status Register */
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case MISCREG_FSR:
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DPRINTF(Sparc, "FSR read as: %#x\n", fsr);
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return fsr;
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case MISCREG_MMU_P_CONTEXT:
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@ -337,10 +338,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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case MISCREG_PCR:
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case MISCREG_PIC:
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panic("Performance Instrumentation not impl\n");
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/** Floating Point Status Register */
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case MISCREG_FSR:
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warn("Reading FSR Floating Point not implemented\n");
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break;
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case MISCREG_SOFTINT_CLR:
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case MISCREG_SOFTINT_SET:
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panic("Can read from softint clr/set\n");
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@ -488,6 +485,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
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/** Floating Point Status Register */
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case MISCREG_FSR:
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fsr = val;
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DPRINTF(Sparc, "FSR written with: %#x\n", fsr);
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break;
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case MISCREG_MMU_P_CONTEXT:
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@ -450,16 +450,13 @@ Trace::InstRecord::dump(ostream &outs)
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diffTlb = true;
|
||||
}
|
||||
|
||||
if ((diffPC || diffCC || diffInst || diffIntRegs ||
|
||||
if (diffPC || diffCC || diffInst || diffIntRegs ||
|
||||
diffFpRegs || diffTpc || diffTnpc || diffTstate ||
|
||||
diffTt || diffHpstate || diffHtstate || diffHtba ||
|
||||
diffPstate || diffY || diffCcr || diffTl || diffFsr ||
|
||||
diffGl || diffAsi || diffPil || diffCwp || diffCansave ||
|
||||
diffCanrestore || diffOtherwin || diffCleanwin || diffTlb)
|
||||
&& !((staticInst->machInst & 0xC1F80000) == 0x81D00000)
|
||||
&& !(((staticInst->machInst & 0xC0000000) == 0xC0000000)
|
||||
&& shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1)
|
||||
) {
|
||||
{
|
||||
|
||||
outs << "Differences found between M5 and Legion:";
|
||||
if (diffPC)
|
||||
|
|
@ -639,7 +636,7 @@ Trace::InstRecord::dump(ostream &outs)
|
|||
char label[8];
|
||||
sprintf(label, "%%f%d", x);
|
||||
printRegPair(outs, label,
|
||||
thread->readFloatRegBits(x,FloatRegFile::DoubleWidth),
|
||||
thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth),
|
||||
shared_data->fpregs[x]);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue