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make sparc fs less chatty

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src/SConscript:
    strip doesn't take a src and dest in solaris

--HG--
extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
This commit is contained in:
Ali Saidi 2007-01-31 18:32:27 -05:00
parent 36a1912bf0
commit 5c7192daed
3 changed files with 30 additions and 28 deletions
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5
src/SConscript
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@ -304,7 +304,10 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
newEnv.Program(bin, make_objs(sources, newEnv))
if strip:
stripped_bin = bin + '.stripped'
newEnv.Command(stripped_bin, bin, 'strip $SOURCE -o $TARGET')
if sys.platform == 'sunos5':
newEnv.Command(stripped_bin, bin, 'cp $SOURCE $TARGET; strip $TARGET')
else:
newEnv.Command(stripped_bin, bin, 'strip $SOURCE -o $TARGET')
bin = stripped_bin
targets = newEnv.Concat(exe, [bin, 'python/m5py.zip'])
newEnv.M5Binary = targets[0]

1
src/arch/sparc/tlb.cc
View file

@ -899,7 +899,6 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
break;
case ASI_SPARC_ERROR_STATUS_REG:
warn("returning 0 for SPARC ERROR regsiter read\n");
pkt->set((uint64_t)0);
break;
case ASI_HYP_SCRATCHPAD:

52
src/python/m5/objects/T1000.py
View file

@ -21,53 +21,53 @@ class T1000(Platform):
type = 'T1000'
system = Param.System(Parent.any, "system")
fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000,
warn_access="Accessing Clock Unit -- Unimplemented!")
fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
#warn_access="Accessing Clock Unit -- Unimplemented!")
fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
ret_data64=0x0000000000000000, update_data=False,
warn_access="Accessing Memory Banks -- Unimplemented!")
ret_data64=0x0000000000000000, update_data=False)
#warn_access="Accessing Memory Banks -- Unimplemented!")
fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000,
warn_access="Accessing IOB -- Unimplemented!")
fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000)
#warn_access="Accessing IOB -- Unimplemented!")
fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000,
warn_access="Accessing JBI -- Unimplemented!")
fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
#warn_access="Accessing JBI -- Unimplemented!")
fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
ret_data64=0x0000000000000001, update_data=True,
warn_access="Accessing L2 Cache Banks -- Unimplemented!")
ret_data64=0x0000000000000001, update_data=True)
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
ret_data64=0x0000000000000001, update_data=True,
warn_access="Accessing L2 Cache Banks -- Unimplemented!")
ret_data64=0x0000000000000001, update_data=True)
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
ret_data64=0x0000000000000001, update_data=True,
warn_access="Accessing L2 Cache Banks -- Unimplemented!")
ret_data64=0x0000000000000001, update_data=True)
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
ret_data64=0x0000000000000001, update_data=True,
warn_access="Accessing L2 Cache Banks -- Unimplemented!")
ret_data64=0x0000000000000001, update_data=True)
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
ret_data64=0x0000000000000000, update_data=True,
warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
ret_data64=0x0000000000000000, update_data=True)
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
ret_data64=0x0000000000000000, update_data=True,
warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
ret_data64=0x0000000000000000, update_data=True)
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
ret_data64=0x0000000000000000, update_data=True,
warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
ret_data64=0x0000000000000000, update_data=True)
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
ret_data64=0x0000000000000000, update_data=True,
warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
ret_data64=0x0000000000000000, update_data=True)
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000,
warn_access="Accessing SSI -- Unimplemented!")
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!")
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()