Ali Saidi 2939d7d061 Make Sparc traceflag even more chatty ... some fixes to fp instructions to use the single precision registers if this is an fp op emit fp check code add fpregs to m5legion struct src/arch/sparc/floatregfile.cc: Make Sparc traceflag even more chatty src/arch/sparc/isa/base.isa: add code to check if the fpu is enabled src/arch/sparc/isa/decoder.isa: some fixes to fp instructions to use the single precision registers fix smul again fix subc/subcc/subccc condition code setting src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/mem/util.isa: if this is an fp op emit fp check code src/cpu/exetrace.cc: check fp regs as well as int regs src/cpu/m5legion_interface.h: add fpregs to m5legion struct --HG-- extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232		2007-01-26 18:57:16 -05:00
..
alpha	pagetable.hh:	2007-01-08 20:50:45 -05:00
mips	Merge zizzer:/bk/sparcfs	2006-12-15 13:27:53 -05:00
sparc	Make Sparc traceflag even more chatty	2007-01-26 18:57:16 -05:00
isa_parser.py	Merge zizzer:/bk/newmem	2006-12-12 21:19:51 -05:00
isa_specific.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
SConscript	Add support for mmapped iprs to atomic cpu	2006-11-29 17:11:10 -05:00