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fix comparing fp registers between legion and m5

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make fp writes also chatty with the Sparc traceflag

src/arch/sparc/floatregfile.cc:
    make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
    fix comparing fp registers between legion and m5

--HG--
extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714
This commit is contained in:
Ali Saidi 2007-01-28 15:30:14 -05:00
parent f9a341f8e7
commit a729e4d4b8
2 changed files with 5 additions and 1 deletions
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4
src/arch/sparc/floatregfile.cc
View file

@ -137,10 +137,12 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
case SingleWidth:
result32 = gtoh((uint32_t)val);
memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32);
break;
case DoubleWidth:
result64 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64);
break;
case QuadWidth:
panic("Quad width FP not implemented.");
@ -163,10 +165,12 @@ Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
case SingleWidth:
result32 = gtoh((uint32_t)val);
memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result32);
break;
case DoubleWidth:
result64 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result64);
break;
case QuadWidth:
panic("Quad width FP not implemented.");

2
src/cpu/exetrace.cc
View file

@ -362,7 +362,7 @@ Trace::InstRecord::dump(ostream &outs)
}
}
for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
if (thread->readFloatRegBits(i,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
diffFpRegs = true;
}
}