Panic if any CMT registers are accessed
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add CMT ASI registers src/arch/sparc/tlb.cc: Panic if any of the CMT registers are being accessed --HG-- extra : convert_revision : b9a94281e2074a576ac21d042b756950d509e758
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@ -247,7 +247,8 @@ namespace SparcISA
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bool AsiIsCmt(ASI asi)
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{
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return
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(asi == ASI_CMT_PER_STRAND);
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(asi == ASI_CMT_PER_STRAND) ||
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(asi == ASI_CMT_SHARED);
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}
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bool AsiIsQueue(ASI asi)
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@ -295,7 +296,8 @@ namespace SparcISA
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bool AsiIsReg(ASI asi)
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{
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return AsiIsMmu(asi) || AsiIsScratchPad(asi) ||
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AsiIsSparcError(asi) || AsiIsInterrupt(asi);
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AsiIsSparcError(asi) || AsiIsInterrupt(asi)
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|| AsiIsCmt(asi);
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}
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bool AsiIsSparcError(ASI asi)
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@ -115,6 +115,7 @@ namespace SparcISA
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ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E,
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ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
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ASI_STREAM_MA = 0x40,
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ASI_CMT_SHARED = 0x41,
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//0x41 implementation dependent
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ASI_SPARC_BIST_CONTROL = 0x42,
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ASI_INST_MASK_REG = 0x42,
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@ -693,6 +693,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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if (AsiIsPartialStore(asi))
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panic("Partial Store ASIs not supported\n");
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if (AsiIsCmt(asi))
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panic("Cmt ASI registers not implmented\n");
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if (AsiIsInterrupt(asi))
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goto handleIntRegAccess;
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if (AsiIsMmu(asi))
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