more sparc fixes
src/arch/sparc/isa/decoder.isa: fix rdgsr fault check src/arch/sparc/tlb.cc: block asis are now supported --HG-- extra : convert_revision : cf55d648d2c5184fab03b6fe057d0e33c1dfc393
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@ -479,10 +479,10 @@ decode OP default Unknown::unknown()
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0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
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//0x12 should cause an illegal instruction exception
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0x13: NoPriv::rdgsr({{
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if(Fprs<2:> == 0 || Pstate<4:> == 0)
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Rd = Gsr;
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else
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fault = new FpDisabled;
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fault = checkFpEnableFault(xc);
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if (fault)
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return fault;
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Rd = Gsr;
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}});
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//0x14-0x15 should cause an illegal instruction exception
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0x16: Priv::rdsoftint({{Rd = Softint;}});
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@ -668,8 +668,6 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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if (!implicit && asi != ASI_P && asi != ASI_S) {
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if (AsiIsLittle(asi))
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panic("Little Endian ASIs not supported\n");
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if (AsiIsBlock(asi))
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panic("Block ASIs not supported\n");
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if (AsiIsNoFault(asi))
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panic("No Fault ASIs not supported\n");
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@ -688,7 +686,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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goto handleSparcErrorRegAccess;
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if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
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!AsiIsTwin(asi))
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!AsiIsTwin(asi) && !AsiIsBlock(asi))
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panic("Accessing ASI %#X. Should we?\n", asi);
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}
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