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Merge zizzer:/bk/newmem

Browse source 
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 0e4a54c21f32fec13deaf00b5d61c258007f172b
This commit is contained in:
Gabe Black 2007-01-29 22:57:18 -05:00
commit a8b8962a4d
3 changed files with 68 additions and 6 deletions
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4
src/arch/sparc/isa/bitfields.isa
View file

@ -1,4 +1,4 @@
// Copyright (c) 2006 The Regents of The University of Michigan
// Copyright (c) 2006-2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@ -38,7 +38,7 @@
def bitfield A <29>;
def bitfield BPCC <21:20>; // for BPcc & FBPcc
def bitfield FCMPCC <26:56>; // for FCMP & FCMPEa
def bitfield FCMPCC <26:25>; // for FCMP & FCMPEa
def bitfield FMOVCC <13:11>; // for FMOVcc
def bitfield CC <12:11>; // for MOVcc & Tcc
def bitfield MOVCC3 <18>; // also for MOVcc

64
src/arch/sparc/isa/decoder.isa
View file

@ -734,7 +734,69 @@ decode OP default Unknown::unknown()
default: FailUnimpl::fpop1();
}
}
0x35: Trap::fpop2({{fault = new FpDisabled;}});
0x35: decode OPF{
format BasicOperate{
0x51: fcmps({{
uint8_t fcc;
if(isnan(Frs1s) || isnan(Frs2s))
fcc = 3;
else if(Frs1s < Frs2s)
fcc = 1;
else if(Frs1s > Frs2s)
fcc = 2;
else
fcc = 0;
uint8_t firstbit = 10;
if(FCMPCC)
firstbit = FCMPCC * 2 + 30;
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
}});
0x52: fcmpd({{
uint8_t fcc;
if(isnan(Frs1s) || isnan(Frs2s))
fcc = 3;
else if(Frs1s < Frs2s)
fcc = 1;
else if(Frs1s > Frs2s)
fcc = 2;
else
fcc = 0;
uint8_t firstbit = 10;
if(FCMPCC)
firstbit = FCMPCC * 2 + 30;
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
}});
0x53: Trap::fcmpq({{fault = new FpExceptionOther;}});
0x54: fcmpes({{
uint8_t fcc = 0;
if(isnan(Frs1s) || isnan(Frs2s))
fault = new FpExceptionIEEE754;
if(Frs1s < Frs2s)
fcc = 1;
else if(Frs1s > Frs2s)
fcc = 2;
uint8_t firstbit = 10;
if(FCMPCC)
firstbit = FCMPCC * 2 + 30;
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
}});
0x55: fcmped({{
uint8_t fcc = 0;
if(isnan(Frs1s) || isnan(Frs2s))
fault = new FpExceptionIEEE754;
if(Frs1s < Frs2s)
fcc = 1;
else if(Frs1s > Frs2s)
fcc = 2;
uint8_t firstbit = 10;
if(FCMPCC)
firstbit = FCMPCC * 2 + 30;
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
}});
0x56: Trap::fcmpeq({{fault = new FpExceptionOther;}});
default: FailUnimpl::fpop2();
}
}
//This used to be just impdep1, but now it's a whole bunch
//of instructions
0x36: decode OPF{

6
src/arch/sparc/isa/operands.isa
View file

@ -1,4 +1,4 @@
// Copyright (c) 2006 The Regents of The University of Michigan
// Copyright (c) 2006-2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@ -88,9 +88,9 @@ def operands {{
'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),