Merge zizzer:/bk/newmem

into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 1b854ec7caa33d3009383754206b643494c4c42d
This commit is contained in:
Lisa Hsu 2007-01-26 12:51:24 -05:00
commit c215d54aac
10 changed files with 5 additions and 36 deletions

View file

@ -94,8 +94,6 @@ AlphaISA::processInterrupts(CPU *cpu)
int ipl = 0;
int summary = 0;
cpu->checkInterrupts = false;
if (cpu->readMiscReg(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
@ -155,8 +153,6 @@ SimpleThread::hwrei()
if (!misspeculating()) {
if (kernelStats)
kernelStats->hwrei();
cpu->checkInterrupts = true;
}
// FIXME: XXX check for interrupts? XXX

View file

@ -48,7 +48,6 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
case MISCREG_SOFTINT_CLR:
return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
case MISCREG_SOFTINT_SET:
tc->getCpuPtr()->checkInterrupts = true;
tc->getCpuPtr()->post_interrupt(soft_interrupt);
return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
@ -78,15 +77,9 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
break;
case MISCREG_PSTATE:
if (val & PSTATE::ie && !(pstate & PSTATE::ie)) {
tc->getCpuPtr()->checkInterrupts = true;
}
setReg(miscReg, val);
case MISCREG_PIL:
if (val < pil) {
tc->getCpuPtr()->checkInterrupts = true;
}
setReg(miscReg, val);
break;
@ -110,7 +103,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
setReg(miscReg, val);
tc->getCpuPtr()->checkInterrupts = true;
//do something to post mondo interrupt
break;
case MISCREG_HSTICK_CMPR:
@ -206,7 +199,6 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
(stick_cmpr & mask(63)));
if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
tc->getCpuPtr()->post_interrupt(soft_interrupt);
tc->getCpuPtr()->checkInterrupts = true;
setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
}
} else
@ -230,7 +222,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
setRegWithEffect(MISCREG_HINTP, 1, tc);
tc->getCpuPtr()->post_interrupt(hstick_match);
tc->getCpuPtr()->checkInterrupts = true;
}
// Need to do something to cause interrupt to happen here !!! @todo
} else

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@ -96,7 +96,7 @@ CPUProgressEvent::description()
#if FULL_SYSTEM
BaseCPU::BaseCPU(Params *p)
: MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true),
: MemObject(p->name), clock(p->clock), instCnt(0),
params(p), number_of_threads(p->numberOfThreads), system(p->system),
phase(p->phase)
#else
@ -334,7 +334,6 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
#if FULL_SYSTEM
interrupts = oldCPU->interrupts;
checkInterrupts = oldCPU->checkInterrupts;
for (int i = 0; i < threadContexts.size(); ++i)
threadContexts[i]->profileClear();
@ -371,7 +370,6 @@ BaseCPU::post_interrupt(int int_type)
void
BaseCPU::post_interrupt(int int_num, int index)
{
checkInterrupts = true;
interrupts.post(int_num, index);
}

View file

@ -106,7 +106,6 @@ class BaseCPU : public MemObject
virtual void post_interrupt(int int_num, int index);
virtual void clear_interrupt(int int_num, int index);
virtual void clear_interrupts();
bool checkInterrupts;
bool check_interrupts(ThreadContext * tc) const
{ return interrupts.check_interrupts(tc); }

View file

@ -217,8 +217,6 @@ AlphaO3CPU<Impl>::hwrei(unsigned tid)
this->thread[tid]->kernelStats->hwrei();
this->checkInterrupts = true;
// FIXME: XXX check for interrupts? XXX
return NoFault;
}
@ -270,7 +268,6 @@ AlphaO3CPU<Impl>::processInterrupts(Fault interrupt)
this->interrupts.updateIntrInfo(this->threadContexts[0]);
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
this->checkInterrupts = false;
this->trap(interrupt, 0);
}

View file

@ -671,8 +671,7 @@ DefaultCommit<Impl>::commit()
} else {
DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
}
} else if (cpu->checkInterrupts &&
cpu->check_interrupts(cpu->tcBase(0)) &&
} else if (cpu->check_interrupts(cpu->tcBase(0)) &&
commitStatus[0] != TrapPending &&
!trapSquash[0] &&
!tcSquash[0]) {

View file

@ -245,7 +245,6 @@ SparcO3CPU<Impl>::processInterrupts(Fault interrupt)
this->interrupts.updateIntrInfo(this->threadContexts[0]);
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
this->checkInterrupts = false;
this->trap(interrupt, 0);
}

View file

@ -182,10 +182,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
globalSeqNum = 1;
#if FULL_SYSTEM
checkInterrupts = false;
#endif
lockFlag = 0;
// Setup rename table, initializing all values to ready.
@ -684,8 +680,6 @@ OzoneCPU<Impl>::hwrei()
lockAddrList.clear();
thread.kernelStats->hwrei();
checkInterrupts = true;
// FIXME: XXX check for interrupts? XXX
return NoFault;
}
@ -704,7 +698,6 @@ OzoneCPU<Impl>::processInterrupts()
if (interrupt != NoFault) {
this->interrupts.updateIntrInfo(thread.getTC());
this->checkInterrupts = false;
interrupt->invoke(thread.getTC());
}
}

View file

@ -88,7 +88,6 @@ InorderBackEnd<Impl>::checkInterrupts()
int ipl = 0;
int summary = 0;
cpu->checkInterrupts = false;
if (thread->readMiscReg(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
@ -151,8 +150,7 @@ InorderBackEnd<Impl>::tick()
// I'm waiting for it to drain. (for now just squash)
#if FULL_SYSTEM
if (interruptBlocked ||
(cpu->checkInterrupts &&
cpu->check_interrupts(tc))) {
cpu->check_interrupts(tc)) {
if (!robEmpty()) {
interruptBlocked = true;
//AlphaDep

View file

@ -311,12 +311,11 @@ void
BaseSimpleCPU::checkForInterrupts()
{
#if FULL_SYSTEM
if (checkInterrupts && check_interrupts(tc)) {
if (check_interrupts(tc)) {
Fault interrupt = interrupts.getInterrupt(tc);
if (interrupt != NoFault) {
interrupts.updateIntrInfo(tc);
checkInterrupts = false;
interrupt->invoke(tc);
}
}