sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
9537 commits 2 branches 0 tags 204 MiB
Commit graph

28 commits

Author SHA1 Message Date
Ali Saidi bd31a5dc18 stats: update regressions for o3 changes in renaming and translation. 2013-02-15 17:40:14 -05:00
Andreas Hansson fce3433b2e stats: Update stats for regressions using SimpleDDR3 
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
 2013-01-31 07:49:16 -05:00
Nilay Vaish 9bc132e473 regressions: update stats due to branch predictor changes 
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
 2013-01-24 12:29:00 -06:00
Ali Saidi fbeced6135 stats: update stats for previous six changes 2013-01-08 08:54:16 -05:00
Ali Saidi 9f15510c2c stats: update stats for previous changes. 2013-01-07 13:05:54 -05:00
Nilay Vaish 5ebe3210d8 regressions: stats update due to decoder changes 2013-01-04 19:00:48 -06:00
Ali Saidi 1dbf9bb4ca update stats for preceeding changes 2012-11-02 11:50:06 -05:00
Andreas Hansson b387d8e213 stats: Update the stats to reflect the 1GHz default system clock 
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
 2012-10-25 13:15:59 -04:00
Andreas Hansson 8fe556338d stats: Update stats to reflect use of SimpleDRAM 
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
 2012-10-25 13:14:42 -04:00
Andreas Hansson a4329af937 stats: Update stats for DMA port send 
This patch updates the stats after removing the zero-time send used in
the DMA port.
 2012-10-23 04:49:48 -04:00
Andreas Hansson d52adc4eb6 Stats: Update stats for cache timings in cycles 
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
 2012-10-15 08:12:21 -04:00
Andreas Hansson 54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width 
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
 2012-10-15 08:09:54 -04:00
Andreas Hansson a850fc916f Stats: Update stats for use of two-level builder 
This patch updates the name of the l2 stats.
 2012-10-15 08:08:06 -04:00
Ali Saidi 91e74beee6 ARM: update stats for bp and squash fixes. 2012-09-25 11:49:41 -05:00
Andreas Hansson d2b57a7473 Stats: Update stats to reflect SimpleMemory bandwidth 
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
 2012-09-18 10:30:04 -04:00
Andreas Hansson ae1652b813 Stats: Remove the reference stats that are no longer present 
This patch simply removes the commitCommittedInsts and
commitCommittedOps from the reference statistics, following their
removal from the CPU.
 2012-09-13 08:02:55 -04:00
Andreas Hansson d628344574 Device: Update stats for PIO and PCI latency change 
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
 2012-09-10 11:57:37 -04:00
Andreas Hansson fb5dd28420 Checker: Bump the realview-o3-checker regression 
This patch bumps the stats for the realview-o3-checker after fixing
the checker CPU in the previous patch.
 2012-08-28 14:30:25 -04:00
Ali Saidi b1a58933e0 stats: update stats for icache change not allowing dirty data 2012-07-27 16:08:05 -04:00
Andreas Hansson fda338f8d3 Stats: Updates due to bus changes 
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
 2012-07-09 12:35:41 -04:00
Ali Saidi 3965ecc36b Stats: Update stats for RAS and LRU fixes. 2012-06-29 11:19:03 -04:00
Ali Saidi c49e739352 all: Update stats for memory per master and total fix. 2012-06-05 01:23:16 -04:00
Ali Saidi e62beaaa8f ARM: update stats for clock frequency fix. 2012-05-10 18:04:29 -05:00
Nathan Binkert 4a644767c5 stats: update stats for no_value -> nan 
Lots of accumulated older changes too.
 2012-05-09 11:52:14 -07:00
Ali Saidi 3c666083c6 ARM: Update stats for IT and conditional branch changes 2012-03-21 10:36:45 -05:00
Ali Saidi 470051345a ARM: Update stats for CBNZ fix. 2012-03-09 15:33:07 -05:00
Ali Saidi 927bba9d60 ARM: Update stats for valgrind fix and replace config.inis which are out of date. 2012-03-09 09:59:29 -05:00
Geoffrey Blake da0d67c3d6 CheckerCPU: Make some basic regression tests for CheckerCPU 
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
 2012-03-09 09:59:28 -05:00