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81 commits

Author SHA1 Message Date
Nilay Vaish
a5a2b9ecbd X86 Regressions: Update stats due to fence instruction 2012-01-10 09:59:01 -06:00
Ali Saidi
d1dd7a24db imported patch ext/stats_updates.patch 
--HG--
extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba
 2011-12-01 00:15:23 -08:00
Ali Saidi
28a2236ec1 O3: Update stats for new ordering fix. 2011-09-13 12:58:09 -04:00
Ali Saidi
999cd8aef5 StoreSet: Update stats for store-set clearing 2011-08-19 15:08:08 -05:00
Ali Saidi
f125ef22b9 O3: Update stats for LSQ changes. 2011-08-19 15:08:06 -05:00
Ali Saidi
3ebfe2eb01 O3: Update stats for fetch and bp changes. 2011-07-10 12:56:09 -05:00
Korey Sewell
b5736ba4ef alpha:o3:simple: update simout/err files 
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning

Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
 2011-06-20 18:57:14 -04:00
Korey Sewell
55dce6419d inorder: update SE regressions 2011-06-19 21:43:42 -04:00
Ali Saidi
5d5b0f49cc Stats: Update stats for minor O3 changes below. 2011-05-23 10:59:13 -05:00
Ali Saidi
44e599a1a4 ARM: Fix up stats for previous changes to condition codes 2011-05-13 17:29:27 -05:00
Nathan Binkert
a7e27f9a82 tests: updates for stat name change 2011-04-22 10:18:51 -07:00
Nathan Binkert
8c1563096c tests: update stats for name changes 2011-04-19 18:45:23 -07:00
Ali Saidi
d50d0152d0 ARM: Fix stats for ARM_SE checkpoint restore fix. 
Register reads/writes done in startup() count against the stats while they
don't count if done in initState().
 2011-04-12 16:09:20 -04:00
Ali Saidi
b20e92e1ca ARM: Update stats for previous changes. 2011-04-04 11:42:31 -05:00
Ali Saidi
1114be4b78 O3: Update stats for memory order violation checking patch. 2011-04-04 11:42:25 -05:00
Ali Saidi
63eb337b3b ARM: Update stats for the previous changes and add ARM_FS/O3 regression. 2011-03-17 19:20:22 -05:00
Korey Sewell
8135b81ae4 inorder: bzip2 regression update 2011-02-27 14:17:26 -05:00
Korey Sewell
72fb282ab1 inorder: add 00.gzip and 60.bzip2 regression tests 2011-02-23 16:35:25 -05:00
Ali Saidi
73603c2b17 ARM: Update regression tests for preceeding changes. 2011-02-23 15:10:50 -06:00
Gabe Black
44306e8114 X86: Update stats now that the dest reg isn't read unnecessarily to set flags. 2011-02-13 17:45:30 -08:00
Gabe Black
b046f3feb6 X86: Update stats for the reduced register reads. 2011-02-13 17:44:32 -08:00
Gabe Black
0851580aad Stats: Re update stats. 2011-02-07 19:23:13 -08:00
Gabe Black
54f88d84c2 Stats: Update the x86 stats to reflect changing stupd to a store and update. 2011-02-02 19:56:49 -08:00
Ali Saidi
f7885b8f26 ARM/O3: Add regressions for ARM w/ O3 CPU. 2011-01-18 16:30:06 -06:00
Ali Saidi
9b67f3723e Stats: Update stats for previous set of patches. 2011-01-18 16:30:06 -06:00
Ali Saidi
371110fb0a Regressions: Update regressions for SIMD opclass changes 2010-11-15 14:04:05 -06:00
Ali Saidi
06c5283930 ARM: Update SE stats for TLB stats additions 2010-11-08 13:59:35 -06:00
Ali Saidi
b4b6a2338a ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads. 2010-11-08 13:58:24 -06:00
Steve Reinhardt
13a15c55a4 stats: update stats for previous cset 
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
 2010-09-21 23:07:35 -07:00
Steve Reinhardt
9e45ada171 stats: update stats for preceding coherence changes 
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
 2010-09-09 14:40:19 -04:00
Ali Saidi
e6d3fe8a0c ARM: Update regression tests for ldr/str microcode changes. 2010-08-25 19:10:42 -05:00
Steve Reinhardt
0f8b5afd7a tests: update reference config.ini files for previous cset 
Rename 'responder_set' to 'use_default_range'.
 2010-08-17 05:06:22 -07:00
Ali Saidi
1b73376b0b ARM: Add regression tests 2010-07-27 01:03:44 -04:00
m5test
744b59d6de tests: Update O3 ref outputs to reflect Lisa's dist format change. 2010-06-06 18:39:10 -04:00
Ali Saidi
a990335b32 BPRED: Update one missing regression 2010-05-19 00:36:05 -04:00
Gabe Black
8b0c83008e X86: Update stats for the updated auxilliary vectors. 2010-05-03 00:45:01 -07:00
Lisa Hsu
ee20a7c0bd stats: update stats for the changes I pushed re: shared cache occupancy 2010-02-25 10:08:41 -08:00
Nathan Binkert
14b5169750 tests: update statistics for change caused by vsyscall support in x86 
Caused by a slight change in memory layout.
 2009-11-08 20:15:23 -08:00
Nathan Binkert
5fe0762ee4 tests: update test for slight change due to the change in brk. 2009-10-24 10:53:58 -07:00
Gabe Black
bcfc4178f5 X86: Update the stats for the slightly lengthened cmov. 2009-08-08 17:23:25 -07:00
Nathan Binkert
e3e509b31a tests: stats outputs now include CDFs, update tests that use those so they're easier to diff 2009-07-06 15:49:48 -07:00
Nathan Binkert
567cab6859 stats: update reference outputs now that compatibility is gone 
Because of the initialization bug, it wasn't consistent anyway.
 2009-04-22 10:25:17 -07:00
Steve Reinhardt
7b40c36fbd Update stats for new single bad-address responder. 
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
 2009-04-22 01:55:52 -04:00
Gabe Black
b4ad233c0c X86: Update the stats for the fix for CPUID. 2009-04-19 03:14:33 -07:00
Steve Reinhardt
48d4ca522a Update stats after elimination of Unallocated state. 
Somehow ending threads with halt() instead of deallocate()
reduces the squash count on o3 by 1 (and a few other
similarly trivial changes).
 2009-04-15 13:13:58 -07:00
Nathan Binkert
374ba9bae3 tests: update tests for TLB unification 2009-04-08 22:21:30 -07:00
Nathan Binkert
5cf0605766 tests: update tests because of changes in stat names and in the stats package 2009-03-07 14:30:55 -08:00
Gabe Black
1bfab291f1 CPU: Update stats now that there's no fetch in the middle of macroops. 2009-02-25 10:18:45 -08:00
Gabe Black
f02df8cb74 X86: Update stats for in place TLB miss handling. 2009-02-25 10:16:29 -08:00
Steve Reinhardt
89ea323250 Update stats for new prefetching fixes. 
Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.
 2009-02-16 12:09:45 -05:00