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gem5/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt

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add SMT hello world test - 2 threads --HG-- extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df
2006-10-06 10:23:27 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_seconds 0.000025 # Number of seconds simulated
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_ticks 24760000 # Number of ticks simulated
final_tick 24760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
add SMT hello world test - 2 threads --HG-- extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df
2006-10-06 10:23:27 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
host_inst_rate 82189 # Simulator instruction rate (inst/s)
host_op_rate 82182 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 159657472 # Simulator tick rate (ticks/s)
host_mem_usage 295960 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_insts 12744 # Number of instructions simulated
sim_ops 12744 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu.inst 40576 # Number of bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.bytes_read::cpu.data 22144 # Number of bytes read from this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::total 62720 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 40576 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 40576 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 634 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.num_reads::cpu.data 346 # Number of read requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.num_reads::total 980 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1638772213 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 894345719 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2533117932 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1638772213 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1638772213 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1638772213 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 894345719 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2533117932 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 980 # Number of read requests accepted
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readBursts 980 # Number of DRAM read bursts, including those serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytesReadDRAM 62720 # Total number of bytes read from DRAM
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytesReadSys 62720 # Total read bytes from the system interface side
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.perBankRdBursts::0 83 # Per bank write bursts
system.physmem.perBankRdBursts::1 155 # Per bank write bursts
system.physmem.perBankRdBursts::2 77 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::3 59 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::4 88 # Per bank write bursts
system.physmem.perBankRdBursts::5 49 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::6 33 # Per bank write bursts
system.physmem.perBankRdBursts::7 50 # Per bank write bursts
system.physmem.perBankRdBursts::8 42 # Per bank write bursts
system.physmem.perBankRdBursts::9 39 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::10 30 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::11 34 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::13 120 # Per bank write bursts
system.physmem.perBankRdBursts::14 69 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::15 37 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.totGap 24609000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readPktSize::6 980 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 324 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 194 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 31 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 289.971564 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 183.051447 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 289.757171 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 60 28.44% 61.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 22 10.43% 71.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 12 5.69% 77.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 14 6.64% 83.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 12 5.69% 89.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3 1.42% 91.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 8 3.79% 94.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 5.21% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation
system.physmem.totQLat 12705250 # Total ticks spent queuing
system.physmem.totMemAccLat 31080250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4900000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12964.54 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgMemAccLat 31714.54 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2533.12 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgRdBWSys 2533.12 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 19.79 # Data bus utilization in percentage
system.physmem.busUtilRead 19.79 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgRdQLen 2.43 # Average read queue length when enqueuing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readRowHits 761 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readRowHitRate 77.65 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgGap 25111.22 # Average gap between requests
system.physmem.pageHitRate 77.65 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 861840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 470250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4539600 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 23543775 # Total energy per rank (pJ)
system.physmem_0.averagePower 996.825615 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.readEnergy 2878200 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.actBackEnergy 15819210 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 295500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 21605295 # Total energy per rank (pJ)
system.physmem_1.averagePower 914.703429 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 407500 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.memoryStateTime::ACT 22446250 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.branchPred.lookups 7026 # Number of BP lookups
system.cpu.branchPred.condPredicted 3965 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1425 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 5143 # Number of BTB lookups
system.cpu.branchPred.BTBHits 872 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.branchPred.BTBHitPct 16.955085 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1033 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.read_hits 4832 # DTB read hits
system.cpu.dtb.read_misses 93 # DTB read misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.read_accesses 4925 # DTB read accesses
system.cpu.dtb.write_hits 2065 # DTB write hits
system.cpu.dtb.write_misses 72 # DTB write misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.write_accesses 2137 # DTB write accesses
system.cpu.dtb.data_hits 6897 # DTB hits
system.cpu.dtb.data_misses 165 # DTB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dtb.data_accesses 7062 # DTB accesses
system.cpu.itb.fetch_hits 5266 # ITB hits
system.cpu.itb.fetch_misses 59 # ITB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.itb.fetch_accesses 5325 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.numCycles 49521 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.icacheStallCycles 1262 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 39496 # Number of instructions fetch has processed
system.cpu.fetch.Branches 7026 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1905 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 11647 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1505 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 695 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 5266 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 809 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 28518 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.384950 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.783550 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.rateDist::0 21883 76.73% 76.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 531 1.86% 78.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 405 1.42% 80.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 525 1.84% 81.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 527 1.85% 83.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 419 1.47% 85.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 492 1.73% 86.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 463 1.62% 88.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 3273 11.48% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.rateDist::total 28518 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.141879 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.797561 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 38016 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 11989 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 5115 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 629 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1147 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 585 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 376 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 32323 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 785 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1147 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 38621 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 5295 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1200 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 5143 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5490 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 30197 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 302 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 566 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 4493 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 22785 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 37650 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 37632 # Number of integer rename lookups
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.rename.UndoneMaps 13645 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 56 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2153 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2897 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1434 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 31 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 21 # Number of conflicting stores.
system.cpu.memDep1.insertedLoads 2813 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep1.insertedStores 1365 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.iqInstsAdded 26855 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 22315 # Number of instructions issued
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.iqSquashedInstsExamined 14161 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 28518 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.782488 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.503369 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.issued_per_cycle::0 20180 70.76% 70.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 2624 9.20% 79.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1911 6.70% 86.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1348 4.73% 91.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1241 4.35% 95.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 673 2.36% 98.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 344 1.21% 99.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 144 0.50% 99.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 53 0.19% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.issued_per_cycle::total 28518 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.fu_full::IntAlu 33 9.65% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 224 65.50% 75.15% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 85 24.85% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::IntAlu 7386 65.50% 65.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2741 24.31% 89.85% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1144 10.15% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::total 11276 # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_1::IntAlu 7337 66.46% 66.48% # Type of FU issued
system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.49% # Type of FU issued
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.49% # Type of FU issued
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued
system.cpu.iq.FU_type_1::MemRead 2570 23.28% 89.79% # Type of FU issued
system.cpu.iq.FU_type_1::MemWrite 1127 10.21% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_1::total 11039 # Type of FU issued
system.cpu.iq.FU_type::total 22315 0.00% 0.00% # Type of FU issued
system.cpu.iq.rate 0.450617 # Inst issue rate
system.cpu.iq.fu_busy_cnt::0 168 # FU busy when requested
system.cpu.iq.fu_busy_cnt::1 174 # FU busy when requested
system.cpu.iq.fu_busy_cnt::total 342 # FU busy when requested
system.cpu.iq.fu_busy_rate::0 0.007529 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::1 0.007797 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total 0.015326 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 73550 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 41081 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19615 # Number of integer instruction queue wakeup accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.int_alu_accesses 22631 # Number of integer alu accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1714 # Number of loads squashed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 569 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 342 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread1.forwLoads 63 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread1.squashedLoads 1630 # Number of loads squashed
system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations
system.cpu.iew.lsq.thread1.squashedStores 500 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread1.cacheBlocked 278 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewSquashCycles 1147 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2841 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 538 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 27054 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 353 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 5710 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2799 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 505 # Number of times the LSQ has become full, causing a stall
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1136 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1278 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 21041 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0 2537 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::1 2397 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::total 4934 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1274 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.exec_nop::0 74 # number of nop insts executed
system.cpu.iew.exec_nop::1 74 # number of nop insts executed
system.cpu.iew.exec_nop::total 148 # number of nop insts executed
system.cpu.iew.exec_refs::0 3628 # number of memory reference insts executed
system.cpu.iew.exec_refs::1 3464 # number of memory reference insts executed
system.cpu.iew.exec_refs::total 7092 # number of memory reference insts executed
system.cpu.iew.exec_branches::0 1676 # Number of branches executed
system.cpu.iew.exec_branches::1 1656 # Number of branches executed
system.cpu.iew.exec_branches::total 3332 # Number of branches executed
system.cpu.iew.exec_stores::0 1091 # Number of stores executed
system.cpu.iew.exec_stores::1 1067 # Number of stores executed
system.cpu.iew.exec_stores::total 2158 # Number of stores executed
system.cpu.iew.exec_rate 0.424890 # Inst execution rate
system.cpu.iew.wb_sent::0 10100 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::1 9901 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::total 20001 # cumulative count of insts sent to commit
system.cpu.iew.wb_count::0 9896 # cumulative count of insts written-back
system.cpu.iew.wb_count::1 9739 # cumulative count of insts written-back
system.cpu.iew.wb_count::total 19635 # cumulative count of insts written-back
system.cpu.iew.wb_producers::0 5244 # num instructions producing a value
system.cpu.iew.wb_producers::1 5132 # num instructions producing a value
system.cpu.iew.wb_producers::total 10376 # num instructions producing a value
system.cpu.iew.wb_consumers::0 6970 # num instructions consuming a value
system.cpu.iew.wb_consumers::1 6831 # num instructions consuming a value
system.cpu.iew.wb_consumers::total 13801 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.wb_rate::0 0.199834 # insts written-back per cycle
system.cpu.iew.wb_rate::1 0.196664 # insts written-back per cycle
system.cpu.iew.wb_rate::total 0.396498 # insts written-back per cycle
system.cpu.iew.wb_fanout::0 0.752367 # average fanout of values written-back
system.cpu.iew.wb_fanout::1 0.751281 # average fanout of values written-back
system.cpu.iew.wb_fanout::total 0.751830 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.commitSquashedInsts 14269 # The number of squashed insts skipped by commit
add SMT hello world test - 2 threads --HG-- extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df
2006-10-06 10:23:27 +02:00
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.branchMispredicts 1068 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 28453 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.449091 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.311891 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.committed_per_cycle::0 23365 82.12% 82.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 2421 8.51% 90.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1102 3.87% 94.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 384 1.35% 95.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 323 1.14% 96.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 209 0.73% 97.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 206 0.72% 98.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 116 0.41% 98.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 327 1.15% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.committed_per_cycle::total 28453 # Number of insts commited each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedInsts::1 6389 # Number of instructions committed
system.cpu.commit.committedInsts::total 12778 # Number of instructions committed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::total 12778 # Number of ops (including micro ops) committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.refs::0 2048 # Number of memory references committed
system.cpu.commit.refs::1 2048 # Number of memory references committed
system.cpu.commit.refs::total 4096 # Number of memory references committed
system.cpu.commit.loads::0 1183 # Number of loads committed
system.cpu.commit.loads::1 1183 # Number of loads committed
system.cpu.commit.loads::total 2366 # Number of loads committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars::0 0 # Number of memory barriers committed
system.cpu.commit.membars::1 0 # Number of memory barriers committed
system.cpu.commit.membars::total 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches::0 1050 # Number of branches committed
system.cpu.commit.branches::1 1050 # Number of branches committed
system.cpu.commit.branches::total 2100 # Number of branches committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_1::IntAlu 4319 67.60% 67.90% # Class of committed instruction
system.cpu.commit.op_class_1::IntMult 1 0.02% 67.91% # Class of committed instruction
system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.91% # Class of committed instruction
system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_1::MemRead 1183 18.52% 86.46% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_1::total 6389 # Class of committed instruction
system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.bw_lim_events 327 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 131668 # The number of ROB reads
system.cpu.rob.rob_writes 56750 # The number of ROB writes
system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 21003 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
system.cpu.committedInsts::total 12744 # Number of Instructions Simulated
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.cpi::0 7.771657 # CPI: Cycles Per Instruction
system.cpu.cpi::1 7.771657 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.885829 # CPI: Total CPI of All Threads
system.cpu.ipc::0 0.128673 # IPC: Instructions Per Cycle
system.cpu.ipc::1 0.128673 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.257345 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 26413 # number of integer regfile reads
system.cpu.int_regfile_writes 14990 # number of integer regfile writes
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.tagsinuse 213.559941 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4863 # Total number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.sampled_refs 346 # Sample count of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.avg_refs 14.054913 # Average number of references to valid blocks.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 213.559941 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.052139 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.052139 # Average percentage of cache occupancy
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.084473 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.tag_accesses 12116 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 12116 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 3840 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3840 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1023 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1023 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 4863 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4863 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4863 # number of overall hits
system.cpu.dcache.overall_hits::total 4863 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 707 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 707 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1022 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1022 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1022 # number of overall misses
system.cpu.dcache.overall_misses::total 1022 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24108500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24108500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 53981926 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 53981926 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 78090426 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 78090426 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 78090426 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 78090426 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 4155 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 4155 # number of ReadReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_accesses::cpu.data 5885 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 5885 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 5885 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 5885 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075812 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.075812 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408671 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.408671 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.173662 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.173662 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.173662 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.173662 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76534.920635 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 76534.920635 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76353.502122 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76353.502122 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76409.418787 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76409.418787 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76409.418787 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76409.418787 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 6161 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.blocked::no_mshrs 133 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.323308 # average number of cycles each access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 114 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 114 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 676 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 676 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 676 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 676 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 346 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17596000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17596000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12625989 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12625989 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30221989 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 30221989 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30221989 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 30221989 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048375 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048375 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058794 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.058794 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058794 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.058794 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87542.288557 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87542.288557 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87075.786207 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87075.786207 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87346.789017 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 87346.789017 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87346.789017 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 87346.789017 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.replacements::0 8 # number of replacements
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements::1 0 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.replacements::total 8 # number of replacements
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.tagsinuse 319.520873 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4318 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 636 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.789308 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 319.520873 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.156016 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.156016 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 628 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.306641 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11148 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11148 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 4318 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4318 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4318 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4318 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4318 # number of overall hits
system.cpu.icache.overall_hits::total 4318 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 938 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 938 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 938 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 938 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 938 # number of overall misses
system.cpu.icache.overall_misses::total 938 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 69872996 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 69872996 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 69872996 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 69872996 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 69872996 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 69872996 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5256 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5256 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5256 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5256 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5256 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5256 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.178463 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.178463 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.178463 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.178463 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.178463 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.178463 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74491.466951 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 74491.466951 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74491.466951 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 74491.466951 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74491.466951 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 74491.466951 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 3812 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.blocked::no_mshrs 79 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 48.253165 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 302 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 302 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 302 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 302 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 302 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 636 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 636 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 636 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 636 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 636 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 636 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51565998 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 51565998 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51565998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 51565998 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51565998 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 51565998 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.121005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.121005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.121005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.121005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.121005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.121005 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81078.613208 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81078.613208 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81078.613208 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 81078.613208 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81078.613208 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 81078.613208 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.tagsinuse 440.180388 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 835 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.011976 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 320.217581 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 119.962806 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009772 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003661 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.013433 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 835 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 322 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025482 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 8900 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 8900 # Number of data accesses
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 634 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 634 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 201 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 201 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 634 # number of demand (read+write) misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_misses::cpu.data 346 # number of demand (read+write) misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_misses::total 980 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 634 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_misses::cpu.data 346 # number of overall misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_misses::total 980 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12401500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12401500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 50585000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 50585000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17285500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17285500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 50585000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 29687000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 80272000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 50585000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 29687000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 80272000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 636 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 636 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 201 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 201 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 636 # number of demand (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 346 # number of demand (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_accesses::total 982 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 636 # number of overall (read+write) accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 346 # number of overall (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_accesses::total 982 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996855 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996855 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996855 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996855 # miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85527.586207 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85527.586207 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79787.066246 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79787.066246 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85997.512438 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85997.512438 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79787.066246 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85800.578035 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81910.204082 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79787.066246 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85800.578035 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81910.204082 # average overall miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 634 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 634 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 201 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 201 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 634 # number of demand (read+write) MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_mshr_misses::total 980 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_misses::total 980 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10951500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10951500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44245000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44245000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15275500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15275500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44245000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26227000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 70472000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44245000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26227000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 70472000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996855 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996855 # mshr miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75527.586207 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75527.586207 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69787.066246 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69787.066246 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75997.512438 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75997.512438 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69787.066246 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75800.578035 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71910.204082 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69787.066246 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75800.578035 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71910.204082 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 837 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 636 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 201 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1280 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.pkt_count::total 1972 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.pkt_size::total 62848 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 990 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::1 990 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::total 990 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 495000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 954000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 519000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
system.membus.trans_dist::ReadResp 835 # Transaction distribution
system.membus.trans_dist::ReadExReq 145 # Transaction distribution
system.membus.trans_dist::ReadExResp 145 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 835 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1960 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1960 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62720 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 62720 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::samples 980 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::0 980 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::total 980 # Request fanout histogram
system.membus.reqLayer0.occupancy 1192500 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 4.8 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer1.occupancy 5223750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 21.1 # Layer utilization (%)
add SMT hello world test - 2 threads --HG-- extra : convert_revision : 54cb19d1325295895b6f0b992499bbb0216b45df
2006-10-06 10:23:27 +02:00
---------- End Simulation Statistics ----------
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